1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <wait_bit.h> 10 #include <dm.h> 11 #include <reset-uclass.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <dt-bindings/reset/stih407-resets.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 struct sti_reset { 19 const struct syscfg_reset_controller_data *data; 20 }; 21 22 /** 23 * Reset channel description for a system configuration register based 24 * reset controller. 25 * 26 * @compatible: Compatible string of the syscon containing this 27 * channel's control and ack (status) bits. 28 * @reset_offset: Reset register offset in sysconf bank. 29 * @reset_bit: Bit number in reset register. 30 * @ack_offset: Ack reset register offset in syscon bank. 31 * @ack_bit: Bit number in Ack reset register. 32 * @deassert_cnt: incremented when reset is deasserted, reset can only be 33 * asserted when equal to 0 34 */ 35 36 struct syscfg_reset_channel_data { 37 const char *compatible; 38 int reset_offset; 39 int reset_bit; 40 int ack_offset; 41 int ack_bit; 42 int deassert_cnt; 43 }; 44 45 /** 46 * Description of a system configuration register based reset controller. 47 * 48 * @wait_for_ack: The controller will wait for reset assert and de-assert to 49 * be "ack'd" in a channel's ack field. 50 * @active_low: Are the resets in this controller active low, i.e. clearing 51 * the reset bit puts the hardware into reset. 52 * @nr_channels: The number of reset channels in this controller. 53 * @channels: An array of reset channel descriptions. 54 */ 55 struct syscfg_reset_controller_data { 56 bool wait_for_ack; 57 bool active_low; 58 int nr_channels; 59 struct syscfg_reset_channel_data *channels; 60 }; 61 62 /* STiH407 Peripheral powerdown definitions. */ 63 static const char stih407_core[] = "st,stih407-core-syscfg"; 64 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg"; 65 static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; 66 67 #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \ 68 { .compatible = _c, \ 69 .reset_offset = _rr, \ 70 .reset_bit = _rb, \ 71 .ack_offset = _ar, \ 72 .ack_bit = _ab, } 73 74 #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \ 75 { .compatible = _c, \ 76 .reset_offset = _rr, \ 77 .reset_bit = _rb, } 78 79 #define STIH407_SRST_CORE(_reg, _bit) \ 80 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) 81 82 #define STIH407_SRST_SBC(_reg, _bit) \ 83 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) 84 85 #define STIH407_SRST_LPM(_reg, _bit) \ 86 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) 87 88 #define STIH407_PDN_0(_bit) \ 89 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) 90 #define STIH407_PDN_1(_bit) \ 91 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) 92 #define STIH407_PDN_ETH(_bit, _stat) \ 93 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) 94 95 /* Powerdown requests control 0 */ 96 #define SYSCFG_5000 0x0 97 #define SYSSTAT_5500 0x7d0 98 /* Powerdown requests control 1 (High Speed Links) */ 99 #define SYSCFG_5001 0x4 100 #define SYSSTAT_5501 0x7d4 101 102 /* Ethernet powerdown/status/reset */ 103 #define SYSCFG_4032 0x80 104 #define SYSSTAT_4520 0x820 105 #define SYSCFG_4002 0x8 106 107 static struct syscfg_reset_channel_data stih407_powerdowns[] = { 108 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), 109 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), 110 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), 111 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), 112 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), 113 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), 114 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), 115 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), 116 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), 117 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), 118 }; 119 120 /* Reset Generator control 0/1 */ 121 #define SYSCFG_5128 0x200 122 #define SYSCFG_5131 0x20c 123 #define SYSCFG_5132 0x210 124 125 #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ 126 127 static struct syscfg_reset_channel_data stih407_softresets[] = { 128 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), 129 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), 130 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), 131 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), 132 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), 133 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), 134 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), 135 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), 136 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), 137 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), 138 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), 139 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), 140 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), 141 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), 142 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), 143 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), 144 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), 145 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), 146 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), 147 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), 148 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), 149 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), 150 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), 151 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), 152 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), 153 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), 154 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), 155 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), 156 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), 157 [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26), 158 [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27), 159 [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28), 160 [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2), 161 }; 162 163 /* PicoPHY reset/control */ 164 #define SYSCFG_5061 0x0f4 165 166 static struct syscfg_reset_channel_data stih407_picophyresets[] = { 167 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), 168 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), 169 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), 170 }; 171 172 static const struct 173 syscfg_reset_controller_data stih407_powerdown_controller = { 174 .wait_for_ack = true, 175 .nr_channels = ARRAY_SIZE(stih407_powerdowns), 176 .channels = stih407_powerdowns, 177 }; 178 179 static const struct 180 syscfg_reset_controller_data stih407_softreset_controller = { 181 .wait_for_ack = false, 182 .active_low = true, 183 .nr_channels = ARRAY_SIZE(stih407_softresets), 184 .channels = stih407_softresets, 185 }; 186 187 static const struct 188 syscfg_reset_controller_data stih407_picophyreset_controller = { 189 .wait_for_ack = false, 190 .nr_channels = ARRAY_SIZE(stih407_picophyresets), 191 .channels = stih407_picophyresets, 192 }; 193 194 phys_addr_t sti_reset_get_regmap(const char *compatible) 195 { 196 struct udevice *syscon; 197 struct regmap *regmap; 198 int node, ret; 199 200 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 201 compatible); 202 if (node < 0) { 203 pr_err("unable to find %s node\n", compatible); 204 return node; 205 } 206 207 ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon); 208 if (ret) { 209 pr_err("%s: uclass_get_device_by_of_offset failed: %d\n", 210 __func__, ret); 211 return ret; 212 } 213 214 regmap = syscon_get_regmap(syscon); 215 if (!regmap) { 216 pr_err("unable to get regmap for %s\n", syscon->name); 217 return -ENODEV; 218 } 219 220 return regmap->ranges[0].start; 221 } 222 223 static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert) 224 { 225 struct udevice *dev = reset_ctl->dev; 226 struct syscfg_reset_controller_data *reset_desc = 227 (struct syscfg_reset_controller_data *)(dev->driver_data); 228 struct syscfg_reset_channel_data *ch; 229 phys_addr_t base; 230 u32 ctrl_val = reset_desc->active_low ? !assert : !!assert; 231 void __iomem *reg; 232 233 /* check if reset id is inside available range */ 234 if (reset_ctl->id >= reset_desc->nr_channels) 235 return -EINVAL; 236 237 /* get reset sysconf register base address */ 238 base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible); 239 240 ch = &reset_desc->channels[reset_ctl->id]; 241 242 /* check the deassert counter to assert reset when it reaches 0 */ 243 if (!assert) { 244 ch->deassert_cnt++; 245 if (ch->deassert_cnt > 1) 246 return 0; 247 } else { 248 if (ch->deassert_cnt > 0) { 249 ch->deassert_cnt--; 250 if (ch->deassert_cnt > 0) 251 return 0; 252 } else 253 pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n", 254 reset_ctl, reset_ctl->dev, reset_ctl->id); 255 } 256 257 reg = (void __iomem *)base + ch->reset_offset; 258 259 if (ctrl_val) 260 generic_set_bit(ch->reset_bit, reg); 261 else 262 generic_clear_bit(ch->reset_bit, reg); 263 264 if (!reset_desc->wait_for_ack) 265 return 0; 266 267 reg = (void __iomem *)base + ch->ack_offset; 268 if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val, 269 1000, false)) { 270 pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n", 271 reset_ctl, reset_ctl->dev, reset_ctl->id); 272 273 return -ETIMEDOUT; 274 } 275 276 return 0; 277 } 278 279 static int sti_reset_request(struct reset_ctl *reset_ctl) 280 { 281 return 0; 282 } 283 284 static int sti_reset_free(struct reset_ctl *reset_ctl) 285 { 286 return 0; 287 } 288 289 static int sti_reset_assert(struct reset_ctl *reset_ctl) 290 { 291 return sti_reset_program_hw(reset_ctl, true); 292 } 293 294 static int sti_reset_deassert(struct reset_ctl *reset_ctl) 295 { 296 return sti_reset_program_hw(reset_ctl, false); 297 } 298 299 struct reset_ops sti_reset_ops = { 300 .request = sti_reset_request, 301 .free = sti_reset_free, 302 .rst_assert = sti_reset_assert, 303 .rst_deassert = sti_reset_deassert, 304 }; 305 306 static int sti_reset_probe(struct udevice *dev) 307 { 308 struct sti_reset *priv = dev_get_priv(dev); 309 310 priv->data = (void *)dev_get_driver_data(dev); 311 312 return 0; 313 } 314 315 static const struct udevice_id sti_reset_ids[] = { 316 { 317 .compatible = "st,stih407-picophyreset", 318 .data = (ulong)&stih407_picophyreset_controller, 319 }, 320 { 321 .compatible = "st,stih407-powerdown", 322 .data = (ulong)&stih407_powerdown_controller, 323 }, 324 { 325 .compatible = "st,stih407-softreset", 326 .data = (ulong)&stih407_softreset_controller, 327 }, 328 { } 329 }; 330 331 U_BOOT_DRIVER(sti_reset) = { 332 .name = "sti_reset", 333 .id = UCLASS_RESET, 334 .of_match = sti_reset_ids, 335 .probe = sti_reset_probe, 336 .priv_auto_alloc_size = sizeof(struct sti_reset), 337 .ops = &sti_reset_ops, 338 }; 339