1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <misc.h> 9 #include <reset.h> 10 #include <reset-uclass.h> 11 #include <wdt.h> 12 #include <asm/io.h> 13 #include <asm/arch/wdt.h> 14 #include <asm/arch/scu_ast2500.h> 15 16 struct ast2500_reset_priv { 17 /* WDT used to perform resets. */ 18 struct udevice *wdt; 19 struct ast2500_scu *scu; 20 }; 21 22 static int ast2500_reset_assert(struct reset_ctl *reset_ctl) 23 { 24 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); 25 struct ast2500_scu *scu = priv->scu; 26 u32 reset_mode, reset_mask; 27 bool reset_sdram; 28 int ret = 0; 29 30 printf("ast2500_reset_assert reset_ctl->id %d \n", reset_ctl->id); 31 /* 32 * To reset SDRAM, a specifal flag in SYSRESET register 33 * needs to be enabled first 34 */ 35 reset_mode = ast_reset_mode_from_flags(reset_ctl->id); 36 reset_mask = ast_reset_mask_from_flags(reset_ctl->id); 37 reset_sdram = reset_mode == WDT_CTRL_RESET_SOC && 38 (reset_mask & WDT_RESET_SDRAM); 39 #if 0 40 if (reset_sdram) { 41 ast_scu_unlock(priv->scu); 42 setbits_le32(&priv->scu->sysreset_ctrl1, 43 SCU_SYSRESET_SDRAM_WDT); 44 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 45 clrbits_le32(&priv->scu->sysreset_ctrl1, 46 SCU_SYSRESET_SDRAM_WDT); 47 ast_scu_lock(priv->scu); 48 } else { 49 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 50 } 51 #endif 52 if(reset_ctl->id >= 32) 53 setbits_le32(scu->sysreset_ctrl1 , BIT(reset_ctl->id - 32)); 54 else 55 setbits_le32(scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 56 57 return ret; 58 } 59 60 static int ast2500_reset_request(struct reset_ctl *reset_ctl) 61 { 62 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, 63 reset_ctl->dev, reset_ctl->id); 64 65 return 0; 66 } 67 68 static int ast2500_reset_probe(struct udevice *dev) 69 { 70 struct ast2500_reset_priv *priv = dev_get_priv(dev); 71 struct udevice *clk_dev; 72 int ret = 0; 73 74 /* find SCU base address from clock device */ 75 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 76 &clk_dev); 77 if (ret) { 78 debug("clock device not found\n"); 79 return ret; 80 } 81 82 priv->scu = devfdt_get_addr_ptr(clk_dev); 83 if (IS_ERR(priv->scu)) { 84 debug("%s(): can't get SCU\n", __func__); 85 return PTR_ERR(priv->scu); 86 } 87 88 return 0; 89 } 90 static int aspeed_ofdata_to_platdata(struct udevice *dev) 91 { 92 struct ast2500_reset_priv *priv = dev_get_priv(dev); 93 int ret; 94 95 ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt", 96 &priv->wdt); 97 if (ret) { 98 debug("%s: can't find WDT for reset controller", __func__); 99 return ret; 100 } 101 102 return 0; 103 } 104 105 static const struct udevice_id aspeed_reset_ids[] = { 106 { .compatible = "aspeed,ast2500-reset" }, 107 { } 108 }; 109 110 struct reset_ops aspeed_reset_ops = { 111 .rst_assert = ast2500_reset_assert, 112 .request = ast2500_reset_request, 113 }; 114 115 U_BOOT_DRIVER(aspeed_reset) = { 116 .name = "aspeed_reset", 117 .id = UCLASS_RESET, 118 .of_match = aspeed_reset_ids, 119 .probe = ast2500_reset_probe, 120 .ops = &aspeed_reset_ops, 121 .ofdata_to_platdata = aspeed_ofdata_to_platdata, 122 .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv), 123 }; 124