1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <misc.h> 9 #include <reset.h> 10 #include <reset-uclass.h> 11 #include <wdt.h> 12 #include <asm/io.h> 13 #include <asm/arch/wdt.h> 14 #include <asm/arch/scu_ast2500.h> 15 16 struct ast2500_reset_priv { 17 /* WDT used to perform resets. */ 18 struct udevice *wdt; 19 struct ast2500_scu *scu; 20 }; 21 22 static int ast2500_reset_assert(struct reset_ctl *reset_ctl) 23 { 24 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); 25 struct ast2500_scu *scu = priv->scu; 26 // u32 reset_mode, reset_mask; 27 bool reset_sdram; 28 int ret = 0; 29 30 debug("ast2500_reset_assert reset_ctl->id %d \n", reset_ctl->id); 31 /* 32 * To reset SDRAM, a specifal flag in SYSRESET register 33 * needs to be enabled first 34 */ 35 #if 0 36 reset_mode = ast_reset_mode_from_flags(reset_ctl->id); 37 reset_mask = ast_reset_mask_from_flags(reset_ctl->id); 38 reset_sdram = reset_mode == WDT_CTRL_RESET_SOC && 39 (reset_mask & WDT_RESET_SDRAM); 40 41 if (reset_sdram) { 42 ast_scu_unlock(priv->scu); 43 setbits_le32(&priv->scu->sysreset_ctrl1, 44 SCU_SYSRESET_SDRAM_WDT); 45 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 46 clrbits_le32(&priv->scu->sysreset_ctrl1, 47 SCU_SYSRESET_SDRAM_WDT); 48 ast_scu_lock(priv->scu); 49 } else { 50 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 51 } 52 #endif 53 if(reset_ctl->id >= 32) 54 setbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 55 else 56 setbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 57 58 return ret; 59 } 60 61 static int ast2500_reset_deassert(struct reset_ctl *reset_ctl) 62 { 63 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev); 64 struct ast2500_scu *scu = priv->scu; 65 u32 reset_mode, reset_mask; 66 bool reset_sdram; 67 int ret = 0; 68 69 debug("ast2500_reset_deassert reset_ctl->id %d \n", reset_ctl->id); 70 71 if(reset_ctl->id >= 32) 72 clrbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 73 else 74 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 75 76 return ret; 77 } 78 79 static int ast2500_reset_request(struct reset_ctl *reset_ctl) 80 { 81 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, 82 reset_ctl->dev, reset_ctl->id); 83 84 return 0; 85 } 86 87 static int ast2500_reset_probe(struct udevice *dev) 88 { 89 struct ast2500_reset_priv *priv = dev_get_priv(dev); 90 struct udevice *clk_dev; 91 int ret = 0; 92 93 /* find SCU base address from clock device */ 94 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 95 &clk_dev); 96 if (ret) { 97 debug("clock device not found\n"); 98 return ret; 99 } 100 101 priv->scu = devfdt_get_addr_ptr(clk_dev); 102 if (IS_ERR(priv->scu)) { 103 debug("%s(): can't get SCU\n", __func__); 104 return PTR_ERR(priv->scu); 105 } 106 107 return 0; 108 } 109 110 static int ast2500_ofdata_to_platdata(struct udevice *dev) 111 { 112 struct ast2500_reset_priv *priv = dev_get_priv(dev); 113 int ret; 114 115 ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt", 116 &priv->wdt); 117 if (ret) { 118 debug("%s: can't find WDT for reset controller", __func__); 119 return ret; 120 } 121 122 return 0; 123 } 124 125 static const struct udevice_id aspeed_reset_ids[] = { 126 { .compatible = "aspeed,ast2500-reset" }, 127 { } 128 }; 129 130 struct reset_ops aspeed_reset_ops = { 131 .rst_assert = ast2500_reset_assert, 132 .rst_deassert = ast2500_reset_deassert, 133 .request = ast2500_reset_request, 134 }; 135 136 U_BOOT_DRIVER(aspeed_reset) = { 137 .name = "aspeed_reset", 138 .id = UCLASS_RESET, 139 .of_match = aspeed_reset_ids, 140 .probe = ast2500_reset_probe, 141 .ops = &aspeed_reset_ops, 142 .ofdata_to_platdata = ast2500_ofdata_to_platdata, 143 .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv), 144 }; 145