1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <common.h> 4 #include <dm.h> 5 #include <misc.h> 6 #include <reset.h> 7 #include <reset-uclass.h> 8 #include <wdt.h> 9 #include <asm/io.h> 10 #include <asm/arch/scu_ast2400.h> 11 12 struct ast2400_reset_priv { 13 /* WDT used to perform resets. */ 14 struct udevice *wdt; 15 struct ast2400_scu *scu; 16 }; 17 18 static int ast2400_reset_deassert(struct reset_ctl *reset_ctl) 19 { 20 struct ast2400_reset_priv *priv = dev_get_priv(reset_ctl->dev); 21 struct ast2400_scu *scu = priv->scu; 22 int ret = 0; 23 24 debug("ast2400_reset_deassert reset_ctl->id %ld \n", reset_ctl->id); 25 26 if(reset_ctl->id >= 32) 27 clrbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 28 else 29 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 30 31 return ret; 32 } 33 34 static int ast2400_reset_assert(struct reset_ctl *reset_ctl) 35 { 36 struct ast2400_reset_priv *priv = dev_get_priv(reset_ctl->dev); 37 struct ast2400_scu *scu = priv->scu; 38 // u32 reset_mode, reset_mask; 39 // bool reset_sdram; 40 int ret = 0; 41 42 debug("ast2400_reset_assert reset_ctl->id %ld \n", reset_ctl->id); 43 /* 44 * To reset SDRAM, a specifal flag in SYSRESET register 45 * needs to be enabled first 46 */ 47 #if 0 48 reset_mode = ast_reset_mode_from_flags(reset_ctl->id); 49 reset_mask = ast_reset_mask_from_flags(reset_ctl->id); 50 reset_sdram = reset_mode == WDT_CTRL_RESET_SOC && 51 (reset_mask & WDT_RESET_SDRAM); 52 53 if (reset_sdram) { 54 ast_scu_unlock(priv->scu); 55 setbits_le32(&priv->scu->sysreset_ctrl1, 56 SCU_SYSRESET_SDRAM_WDT); 57 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 58 clrbits_le32(&priv->scu->sysreset_ctrl1, 59 SCU_SYSRESET_SDRAM_WDT); 60 ast_scu_lock(priv->scu); 61 } else { 62 ret = wdt_expire_now(priv->wdt, reset_ctl->id); 63 } 64 #endif 65 if(reset_ctl->id >= 32) 66 setbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); 67 else 68 setbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); 69 70 return ret; 71 } 72 73 74 static int ast2400_reset_request(struct reset_ctl *reset_ctl) 75 { 76 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, 77 reset_ctl->dev, reset_ctl->id); 78 79 return 0; 80 } 81 82 static int ast2400_reset_probe(struct udevice *dev) 83 { 84 struct ast2400_reset_priv *priv = dev_get_priv(dev); 85 struct udevice *clk_dev; 86 int ret = 0; 87 88 /* find SCU base address from clock device */ 89 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 90 &clk_dev); 91 if (ret) { 92 debug("clock device not found\n"); 93 return ret; 94 } 95 96 priv->scu = devfdt_get_addr_ptr(clk_dev); 97 if (IS_ERR(priv->scu)) { 98 debug("%s(): can't get SCU\n", __func__); 99 return PTR_ERR(priv->scu); 100 } 101 102 return 0; 103 } 104 105 static int ast2400_ofdata_to_platdata(struct udevice *dev) 106 { 107 struct ast2400_reset_priv *priv = dev_get_priv(dev); 108 int ret; 109 110 ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt", 111 &priv->wdt); 112 if (ret) { 113 debug("%s: can't find WDT for reset controller", __func__); 114 return ret; 115 } 116 117 return 0; 118 } 119 120 static const struct udevice_id aspeed_reset_ids[] = { 121 { .compatible = "aspeed,ast2400-reset" }, 122 { } 123 }; 124 125 struct reset_ops aspeed_reset_ops = { 126 .rst_assert = ast2400_reset_assert, 127 .rst_deassert = ast2400_reset_deassert, 128 .request = ast2400_reset_request, 129 }; 130 131 U_BOOT_DRIVER(aspeed_reset) = { 132 .name = "aspeed_reset", 133 .id = UCLASS_RESET, 134 .of_match = aspeed_reset_ids, 135 .probe = ast2400_reset_probe, 136 .ops = &aspeed_reset_ops, 137 .ofdata_to_platdata = ast2400_ofdata_to_platdata, 138 .priv_auto_alloc_size = sizeof(struct ast2400_reset_priv), 139 }; 140