xref: /openbmc/u-boot/drivers/reset/Kconfig (revision d891ab95)
1menu "Reset Controller Support"
2
3config DM_RESET
4	bool "Enable reset controllers using Driver Model"
5	depends on DM && OF_CONTROL
6	help
7	  Enable support for the reset controller driver class. Many hardware
8	  modules are equipped with a reset signal, typically driven by some
9	  reset controller hardware module within the chip. In U-Boot, reset
10	  controller drivers allow control over these reset signals. In some
11	  cases this API is applicable to chips outside the CPU as well,
12	  although driving such reset isgnals using GPIOs may be more
13	  appropriate in this case.
14
15config SANDBOX_RESET
16	bool "Enable the sandbox reset test driver"
17	depends on DM_MAILBOX && SANDBOX
18	help
19	  Enable support for a test reset controller implementation, which
20	  simply accepts requests to reset various HW modules without actually
21	  doing anything beyond a little error checking.
22
23config STI_RESET
24	bool "Enable the STi reset"
25	depends on ARCH_STI
26	help
27	  Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28	  Say Y if you want to control reset signals provided by system config
29	  block.
30
31config TEGRA_CAR_RESET
32	bool "Enable Tegra CAR-based reset driver"
33	depends on TEGRA_CAR
34	help
35	  Enable support for manipulating Tegra's on-SoC reset signals via
36	  direct register access to the Tegra CAR (Clock And Reset controller).
37
38config TEGRA186_RESET
39	bool "Enable Tegra186 BPMP-based reset driver"
40	depends on TEGRA186_BPMP
41	help
42	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
43	  requests to the BPMP (Boot and Power Management Processor).
44
45config RESET_UNIPHIER
46	bool "Reset controller driver for UniPhier SoCs"
47	depends on ARCH_UNIPHIER
48	default y
49	help
50	  Support for reset controllers on UniPhier SoCs.
51	  Say Y if you want to control reset signals provided by System Control
52	  block, Media I/O block, Peripheral Block.
53
54endmenu
55