189c1e2daSStephen Warrenmenu "Reset Controller Support" 289c1e2daSStephen Warren 389c1e2daSStephen Warrenconfig DM_RESET 489c1e2daSStephen Warren bool "Enable reset controllers using Driver Model" 589c1e2daSStephen Warren depends on DM && OF_CONTROL 689c1e2daSStephen Warren help 789c1e2daSStephen Warren Enable support for the reset controller driver class. Many hardware 889c1e2daSStephen Warren modules are equipped with a reset signal, typically driven by some 989c1e2daSStephen Warren reset controller hardware module within the chip. In U-Boot, reset 1089c1e2daSStephen Warren controller drivers allow control over these reset signals. In some 1189c1e2daSStephen Warren cases this API is applicable to chips outside the CPU as well, 1289c1e2daSStephen Warren although driving such reset isgnals using GPIOs may be more 1389c1e2daSStephen Warren appropriate in this case. 1489c1e2daSStephen Warren 154581b717SStephen Warrenconfig SANDBOX_RESET 164581b717SStephen Warren bool "Enable the sandbox reset test driver" 174581b717SStephen Warren depends on DM_MAILBOX && SANDBOX 184581b717SStephen Warren help 194581b717SStephen Warren Enable support for a test reset controller implementation, which 204581b717SStephen Warren simply accepts requests to reset various HW modules without actually 214581b717SStephen Warren doing anything beyond a little error checking. 224581b717SStephen Warren 23*fe60f06dSStephen Warrenconfig TEGRA_CAR_RESET 24*fe60f06dSStephen Warren bool "Enable Tegra CAR-based reset driver" 25*fe60f06dSStephen Warren depends on TEGRA_CAR 26*fe60f06dSStephen Warren help 27*fe60f06dSStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via 28*fe60f06dSStephen Warren direct register access to the Tegra CAR (Clock And Reset controller). 29*fe60f06dSStephen Warren 304dd99d14SStephen Warrenconfig TEGRA186_RESET 314dd99d14SStephen Warren bool "Enable Tegra186 BPMP-based reset driver" 324dd99d14SStephen Warren depends on TEGRA186_BPMP 334dd99d14SStephen Warren help 344dd99d14SStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via IPC 354dd99d14SStephen Warren requests to the BPMP (Boot and Power Management Processor). 364dd99d14SStephen Warren 3789c1e2daSStephen Warrenendmenu 38