189c1e2daSStephen Warrenmenu "Reset Controller Support" 289c1e2daSStephen Warren 389c1e2daSStephen Warrenconfig DM_RESET 489c1e2daSStephen Warren bool "Enable reset controllers using Driver Model" 589c1e2daSStephen Warren depends on DM && OF_CONTROL 689c1e2daSStephen Warren help 789c1e2daSStephen Warren Enable support for the reset controller driver class. Many hardware 889c1e2daSStephen Warren modules are equipped with a reset signal, typically driven by some 989c1e2daSStephen Warren reset controller hardware module within the chip. In U-Boot, reset 1089c1e2daSStephen Warren controller drivers allow control over these reset signals. In some 1189c1e2daSStephen Warren cases this API is applicable to chips outside the CPU as well, 1289c1e2daSStephen Warren although driving such reset isgnals using GPIOs may be more 1389c1e2daSStephen Warren appropriate in this case. 1489c1e2daSStephen Warren 154581b717SStephen Warrenconfig SANDBOX_RESET 164581b717SStephen Warren bool "Enable the sandbox reset test driver" 174581b717SStephen Warren depends on DM_MAILBOX && SANDBOX 184581b717SStephen Warren help 194581b717SStephen Warren Enable support for a test reset controller implementation, which 204581b717SStephen Warren simply accepts requests to reset various HW modules without actually 214581b717SStephen Warren doing anything beyond a little error checking. 224581b717SStephen Warren 23584861ffSPatrice Chotardconfig STI_RESET 24584861ffSPatrice Chotard bool "Enable the STi reset" 25584861ffSPatrice Chotard depends on ARCH_STI 26584861ffSPatrice Chotard help 27584861ffSPatrice Chotard Support for reset controllers on STMicroelectronics STiH407 family SoCs. 28584861ffSPatrice Chotard Say Y if you want to control reset signals provided by system config 29584861ffSPatrice Chotard block. 30584861ffSPatrice Chotard 31fe60f06dSStephen Warrenconfig TEGRA_CAR_RESET 32fe60f06dSStephen Warren bool "Enable Tegra CAR-based reset driver" 33fe60f06dSStephen Warren depends on TEGRA_CAR 34fe60f06dSStephen Warren help 35fe60f06dSStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via 36fe60f06dSStephen Warren direct register access to the Tegra CAR (Clock And Reset controller). 37fe60f06dSStephen Warren 384dd99d14SStephen Warrenconfig TEGRA186_RESET 394dd99d14SStephen Warren bool "Enable Tegra186 BPMP-based reset driver" 404dd99d14SStephen Warren depends on TEGRA186_BPMP 414dd99d14SStephen Warren help 424dd99d14SStephen Warren Enable support for manipulating Tegra's on-SoC reset signals via IPC 434dd99d14SStephen Warren requests to the BPMP (Boot and Power Management Processor). 444dd99d14SStephen Warren 45*18393f70SÁlvaro Fernández Rojasconfig RESET_BCM6345 46*18393f70SÁlvaro Fernández Rojas bool "Reset controller driver for BCM6345" 47*18393f70SÁlvaro Fernández Rojas depends on DM_RESET && ARCH_BMIPS 48*18393f70SÁlvaro Fernández Rojas help 49*18393f70SÁlvaro Fernández Rojas Support reset controller on BCM6345. 50*18393f70SÁlvaro Fernández Rojas 514fb96c48SMasahiro Yamadaconfig RESET_UNIPHIER 524fb96c48SMasahiro Yamada bool "Reset controller driver for UniPhier SoCs" 534fb96c48SMasahiro Yamada depends on ARCH_UNIPHIER 544fb96c48SMasahiro Yamada default y 554fb96c48SMasahiro Yamada help 564fb96c48SMasahiro Yamada Support for reset controllers on UniPhier SoCs. 574fb96c48SMasahiro Yamada Say Y if you want to control reset signals provided by System Control 584fb96c48SMasahiro Yamada block, Media I/O block, Peripheral Block. 594fb96c48SMasahiro Yamada 60858d4976Smaxims@google.comconfig AST2500_RESET 61858d4976Smaxims@google.com bool "Reset controller driver for AST2500 SoCs" 62858d4976Smaxims@google.com depends on DM_RESET && WDT_ASPEED 63858d4976Smaxims@google.com default y if ASPEED_AST2500 64858d4976Smaxims@google.com help 65858d4976Smaxims@google.com Support for reset controller on AST2500 SoC. This controller uses 66858d4976Smaxims@google.com watchdog to reset different peripherals and thus only supports 67858d4976Smaxims@google.com resets that are supported by watchdog. The main limitation though 68858d4976Smaxims@google.com is that some reset signals, like I2C or MISC reset multiple devices. 69858d4976Smaxims@google.com 7089c1e2daSStephen Warrenendmenu 71