1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include "stm32mp1_ddr.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 static const char *const clkname[] = { 19 "ddrc1", 20 "ddrc2", 21 "ddrcapb", 22 "ddrphycapb", 23 "ddrphyc" /* LAST clock => used for get_rate() */ 24 }; 25 26 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) 27 { 28 unsigned long ddrphy_clk; 29 unsigned long ddr_clk; 30 struct clk clk; 31 int ret; 32 int idx; 33 34 for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { 35 ret = clk_get_by_name(priv->dev, clkname[idx], &clk); 36 37 if (!ret) 38 ret = clk_enable(&clk); 39 40 if (ret) { 41 printf("error for %s : %d\n", clkname[idx], ret); 42 return ret; 43 } 44 } 45 46 priv->clk = clk; 47 ddrphy_clk = clk_get_rate(&priv->clk); 48 49 debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", 50 mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); 51 /* max 10% frequency delta */ 52 ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); 53 if (ddr_clk > (mem_speed * 1000 * 100)) { 54 pr_err("DDR expected freq %d MHz, current is %d MHz\n", 55 mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); 56 return -EINVAL; 57 } 58 59 return 0; 60 } 61 62 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) 63 { 64 struct ddr_info *priv = dev_get_priv(dev); 65 int ret, idx; 66 struct clk axidcg; 67 struct stm32mp1_ddr_config config; 68 69 #define PARAM(x, y) \ 70 { x,\ 71 offsetof(struct stm32mp1_ddr_config, y),\ 72 sizeof(config.y) / sizeof(u32)} 73 74 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) 75 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) 76 77 const struct { 78 const char *name; /* name in DT */ 79 const u32 offset; /* offset in config struct */ 80 const u32 size; /* size of parameters */ 81 } param[] = { 82 CTL_PARAM(reg), 83 CTL_PARAM(timing), 84 CTL_PARAM(map), 85 CTL_PARAM(perf), 86 PHY_PARAM(reg), 87 PHY_PARAM(timing), 88 PHY_PARAM(cal) 89 }; 90 91 config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); 92 config.info.size = dev_read_u32_default(dev, "st,mem-size", 0); 93 config.info.name = dev_read_string(dev, "st,mem-name"); 94 if (!config.info.name) { 95 debug("%s: no st,mem-name\n", __func__); 96 return -EINVAL; 97 } 98 printf("RAM: %s\n", config.info.name); 99 100 for (idx = 0; idx < ARRAY_SIZE(param); idx++) { 101 ret = dev_read_u32_array(dev, param[idx].name, 102 (void *)((u32)&config + 103 param[idx].offset), 104 param[idx].size); 105 debug("%s: %s[0x%x] = %d\n", __func__, 106 param[idx].name, param[idx].size, ret); 107 if (ret) { 108 pr_err("%s: Cannot read %s\n", 109 __func__, param[idx].name); 110 return -EINVAL; 111 } 112 } 113 114 ret = clk_get_by_name(dev, "axidcg", &axidcg); 115 if (ret) { 116 debug("%s: Cannot found axidcg\n", __func__); 117 return -EINVAL; 118 } 119 clk_disable(&axidcg); /* disable clock gating during init */ 120 121 stm32mp1_ddr_init(priv, &config); 122 123 clk_enable(&axidcg); /* enable clock gating */ 124 125 /* check size */ 126 debug("%s : get_ram_size(%x, %x)\n", __func__, 127 (u32)priv->info.base, (u32)STM32_DDR_SIZE); 128 129 priv->info.size = get_ram_size((long *)priv->info.base, 130 STM32_DDR_SIZE); 131 132 debug("%s : %x\n", __func__, (u32)priv->info.size); 133 134 /* check memory access for all memory */ 135 if (config.info.size != priv->info.size) { 136 printf("DDR invalid size : 0x%x, expected 0x%x\n", 137 priv->info.size, config.info.size); 138 return -EINVAL; 139 } 140 return 0; 141 } 142 143 static int stm32mp1_ddr_probe(struct udevice *dev) 144 { 145 struct ddr_info *priv = dev_get_priv(dev); 146 struct regmap *map; 147 int ret; 148 149 debug("STM32MP1 DDR probe\n"); 150 priv->dev = dev; 151 152 ret = regmap_init_mem(dev, &map); 153 if (ret) 154 return ret; 155 156 priv->ctl = regmap_get_range(map, 0); 157 priv->phy = regmap_get_range(map, 1); 158 159 priv->rcc = STM32_RCC_BASE; 160 161 priv->info.base = STM32_DDR_BASE; 162 163 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 164 priv->info.size = 0; 165 return stm32mp1_ddr_setup(dev); 166 #else 167 priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0); 168 return 0; 169 #endif 170 } 171 172 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info) 173 { 174 struct ddr_info *priv = dev_get_priv(dev); 175 176 *info = priv->info; 177 178 return 0; 179 } 180 181 static struct ram_ops stm32mp1_ddr_ops = { 182 .get_info = stm32mp1_ddr_get_info, 183 }; 184 185 static const struct udevice_id stm32mp1_ddr_ids[] = { 186 { .compatible = "st,stm32mp1-ddr" }, 187 { } 188 }; 189 190 U_BOOT_DRIVER(ddr_stm32mp1) = { 191 .name = "stm32mp1_ddr", 192 .id = UCLASS_RAM, 193 .of_match = stm32mp1_ddr_ids, 194 .ops = &stm32mp1_ddr_ops, 195 .probe = stm32mp1_ddr_probe, 196 .priv_auto_alloc_size = sizeof(struct ddr_info), 197 }; 198