1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 7 #ifndef _RAM_STM32MP1_DDR_H 8 #define _RAM_STM32MP1_DDR_H 9 10 enum stm32mp1_ddr_interact_step { 11 STEP_DDR_RESET, 12 STEP_CTL_INIT, 13 STEP_PHY_INIT, 14 STEP_DDR_READY, 15 STEP_RUN, 16 }; 17 18 /* DDR CTL and DDR PHY REGISTERS */ 19 struct stm32mp1_ddrctl; 20 struct stm32mp1_ddrphy; 21 22 /** 23 * struct ddr_info 24 * 25 * @dev: pointer for the device 26 * @info: UCLASS RAM information 27 * @ctl: DDR controleur base address 28 * @clk: DDR clock 29 * @phy: DDR PHY base address 30 * @rcc: rcc base address 31 */ 32 struct ddr_info { 33 struct udevice *dev; 34 struct ram_info info; 35 struct clk clk; 36 struct stm32mp1_ddrctl *ctl; 37 struct stm32mp1_ddrphy *phy; 38 u32 rcc; 39 }; 40 41 struct stm32mp1_ddrctrl_reg { 42 u32 mstr; 43 u32 mrctrl0; 44 u32 mrctrl1; 45 u32 derateen; 46 u32 derateint; 47 u32 pwrctl; 48 u32 pwrtmg; 49 u32 hwlpctl; 50 u32 rfshctl0; 51 u32 rfshctl3; 52 u32 crcparctl0; 53 u32 zqctl0; 54 u32 dfitmg0; 55 u32 dfitmg1; 56 u32 dfilpcfg0; 57 u32 dfiupd0; 58 u32 dfiupd1; 59 u32 dfiupd2; 60 u32 dfiphymstr; 61 u32 odtmap; 62 u32 dbg0; 63 u32 dbg1; 64 u32 dbgcmd; 65 u32 poisoncfg; 66 u32 pccfg; 67 68 }; 69 70 struct stm32mp1_ddrctrl_timing { 71 u32 rfshtmg; 72 u32 dramtmg0; 73 u32 dramtmg1; 74 u32 dramtmg2; 75 u32 dramtmg3; 76 u32 dramtmg4; 77 u32 dramtmg5; 78 u32 dramtmg6; 79 u32 dramtmg7; 80 u32 dramtmg8; 81 u32 dramtmg14; 82 u32 odtcfg; 83 }; 84 85 struct stm32mp1_ddrctrl_map { 86 u32 addrmap1; 87 u32 addrmap2; 88 u32 addrmap3; 89 u32 addrmap4; 90 u32 addrmap5; 91 u32 addrmap6; 92 u32 addrmap9; 93 u32 addrmap10; 94 u32 addrmap11; 95 }; 96 97 struct stm32mp1_ddrctrl_perf { 98 u32 sched; 99 u32 sched1; 100 u32 perfhpr1; 101 u32 perflpr1; 102 u32 perfwr1; 103 u32 pcfgr_0; 104 u32 pcfgw_0; 105 u32 pcfgqos0_0; 106 u32 pcfgqos1_0; 107 u32 pcfgwqos0_0; 108 u32 pcfgwqos1_0; 109 u32 pcfgr_1; 110 u32 pcfgw_1; 111 u32 pcfgqos0_1; 112 u32 pcfgqos1_1; 113 u32 pcfgwqos0_1; 114 u32 pcfgwqos1_1; 115 }; 116 117 struct stm32mp1_ddrphy_reg { 118 u32 pgcr; 119 u32 aciocr; 120 u32 dxccr; 121 u32 dsgcr; 122 u32 dcr; 123 u32 odtcr; 124 u32 zq0cr1; 125 u32 dx0gcr; 126 u32 dx1gcr; 127 u32 dx2gcr; 128 u32 dx3gcr; 129 }; 130 131 struct stm32mp1_ddrphy_timing { 132 u32 ptr0; 133 u32 ptr1; 134 u32 ptr2; 135 u32 dtpr0; 136 u32 dtpr1; 137 u32 dtpr2; 138 u32 mr0; 139 u32 mr1; 140 u32 mr2; 141 u32 mr3; 142 }; 143 144 struct stm32mp1_ddrphy_cal { 145 u32 dx0dllcr; 146 u32 dx0dqtr; 147 u32 dx0dqstr; 148 u32 dx1dllcr; 149 u32 dx1dqtr; 150 u32 dx1dqstr; 151 u32 dx2dllcr; 152 u32 dx2dqtr; 153 u32 dx2dqstr; 154 u32 dx3dllcr; 155 u32 dx3dqtr; 156 u32 dx3dqstr; 157 }; 158 159 struct stm32mp1_ddr_info { 160 const char *name; 161 u16 speed; /* in MHZ */ 162 u32 size; /* memory size in byte = col * row * width */ 163 }; 164 165 struct stm32mp1_ddr_config { 166 struct stm32mp1_ddr_info info; 167 struct stm32mp1_ddrctrl_reg c_reg; 168 struct stm32mp1_ddrctrl_timing c_timing; 169 struct stm32mp1_ddrctrl_map c_map; 170 struct stm32mp1_ddrctrl_perf c_perf; 171 struct stm32mp1_ddrphy_reg p_reg; 172 struct stm32mp1_ddrphy_timing p_timing; 173 struct stm32mp1_ddrphy_cal p_cal; 174 }; 175 176 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed); 177 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); 178 void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); 179 void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, 180 u32 rfshctl3, 181 u32 pwrctl); 182 183 void stm32mp1_ddr_init( 184 struct ddr_info *priv, 185 const struct stm32mp1_ddr_config *config); 186 187 int stm32mp1_dump_reg(const struct ddr_info *priv, 188 const char *name); 189 190 void stm32mp1_edit_reg(const struct ddr_info *priv, 191 char *name, 192 char *string); 193 194 int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, 195 const char *name); 196 197 void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, 198 char *name, 199 char *string); 200 201 void stm32mp1_dump_info( 202 const struct ddr_info *priv, 203 const struct stm32mp1_ddr_config *config); 204 205 bool stm32mp1_ddr_interactive( 206 void *priv, 207 enum stm32mp1_ddr_interact_step step, 208 const struct stm32mp1_ddr_config *config); 209 210 #endif 211