1*e70f70aaSPatrick Delaunay /* 2*e70f70aaSPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3*e70f70aaSPatrick Delaunay * 4*e70f70aaSPatrick Delaunay * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5*e70f70aaSPatrick Delaunay */ 6*e70f70aaSPatrick Delaunay 7*e70f70aaSPatrick Delaunay #ifndef _RAM_STM32MP1_DDR_H 8*e70f70aaSPatrick Delaunay #define _RAM_STM32MP1_DDR_H 9*e70f70aaSPatrick Delaunay 10*e70f70aaSPatrick Delaunay enum stm32mp1_ddr_interact_step { 11*e70f70aaSPatrick Delaunay STEP_DDR_RESET, 12*e70f70aaSPatrick Delaunay STEP_CTL_INIT, 13*e70f70aaSPatrick Delaunay STEP_PHY_INIT, 14*e70f70aaSPatrick Delaunay STEP_DDR_READY, 15*e70f70aaSPatrick Delaunay STEP_RUN, 16*e70f70aaSPatrick Delaunay }; 17*e70f70aaSPatrick Delaunay 18*e70f70aaSPatrick Delaunay /* DDR CTL and DDR PHY REGISTERS */ 19*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctl; 20*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy; 21*e70f70aaSPatrick Delaunay 22*e70f70aaSPatrick Delaunay /** 23*e70f70aaSPatrick Delaunay * struct ddr_info 24*e70f70aaSPatrick Delaunay * 25*e70f70aaSPatrick Delaunay * @dev: pointer for the device 26*e70f70aaSPatrick Delaunay * @info: UCLASS RAM information 27*e70f70aaSPatrick Delaunay * @ctl: DDR controleur base address 28*e70f70aaSPatrick Delaunay * @clk: DDR clock 29*e70f70aaSPatrick Delaunay * @phy: DDR PHY base address 30*e70f70aaSPatrick Delaunay * @rcc: rcc base address 31*e70f70aaSPatrick Delaunay */ 32*e70f70aaSPatrick Delaunay struct ddr_info { 33*e70f70aaSPatrick Delaunay struct udevice *dev; 34*e70f70aaSPatrick Delaunay struct ram_info info; 35*e70f70aaSPatrick Delaunay struct clk clk; 36*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctl *ctl; 37*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy *phy; 38*e70f70aaSPatrick Delaunay u32 rcc; 39*e70f70aaSPatrick Delaunay }; 40*e70f70aaSPatrick Delaunay 41*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_reg { 42*e70f70aaSPatrick Delaunay u32 mstr; 43*e70f70aaSPatrick Delaunay u32 mrctrl0; 44*e70f70aaSPatrick Delaunay u32 mrctrl1; 45*e70f70aaSPatrick Delaunay u32 derateen; 46*e70f70aaSPatrick Delaunay u32 derateint; 47*e70f70aaSPatrick Delaunay u32 pwrctl; 48*e70f70aaSPatrick Delaunay u32 pwrtmg; 49*e70f70aaSPatrick Delaunay u32 hwlpctl; 50*e70f70aaSPatrick Delaunay u32 rfshctl0; 51*e70f70aaSPatrick Delaunay u32 rfshctl3; 52*e70f70aaSPatrick Delaunay u32 crcparctl0; 53*e70f70aaSPatrick Delaunay u32 zqctl0; 54*e70f70aaSPatrick Delaunay u32 dfitmg0; 55*e70f70aaSPatrick Delaunay u32 dfitmg1; 56*e70f70aaSPatrick Delaunay u32 dfilpcfg0; 57*e70f70aaSPatrick Delaunay u32 dfiupd0; 58*e70f70aaSPatrick Delaunay u32 dfiupd1; 59*e70f70aaSPatrick Delaunay u32 dfiupd2; 60*e70f70aaSPatrick Delaunay u32 dfiphymstr; 61*e70f70aaSPatrick Delaunay u32 odtmap; 62*e70f70aaSPatrick Delaunay u32 dbg0; 63*e70f70aaSPatrick Delaunay u32 dbg1; 64*e70f70aaSPatrick Delaunay u32 dbgcmd; 65*e70f70aaSPatrick Delaunay u32 poisoncfg; 66*e70f70aaSPatrick Delaunay u32 pccfg; 67*e70f70aaSPatrick Delaunay 68*e70f70aaSPatrick Delaunay }; 69*e70f70aaSPatrick Delaunay 70*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_timing { 71*e70f70aaSPatrick Delaunay u32 rfshtmg; 72*e70f70aaSPatrick Delaunay u32 dramtmg0; 73*e70f70aaSPatrick Delaunay u32 dramtmg1; 74*e70f70aaSPatrick Delaunay u32 dramtmg2; 75*e70f70aaSPatrick Delaunay u32 dramtmg3; 76*e70f70aaSPatrick Delaunay u32 dramtmg4; 77*e70f70aaSPatrick Delaunay u32 dramtmg5; 78*e70f70aaSPatrick Delaunay u32 dramtmg6; 79*e70f70aaSPatrick Delaunay u32 dramtmg7; 80*e70f70aaSPatrick Delaunay u32 dramtmg8; 81*e70f70aaSPatrick Delaunay u32 dramtmg14; 82*e70f70aaSPatrick Delaunay u32 odtcfg; 83*e70f70aaSPatrick Delaunay }; 84*e70f70aaSPatrick Delaunay 85*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_map { 86*e70f70aaSPatrick Delaunay u32 addrmap1; 87*e70f70aaSPatrick Delaunay u32 addrmap2; 88*e70f70aaSPatrick Delaunay u32 addrmap3; 89*e70f70aaSPatrick Delaunay u32 addrmap4; 90*e70f70aaSPatrick Delaunay u32 addrmap5; 91*e70f70aaSPatrick Delaunay u32 addrmap6; 92*e70f70aaSPatrick Delaunay u32 addrmap9; 93*e70f70aaSPatrick Delaunay u32 addrmap10; 94*e70f70aaSPatrick Delaunay u32 addrmap11; 95*e70f70aaSPatrick Delaunay }; 96*e70f70aaSPatrick Delaunay 97*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_perf { 98*e70f70aaSPatrick Delaunay u32 sched; 99*e70f70aaSPatrick Delaunay u32 sched1; 100*e70f70aaSPatrick Delaunay u32 perfhpr1; 101*e70f70aaSPatrick Delaunay u32 perflpr1; 102*e70f70aaSPatrick Delaunay u32 perfwr1; 103*e70f70aaSPatrick Delaunay u32 pcfgr_0; 104*e70f70aaSPatrick Delaunay u32 pcfgw_0; 105*e70f70aaSPatrick Delaunay u32 pcfgqos0_0; 106*e70f70aaSPatrick Delaunay u32 pcfgqos1_0; 107*e70f70aaSPatrick Delaunay u32 pcfgwqos0_0; 108*e70f70aaSPatrick Delaunay u32 pcfgwqos1_0; 109*e70f70aaSPatrick Delaunay u32 pcfgr_1; 110*e70f70aaSPatrick Delaunay u32 pcfgw_1; 111*e70f70aaSPatrick Delaunay u32 pcfgqos0_1; 112*e70f70aaSPatrick Delaunay u32 pcfgqos1_1; 113*e70f70aaSPatrick Delaunay u32 pcfgwqos0_1; 114*e70f70aaSPatrick Delaunay u32 pcfgwqos1_1; 115*e70f70aaSPatrick Delaunay }; 116*e70f70aaSPatrick Delaunay 117*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_reg { 118*e70f70aaSPatrick Delaunay u32 pgcr; 119*e70f70aaSPatrick Delaunay u32 aciocr; 120*e70f70aaSPatrick Delaunay u32 dxccr; 121*e70f70aaSPatrick Delaunay u32 dsgcr; 122*e70f70aaSPatrick Delaunay u32 dcr; 123*e70f70aaSPatrick Delaunay u32 odtcr; 124*e70f70aaSPatrick Delaunay u32 zq0cr1; 125*e70f70aaSPatrick Delaunay u32 dx0gcr; 126*e70f70aaSPatrick Delaunay u32 dx1gcr; 127*e70f70aaSPatrick Delaunay u32 dx2gcr; 128*e70f70aaSPatrick Delaunay u32 dx3gcr; 129*e70f70aaSPatrick Delaunay }; 130*e70f70aaSPatrick Delaunay 131*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_timing { 132*e70f70aaSPatrick Delaunay u32 ptr0; 133*e70f70aaSPatrick Delaunay u32 ptr1; 134*e70f70aaSPatrick Delaunay u32 ptr2; 135*e70f70aaSPatrick Delaunay u32 dtpr0; 136*e70f70aaSPatrick Delaunay u32 dtpr1; 137*e70f70aaSPatrick Delaunay u32 dtpr2; 138*e70f70aaSPatrick Delaunay u32 mr0; 139*e70f70aaSPatrick Delaunay u32 mr1; 140*e70f70aaSPatrick Delaunay u32 mr2; 141*e70f70aaSPatrick Delaunay u32 mr3; 142*e70f70aaSPatrick Delaunay }; 143*e70f70aaSPatrick Delaunay 144*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_cal { 145*e70f70aaSPatrick Delaunay u32 dx0dllcr; 146*e70f70aaSPatrick Delaunay u32 dx0dqtr; 147*e70f70aaSPatrick Delaunay u32 dx0dqstr; 148*e70f70aaSPatrick Delaunay u32 dx1dllcr; 149*e70f70aaSPatrick Delaunay u32 dx1dqtr; 150*e70f70aaSPatrick Delaunay u32 dx1dqstr; 151*e70f70aaSPatrick Delaunay u32 dx2dllcr; 152*e70f70aaSPatrick Delaunay u32 dx2dqtr; 153*e70f70aaSPatrick Delaunay u32 dx2dqstr; 154*e70f70aaSPatrick Delaunay u32 dx3dllcr; 155*e70f70aaSPatrick Delaunay u32 dx3dqtr; 156*e70f70aaSPatrick Delaunay u32 dx3dqstr; 157*e70f70aaSPatrick Delaunay }; 158*e70f70aaSPatrick Delaunay 159*e70f70aaSPatrick Delaunay struct stm32mp1_ddr_info { 160*e70f70aaSPatrick Delaunay const char *name; 161*e70f70aaSPatrick Delaunay u16 speed; /* in MHZ */ 162*e70f70aaSPatrick Delaunay u32 size; /* memory size in byte = col * row * width */ 163*e70f70aaSPatrick Delaunay }; 164*e70f70aaSPatrick Delaunay 165*e70f70aaSPatrick Delaunay struct stm32mp1_ddr_config { 166*e70f70aaSPatrick Delaunay struct stm32mp1_ddr_info info; 167*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_reg c_reg; 168*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_timing c_timing; 169*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_map c_map; 170*e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_perf c_perf; 171*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_reg p_reg; 172*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_timing p_timing; 173*e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_cal p_cal; 174*e70f70aaSPatrick Delaunay }; 175*e70f70aaSPatrick Delaunay 176*e70f70aaSPatrick Delaunay int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed); 177*e70f70aaSPatrick Delaunay void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); 178*e70f70aaSPatrick Delaunay void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); 179*e70f70aaSPatrick Delaunay void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, 180*e70f70aaSPatrick Delaunay u32 rfshctl3, 181*e70f70aaSPatrick Delaunay u32 pwrctl); 182*e70f70aaSPatrick Delaunay 183*e70f70aaSPatrick Delaunay void stm32mp1_ddr_init( 184*e70f70aaSPatrick Delaunay struct ddr_info *priv, 185*e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 186*e70f70aaSPatrick Delaunay 187*e70f70aaSPatrick Delaunay int stm32mp1_dump_reg(const struct ddr_info *priv, 188*e70f70aaSPatrick Delaunay const char *name); 189*e70f70aaSPatrick Delaunay 190*e70f70aaSPatrick Delaunay void stm32mp1_edit_reg(const struct ddr_info *priv, 191*e70f70aaSPatrick Delaunay char *name, 192*e70f70aaSPatrick Delaunay char *string); 193*e70f70aaSPatrick Delaunay 194*e70f70aaSPatrick Delaunay int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, 195*e70f70aaSPatrick Delaunay const char *name); 196*e70f70aaSPatrick Delaunay 197*e70f70aaSPatrick Delaunay void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, 198*e70f70aaSPatrick Delaunay char *name, 199*e70f70aaSPatrick Delaunay char *string); 200*e70f70aaSPatrick Delaunay 201*e70f70aaSPatrick Delaunay void stm32mp1_dump_info( 202*e70f70aaSPatrick Delaunay const struct ddr_info *priv, 203*e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 204*e70f70aaSPatrick Delaunay 205*e70f70aaSPatrick Delaunay bool stm32mp1_ddr_interactive( 206*e70f70aaSPatrick Delaunay void *priv, 207*e70f70aaSPatrick Delaunay enum stm32mp1_ddr_interact_step step, 208*e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 209*e70f70aaSPatrick Delaunay 210*e70f70aaSPatrick Delaunay #endif 211