1*4549e789STom Rini /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2e70f70aaSPatrick Delaunay /* 3e70f70aaSPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4e70f70aaSPatrick Delaunay */ 5e70f70aaSPatrick Delaunay 6e70f70aaSPatrick Delaunay #ifndef _RAM_STM32MP1_DDR_H 7e70f70aaSPatrick Delaunay #define _RAM_STM32MP1_DDR_H 8e70f70aaSPatrick Delaunay 9e70f70aaSPatrick Delaunay enum stm32mp1_ddr_interact_step { 10e70f70aaSPatrick Delaunay STEP_DDR_RESET, 11e70f70aaSPatrick Delaunay STEP_CTL_INIT, 12e70f70aaSPatrick Delaunay STEP_PHY_INIT, 13e70f70aaSPatrick Delaunay STEP_DDR_READY, 14e70f70aaSPatrick Delaunay STEP_RUN, 15e70f70aaSPatrick Delaunay }; 16e70f70aaSPatrick Delaunay 17e70f70aaSPatrick Delaunay /* DDR CTL and DDR PHY REGISTERS */ 18e70f70aaSPatrick Delaunay struct stm32mp1_ddrctl; 19e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy; 20e70f70aaSPatrick Delaunay 21e70f70aaSPatrick Delaunay /** 22e70f70aaSPatrick Delaunay * struct ddr_info 23e70f70aaSPatrick Delaunay * 24e70f70aaSPatrick Delaunay * @dev: pointer for the device 25e70f70aaSPatrick Delaunay * @info: UCLASS RAM information 26e70f70aaSPatrick Delaunay * @ctl: DDR controleur base address 27e70f70aaSPatrick Delaunay * @clk: DDR clock 28e70f70aaSPatrick Delaunay * @phy: DDR PHY base address 29e70f70aaSPatrick Delaunay * @rcc: rcc base address 30e70f70aaSPatrick Delaunay */ 31e70f70aaSPatrick Delaunay struct ddr_info { 32e70f70aaSPatrick Delaunay struct udevice *dev; 33e70f70aaSPatrick Delaunay struct ram_info info; 34e70f70aaSPatrick Delaunay struct clk clk; 35e70f70aaSPatrick Delaunay struct stm32mp1_ddrctl *ctl; 36e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy *phy; 37e70f70aaSPatrick Delaunay u32 rcc; 38e70f70aaSPatrick Delaunay }; 39e70f70aaSPatrick Delaunay 40e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_reg { 41e70f70aaSPatrick Delaunay u32 mstr; 42e70f70aaSPatrick Delaunay u32 mrctrl0; 43e70f70aaSPatrick Delaunay u32 mrctrl1; 44e70f70aaSPatrick Delaunay u32 derateen; 45e70f70aaSPatrick Delaunay u32 derateint; 46e70f70aaSPatrick Delaunay u32 pwrctl; 47e70f70aaSPatrick Delaunay u32 pwrtmg; 48e70f70aaSPatrick Delaunay u32 hwlpctl; 49e70f70aaSPatrick Delaunay u32 rfshctl0; 50e70f70aaSPatrick Delaunay u32 rfshctl3; 51e70f70aaSPatrick Delaunay u32 crcparctl0; 52e70f70aaSPatrick Delaunay u32 zqctl0; 53e70f70aaSPatrick Delaunay u32 dfitmg0; 54e70f70aaSPatrick Delaunay u32 dfitmg1; 55e70f70aaSPatrick Delaunay u32 dfilpcfg0; 56e70f70aaSPatrick Delaunay u32 dfiupd0; 57e70f70aaSPatrick Delaunay u32 dfiupd1; 58e70f70aaSPatrick Delaunay u32 dfiupd2; 59e70f70aaSPatrick Delaunay u32 dfiphymstr; 60e70f70aaSPatrick Delaunay u32 odtmap; 61e70f70aaSPatrick Delaunay u32 dbg0; 62e70f70aaSPatrick Delaunay u32 dbg1; 63e70f70aaSPatrick Delaunay u32 dbgcmd; 64e70f70aaSPatrick Delaunay u32 poisoncfg; 65e70f70aaSPatrick Delaunay u32 pccfg; 66e70f70aaSPatrick Delaunay 67e70f70aaSPatrick Delaunay }; 68e70f70aaSPatrick Delaunay 69e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_timing { 70e70f70aaSPatrick Delaunay u32 rfshtmg; 71e70f70aaSPatrick Delaunay u32 dramtmg0; 72e70f70aaSPatrick Delaunay u32 dramtmg1; 73e70f70aaSPatrick Delaunay u32 dramtmg2; 74e70f70aaSPatrick Delaunay u32 dramtmg3; 75e70f70aaSPatrick Delaunay u32 dramtmg4; 76e70f70aaSPatrick Delaunay u32 dramtmg5; 77e70f70aaSPatrick Delaunay u32 dramtmg6; 78e70f70aaSPatrick Delaunay u32 dramtmg7; 79e70f70aaSPatrick Delaunay u32 dramtmg8; 80e70f70aaSPatrick Delaunay u32 dramtmg14; 81e70f70aaSPatrick Delaunay u32 odtcfg; 82e70f70aaSPatrick Delaunay }; 83e70f70aaSPatrick Delaunay 84e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_map { 85e70f70aaSPatrick Delaunay u32 addrmap1; 86e70f70aaSPatrick Delaunay u32 addrmap2; 87e70f70aaSPatrick Delaunay u32 addrmap3; 88e70f70aaSPatrick Delaunay u32 addrmap4; 89e70f70aaSPatrick Delaunay u32 addrmap5; 90e70f70aaSPatrick Delaunay u32 addrmap6; 91e70f70aaSPatrick Delaunay u32 addrmap9; 92e70f70aaSPatrick Delaunay u32 addrmap10; 93e70f70aaSPatrick Delaunay u32 addrmap11; 94e70f70aaSPatrick Delaunay }; 95e70f70aaSPatrick Delaunay 96e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_perf { 97e70f70aaSPatrick Delaunay u32 sched; 98e70f70aaSPatrick Delaunay u32 sched1; 99e70f70aaSPatrick Delaunay u32 perfhpr1; 100e70f70aaSPatrick Delaunay u32 perflpr1; 101e70f70aaSPatrick Delaunay u32 perfwr1; 102e70f70aaSPatrick Delaunay u32 pcfgr_0; 103e70f70aaSPatrick Delaunay u32 pcfgw_0; 104e70f70aaSPatrick Delaunay u32 pcfgqos0_0; 105e70f70aaSPatrick Delaunay u32 pcfgqos1_0; 106e70f70aaSPatrick Delaunay u32 pcfgwqos0_0; 107e70f70aaSPatrick Delaunay u32 pcfgwqos1_0; 108e70f70aaSPatrick Delaunay u32 pcfgr_1; 109e70f70aaSPatrick Delaunay u32 pcfgw_1; 110e70f70aaSPatrick Delaunay u32 pcfgqos0_1; 111e70f70aaSPatrick Delaunay u32 pcfgqos1_1; 112e70f70aaSPatrick Delaunay u32 pcfgwqos0_1; 113e70f70aaSPatrick Delaunay u32 pcfgwqos1_1; 114e70f70aaSPatrick Delaunay }; 115e70f70aaSPatrick Delaunay 116e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_reg { 117e70f70aaSPatrick Delaunay u32 pgcr; 118e70f70aaSPatrick Delaunay u32 aciocr; 119e70f70aaSPatrick Delaunay u32 dxccr; 120e70f70aaSPatrick Delaunay u32 dsgcr; 121e70f70aaSPatrick Delaunay u32 dcr; 122e70f70aaSPatrick Delaunay u32 odtcr; 123e70f70aaSPatrick Delaunay u32 zq0cr1; 124e70f70aaSPatrick Delaunay u32 dx0gcr; 125e70f70aaSPatrick Delaunay u32 dx1gcr; 126e70f70aaSPatrick Delaunay u32 dx2gcr; 127e70f70aaSPatrick Delaunay u32 dx3gcr; 128e70f70aaSPatrick Delaunay }; 129e70f70aaSPatrick Delaunay 130e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_timing { 131e70f70aaSPatrick Delaunay u32 ptr0; 132e70f70aaSPatrick Delaunay u32 ptr1; 133e70f70aaSPatrick Delaunay u32 ptr2; 134e70f70aaSPatrick Delaunay u32 dtpr0; 135e70f70aaSPatrick Delaunay u32 dtpr1; 136e70f70aaSPatrick Delaunay u32 dtpr2; 137e70f70aaSPatrick Delaunay u32 mr0; 138e70f70aaSPatrick Delaunay u32 mr1; 139e70f70aaSPatrick Delaunay u32 mr2; 140e70f70aaSPatrick Delaunay u32 mr3; 141e70f70aaSPatrick Delaunay }; 142e70f70aaSPatrick Delaunay 143e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_cal { 144e70f70aaSPatrick Delaunay u32 dx0dllcr; 145e70f70aaSPatrick Delaunay u32 dx0dqtr; 146e70f70aaSPatrick Delaunay u32 dx0dqstr; 147e70f70aaSPatrick Delaunay u32 dx1dllcr; 148e70f70aaSPatrick Delaunay u32 dx1dqtr; 149e70f70aaSPatrick Delaunay u32 dx1dqstr; 150e70f70aaSPatrick Delaunay u32 dx2dllcr; 151e70f70aaSPatrick Delaunay u32 dx2dqtr; 152e70f70aaSPatrick Delaunay u32 dx2dqstr; 153e70f70aaSPatrick Delaunay u32 dx3dllcr; 154e70f70aaSPatrick Delaunay u32 dx3dqtr; 155e70f70aaSPatrick Delaunay u32 dx3dqstr; 156e70f70aaSPatrick Delaunay }; 157e70f70aaSPatrick Delaunay 158e70f70aaSPatrick Delaunay struct stm32mp1_ddr_info { 159e70f70aaSPatrick Delaunay const char *name; 160e70f70aaSPatrick Delaunay u16 speed; /* in MHZ */ 161e70f70aaSPatrick Delaunay u32 size; /* memory size in byte = col * row * width */ 162e70f70aaSPatrick Delaunay }; 163e70f70aaSPatrick Delaunay 164e70f70aaSPatrick Delaunay struct stm32mp1_ddr_config { 165e70f70aaSPatrick Delaunay struct stm32mp1_ddr_info info; 166e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_reg c_reg; 167e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_timing c_timing; 168e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_map c_map; 169e70f70aaSPatrick Delaunay struct stm32mp1_ddrctrl_perf c_perf; 170e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_reg p_reg; 171e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_timing p_timing; 172e70f70aaSPatrick Delaunay struct stm32mp1_ddrphy_cal p_cal; 173e70f70aaSPatrick Delaunay }; 174e70f70aaSPatrick Delaunay 175e70f70aaSPatrick Delaunay int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed); 176e70f70aaSPatrick Delaunay void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); 177e70f70aaSPatrick Delaunay void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); 178e70f70aaSPatrick Delaunay void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, 179e70f70aaSPatrick Delaunay u32 rfshctl3, 180e70f70aaSPatrick Delaunay u32 pwrctl); 181e70f70aaSPatrick Delaunay 182e70f70aaSPatrick Delaunay void stm32mp1_ddr_init( 183e70f70aaSPatrick Delaunay struct ddr_info *priv, 184e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 185e70f70aaSPatrick Delaunay 186e70f70aaSPatrick Delaunay int stm32mp1_dump_reg(const struct ddr_info *priv, 187e70f70aaSPatrick Delaunay const char *name); 188e70f70aaSPatrick Delaunay 189e70f70aaSPatrick Delaunay void stm32mp1_edit_reg(const struct ddr_info *priv, 190e70f70aaSPatrick Delaunay char *name, 191e70f70aaSPatrick Delaunay char *string); 192e70f70aaSPatrick Delaunay 193e70f70aaSPatrick Delaunay int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, 194e70f70aaSPatrick Delaunay const char *name); 195e70f70aaSPatrick Delaunay 196e70f70aaSPatrick Delaunay void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, 197e70f70aaSPatrick Delaunay char *name, 198e70f70aaSPatrick Delaunay char *string); 199e70f70aaSPatrick Delaunay 200e70f70aaSPatrick Delaunay void stm32mp1_dump_info( 201e70f70aaSPatrick Delaunay const struct ddr_info *priv, 202e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 203e70f70aaSPatrick Delaunay 204e70f70aaSPatrick Delaunay bool stm32mp1_ddr_interactive( 205e70f70aaSPatrick Delaunay void *priv, 206e70f70aaSPatrick Delaunay enum stm32mp1_ddr_interact_step step, 207e70f70aaSPatrick Delaunay const struct stm32mp1_ddr_config *config); 208e70f70aaSPatrick Delaunay 209e70f70aaSPatrick Delaunay #endif 210