1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct stm32_fmc_regs { 17 /* 0x0 */ 18 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ 19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ 20 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ 21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ 22 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ 23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ 24 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ 25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ 26 u32 reserved1[24]; 27 28 /* 0x80 */ 29 u32 pcr; /* NAND Flash control register */ 30 u32 sr; /* FIFO status and interrupt register */ 31 u32 pmem; /* Common memory space timing register */ 32 u32 patt; /* Attribute memory space timing registers */ 33 u32 reserved2[1]; 34 u32 eccr; /* ECC result registers */ 35 u32 reserved3[27]; 36 37 /* 0x104 */ 38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ 39 u32 reserved4[1]; 40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ 41 u32 reserved5[1]; 42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ 43 u32 reserved6[1]; 44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ 45 u32 reserved7[8]; 46 47 /* 0x140 */ 48 u32 sdcr1; /* SDRAM Control register 1 */ 49 u32 sdcr2; /* SDRAM Control register 2 */ 50 u32 sdtr1; /* SDRAM Timing register 1 */ 51 u32 sdtr2; /* SDRAM Timing register 2 */ 52 u32 sdcmr; /* SDRAM Mode register */ 53 u32 sdrtr; /* SDRAM Refresh timing register */ 54 u32 sdsr; /* SDRAM Status register */ 55 }; 56 57 /* 58 * NOR/PSRAM Control register BCR1 59 * FMC controller Enable, only availabe for H7 60 */ 61 #define FMC_BCR1_FMCEN BIT(31) 62 63 /* Control register SDCR */ 64 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 65 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 66 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 67 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 68 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 69 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 70 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 71 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 72 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 73 74 /* Timings register SDTR */ 75 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 76 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 77 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 78 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 79 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 80 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 81 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 82 83 #define FMC_SDCMR_NRFS_SHIFT 5 84 85 #define FMC_SDCMR_MODE_NORMAL 0 86 #define FMC_SDCMR_MODE_START_CLOCK 1 87 #define FMC_SDCMR_MODE_PRECHARGE 2 88 #define FMC_SDCMR_MODE_AUTOREFRESH 3 89 #define FMC_SDCMR_MODE_WRITE_MODE 4 90 #define FMC_SDCMR_MODE_SELFREFRESH 5 91 #define FMC_SDCMR_MODE_POWERDOWN 6 92 93 #define FMC_SDCMR_BANK_1 BIT(4) 94 #define FMC_SDCMR_BANK_2 BIT(3) 95 96 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 97 98 #define FMC_SDSR_BUSY BIT(5) 99 100 #define FMC_BUSY_WAIT(regs) do { \ 101 __asm__ __volatile__ ("dsb" : : : "memory"); \ 102 while (regs->sdsr & FMC_SDSR_BUSY) \ 103 ; \ 104 } while (0) 105 106 struct stm32_sdram_control { 107 u8 no_columns; 108 u8 no_rows; 109 u8 memory_width; 110 u8 no_banks; 111 u8 cas_latency; 112 u8 sdclk; 113 u8 rd_burst; 114 u8 rd_pipe_delay; 115 }; 116 117 struct stm32_sdram_timing { 118 u8 tmrd; 119 u8 txsr; 120 u8 tras; 121 u8 trc; 122 u8 trp; 123 u8 twr; 124 u8 trcd; 125 }; 126 enum stm32_fmc_bank { 127 SDRAM_BANK1, 128 SDRAM_BANK2, 129 MAX_SDRAM_BANK, 130 }; 131 132 enum stm32_fmc_family { 133 STM32F7_FMC, 134 STM32H7_FMC, 135 }; 136 137 struct bank_params { 138 struct stm32_sdram_control *sdram_control; 139 struct stm32_sdram_timing *sdram_timing; 140 u32 sdram_ref_count; 141 enum stm32_fmc_bank target_bank; 142 }; 143 144 struct stm32_sdram_params { 145 struct stm32_fmc_regs *base; 146 u8 no_sdram_banks; 147 struct bank_params bank_params[MAX_SDRAM_BANK]; 148 enum stm32_fmc_family family; 149 }; 150 151 #define SDRAM_MODE_BL_SHIFT 0 152 #define SDRAM_MODE_CAS_SHIFT 4 153 #define SDRAM_MODE_BL 0 154 155 int stm32_sdram_init(struct udevice *dev) 156 { 157 struct stm32_sdram_params *params = dev_get_platdata(dev); 158 struct stm32_sdram_control *control; 159 struct stm32_sdram_timing *timing; 160 struct stm32_fmc_regs *regs = params->base; 161 enum stm32_fmc_bank target_bank; 162 u32 ctb; /* SDCMR register: Command Target Bank */ 163 u32 ref_count; 164 u8 i; 165 166 /* disable the FMC controller */ 167 if (params->family == STM32H7_FMC) 168 clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); 169 170 for (i = 0; i < params->no_sdram_banks; i++) { 171 control = params->bank_params[i].sdram_control; 172 timing = params->bank_params[i].sdram_timing; 173 target_bank = params->bank_params[i].target_bank; 174 ref_count = params->bank_params[i].sdram_ref_count; 175 176 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT 177 | control->cas_latency << FMC_SDCR_CAS_SHIFT 178 | control->no_banks << FMC_SDCR_NB_SHIFT 179 | control->memory_width << FMC_SDCR_MWID_SHIFT 180 | control->no_rows << FMC_SDCR_NR_SHIFT 181 | control->no_columns << FMC_SDCR_NC_SHIFT 182 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 183 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, 184 ®s->sdcr1); 185 186 if (target_bank == SDRAM_BANK2) 187 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT 188 | control->no_banks << FMC_SDCR_NB_SHIFT 189 | control->memory_width << FMC_SDCR_MWID_SHIFT 190 | control->no_rows << FMC_SDCR_NR_SHIFT 191 | control->no_columns << FMC_SDCR_NC_SHIFT, 192 ®s->sdcr2); 193 194 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 195 | timing->trp << FMC_SDTR_TRP_SHIFT 196 | timing->twr << FMC_SDTR_TWR_SHIFT 197 | timing->trc << FMC_SDTR_TRC_SHIFT 198 | timing->tras << FMC_SDTR_TRAS_SHIFT 199 | timing->txsr << FMC_SDTR_TXSR_SHIFT 200 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 201 ®s->sdtr1); 202 203 if (target_bank == SDRAM_BANK2) 204 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 205 | timing->trp << FMC_SDTR_TRP_SHIFT 206 | timing->twr << FMC_SDTR_TWR_SHIFT 207 | timing->trc << FMC_SDTR_TRC_SHIFT 208 | timing->tras << FMC_SDTR_TRAS_SHIFT 209 | timing->txsr << FMC_SDTR_TXSR_SHIFT 210 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 211 ®s->sdtr2); 212 213 if (target_bank == SDRAM_BANK1) 214 ctb = FMC_SDCMR_BANK_1; 215 else 216 ctb = FMC_SDCMR_BANK_2; 217 218 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); 219 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 220 FMC_BUSY_WAIT(regs); 221 222 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); 223 udelay(100); 224 FMC_BUSY_WAIT(regs); 225 226 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), 227 ®s->sdcmr); 228 udelay(100); 229 FMC_BUSY_WAIT(regs); 230 231 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 232 | control->cas_latency << SDRAM_MODE_CAS_SHIFT) 233 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 234 ®s->sdcmr); 235 udelay(100); 236 FMC_BUSY_WAIT(regs); 237 238 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); 239 FMC_BUSY_WAIT(regs); 240 241 /* Refresh timer */ 242 writel(ref_count << 1, ®s->sdrtr); 243 } 244 245 /* enable the FMC controller */ 246 if (params->family == STM32H7_FMC) 247 setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); 248 249 return 0; 250 } 251 252 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 253 { 254 struct stm32_sdram_params *params = dev_get_platdata(dev); 255 struct bank_params *bank_params; 256 ofnode bank_node; 257 char *bank_name; 258 u8 bank = 0; 259 260 dev_for_each_subnode(bank_node, dev) { 261 /* extract the bank index from DT */ 262 bank_name = (char *)ofnode_get_name(bank_node); 263 strsep(&bank_name, "@"); 264 if (!bank_name) { 265 pr_err("missing sdram bank index"); 266 return -EINVAL; 267 } 268 269 bank_params = ¶ms->bank_params[bank]; 270 strict_strtoul(bank_name, 10, 271 (long unsigned int *)&bank_params->target_bank); 272 273 if (bank_params->target_bank >= MAX_SDRAM_BANK) { 274 pr_err("Found bank %d , but only bank 0 and 1 are supported", 275 bank_params->target_bank); 276 return -EINVAL; 277 } 278 279 debug("Find bank %s %u\n", bank_name, bank_params->target_bank); 280 281 params->bank_params[bank].sdram_control = 282 (struct stm32_sdram_control *) 283 ofnode_read_u8_array_ptr(bank_node, 284 "st,sdram-control", 285 sizeof(struct stm32_sdram_control)); 286 287 if (!params->bank_params[bank].sdram_control) { 288 pr_err("st,sdram-control not found for %s", 289 ofnode_get_name(bank_node)); 290 return -EINVAL; 291 } 292 293 294 params->bank_params[bank].sdram_timing = 295 (struct stm32_sdram_timing *) 296 ofnode_read_u8_array_ptr(bank_node, 297 "st,sdram-timing", 298 sizeof(struct stm32_sdram_timing)); 299 300 if (!params->bank_params[bank].sdram_timing) { 301 pr_err("st,sdram-timing not found for %s", 302 ofnode_get_name(bank_node)); 303 return -EINVAL; 304 } 305 306 307 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, 308 "st,sdram-refcount", 8196); 309 bank++; 310 } 311 312 params->no_sdram_banks = bank; 313 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 314 315 return 0; 316 } 317 318 static int stm32_fmc_probe(struct udevice *dev) 319 { 320 struct stm32_sdram_params *params = dev_get_platdata(dev); 321 int ret; 322 fdt_addr_t addr; 323 324 addr = dev_read_addr(dev); 325 if (addr == FDT_ADDR_T_NONE) 326 return -EINVAL; 327 328 params->base = (struct stm32_fmc_regs *)addr; 329 params->family = dev_get_driver_data(dev); 330 331 #ifdef CONFIG_CLK 332 struct clk clk; 333 334 ret = clk_get_by_index(dev, 0, &clk); 335 if (ret < 0) 336 return ret; 337 338 ret = clk_enable(&clk); 339 340 if (ret) { 341 dev_err(dev, "failed to enable clock\n"); 342 return ret; 343 } 344 #endif 345 ret = stm32_sdram_init(dev); 346 if (ret) 347 return ret; 348 349 return 0; 350 } 351 352 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 353 { 354 return 0; 355 } 356 357 static struct ram_ops stm32_fmc_ops = { 358 .get_info = stm32_fmc_get_info, 359 }; 360 361 static const struct udevice_id stm32_fmc_ids[] = { 362 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, 363 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, 364 { } 365 }; 366 367 U_BOOT_DRIVER(stm32_fmc) = { 368 .name = "stm32_fmc", 369 .id = UCLASS_RAM, 370 .of_match = stm32_fmc_ids, 371 .ops = &stm32_fmc_ops, 372 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 373 .probe = stm32_fmc_probe, 374 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 375 }; 376