1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <ram.h> 12 #include <asm/io.h> 13 14 #define MEM_MODE_MASK GENMASK(2, 0) 15 #define NOT_FOUND 0xff 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 struct stm32_fmc_regs { 20 /* 0x0 */ 21 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ 22 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ 23 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ 24 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ 25 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ 26 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ 27 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ 28 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ 29 u32 reserved1[24]; 30 31 /* 0x80 */ 32 u32 pcr; /* NAND Flash control register */ 33 u32 sr; /* FIFO status and interrupt register */ 34 u32 pmem; /* Common memory space timing register */ 35 u32 patt; /* Attribute memory space timing registers */ 36 u32 reserved2[1]; 37 u32 eccr; /* ECC result registers */ 38 u32 reserved3[27]; 39 40 /* 0x104 */ 41 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ 42 u32 reserved4[1]; 43 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ 44 u32 reserved5[1]; 45 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ 46 u32 reserved6[1]; 47 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ 48 u32 reserved7[8]; 49 50 /* 0x140 */ 51 u32 sdcr1; /* SDRAM Control register 1 */ 52 u32 sdcr2; /* SDRAM Control register 2 */ 53 u32 sdtr1; /* SDRAM Timing register 1 */ 54 u32 sdtr2; /* SDRAM Timing register 2 */ 55 u32 sdcmr; /* SDRAM Mode register */ 56 u32 sdrtr; /* SDRAM Refresh timing register */ 57 u32 sdsr; /* SDRAM Status register */ 58 }; 59 60 /* 61 * NOR/PSRAM Control register BCR1 62 * FMC controller Enable, only availabe for H7 63 */ 64 #define FMC_BCR1_FMCEN BIT(31) 65 66 /* Control register SDCR */ 67 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ 68 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ 69 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ 70 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ 71 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ 72 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ 73 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ 74 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ 75 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ 76 77 /* Timings register SDTR */ 78 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ 79 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ 80 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ 81 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ 82 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ 83 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ 84 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ 85 86 #define FMC_SDCMR_NRFS_SHIFT 5 87 88 #define FMC_SDCMR_MODE_NORMAL 0 89 #define FMC_SDCMR_MODE_START_CLOCK 1 90 #define FMC_SDCMR_MODE_PRECHARGE 2 91 #define FMC_SDCMR_MODE_AUTOREFRESH 3 92 #define FMC_SDCMR_MODE_WRITE_MODE 4 93 #define FMC_SDCMR_MODE_SELFREFRESH 5 94 #define FMC_SDCMR_MODE_POWERDOWN 6 95 96 #define FMC_SDCMR_BANK_1 BIT(4) 97 #define FMC_SDCMR_BANK_2 BIT(3) 98 99 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 100 101 #define FMC_SDSR_BUSY BIT(5) 102 103 #define FMC_BUSY_WAIT(regs) do { \ 104 __asm__ __volatile__ ("dsb" : : : "memory"); \ 105 while (regs->sdsr & FMC_SDSR_BUSY) \ 106 ; \ 107 } while (0) 108 109 struct stm32_sdram_control { 110 u8 no_columns; 111 u8 no_rows; 112 u8 memory_width; 113 u8 no_banks; 114 u8 cas_latency; 115 u8 sdclk; 116 u8 rd_burst; 117 u8 rd_pipe_delay; 118 }; 119 120 struct stm32_sdram_timing { 121 u8 tmrd; 122 u8 txsr; 123 u8 tras; 124 u8 trc; 125 u8 trp; 126 u8 twr; 127 u8 trcd; 128 }; 129 enum stm32_fmc_bank { 130 SDRAM_BANK1, 131 SDRAM_BANK2, 132 MAX_SDRAM_BANK, 133 }; 134 135 enum stm32_fmc_family { 136 STM32F7_FMC, 137 STM32H7_FMC, 138 }; 139 140 struct bank_params { 141 struct stm32_sdram_control *sdram_control; 142 struct stm32_sdram_timing *sdram_timing; 143 u32 sdram_ref_count; 144 enum stm32_fmc_bank target_bank; 145 }; 146 147 struct stm32_sdram_params { 148 struct stm32_fmc_regs *base; 149 u8 no_sdram_banks; 150 struct bank_params bank_params[MAX_SDRAM_BANK]; 151 enum stm32_fmc_family family; 152 }; 153 154 #define SDRAM_MODE_BL_SHIFT 0 155 #define SDRAM_MODE_CAS_SHIFT 4 156 #define SDRAM_MODE_BL 0 157 158 int stm32_sdram_init(struct udevice *dev) 159 { 160 struct stm32_sdram_params *params = dev_get_platdata(dev); 161 struct stm32_sdram_control *control; 162 struct stm32_sdram_timing *timing; 163 struct stm32_fmc_regs *regs = params->base; 164 enum stm32_fmc_bank target_bank; 165 u32 ctb; /* SDCMR register: Command Target Bank */ 166 u32 ref_count; 167 u8 i; 168 169 /* disable the FMC controller */ 170 if (params->family == STM32H7_FMC) 171 clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); 172 173 for (i = 0; i < params->no_sdram_banks; i++) { 174 control = params->bank_params[i].sdram_control; 175 timing = params->bank_params[i].sdram_timing; 176 target_bank = params->bank_params[i].target_bank; 177 ref_count = params->bank_params[i].sdram_ref_count; 178 179 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT 180 | control->cas_latency << FMC_SDCR_CAS_SHIFT 181 | control->no_banks << FMC_SDCR_NB_SHIFT 182 | control->memory_width << FMC_SDCR_MWID_SHIFT 183 | control->no_rows << FMC_SDCR_NR_SHIFT 184 | control->no_columns << FMC_SDCR_NC_SHIFT 185 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT 186 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, 187 ®s->sdcr1); 188 189 if (target_bank == SDRAM_BANK2) 190 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT 191 | control->no_banks << FMC_SDCR_NB_SHIFT 192 | control->memory_width << FMC_SDCR_MWID_SHIFT 193 | control->no_rows << FMC_SDCR_NR_SHIFT 194 | control->no_columns << FMC_SDCR_NC_SHIFT, 195 ®s->sdcr2); 196 197 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 198 | timing->trp << FMC_SDTR_TRP_SHIFT 199 | timing->twr << FMC_SDTR_TWR_SHIFT 200 | timing->trc << FMC_SDTR_TRC_SHIFT 201 | timing->tras << FMC_SDTR_TRAS_SHIFT 202 | timing->txsr << FMC_SDTR_TXSR_SHIFT 203 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 204 ®s->sdtr1); 205 206 if (target_bank == SDRAM_BANK2) 207 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT 208 | timing->trp << FMC_SDTR_TRP_SHIFT 209 | timing->twr << FMC_SDTR_TWR_SHIFT 210 | timing->trc << FMC_SDTR_TRC_SHIFT 211 | timing->tras << FMC_SDTR_TRAS_SHIFT 212 | timing->txsr << FMC_SDTR_TXSR_SHIFT 213 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, 214 ®s->sdtr2); 215 216 if (target_bank == SDRAM_BANK1) 217 ctb = FMC_SDCMR_BANK_1; 218 else 219 ctb = FMC_SDCMR_BANK_2; 220 221 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); 222 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 223 FMC_BUSY_WAIT(regs); 224 225 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); 226 udelay(100); 227 FMC_BUSY_WAIT(regs); 228 229 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), 230 ®s->sdcmr); 231 udelay(100); 232 FMC_BUSY_WAIT(regs); 233 234 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 235 | control->cas_latency << SDRAM_MODE_CAS_SHIFT) 236 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 237 ®s->sdcmr); 238 udelay(100); 239 FMC_BUSY_WAIT(regs); 240 241 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); 242 FMC_BUSY_WAIT(regs); 243 244 /* Refresh timer */ 245 writel(ref_count << 1, ®s->sdrtr); 246 } 247 248 /* enable the FMC controller */ 249 if (params->family == STM32H7_FMC) 250 setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); 251 252 return 0; 253 } 254 255 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) 256 { 257 struct stm32_sdram_params *params = dev_get_platdata(dev); 258 struct bank_params *bank_params; 259 struct ofnode_phandle_args args; 260 u32 *syscfg_base; 261 u32 mem_remap; 262 ofnode bank_node; 263 char *bank_name; 264 u8 bank = 0; 265 int ret; 266 267 mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); 268 if (mem_remap != NOT_FOUND) { 269 ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, 270 &args); 271 if (ret) { 272 debug("%s: can't find syscon device (%d)\n", __func__, 273 ret); 274 return ret; 275 } 276 277 syscfg_base = (u32 *)ofnode_get_addr(args.node); 278 279 /* set memory mapping selection */ 280 clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); 281 } else { 282 debug("%s: cannot find st,mem_remap property\n", __func__); 283 } 284 285 dev_for_each_subnode(bank_node, dev) { 286 /* extract the bank index from DT */ 287 bank_name = (char *)ofnode_get_name(bank_node); 288 strsep(&bank_name, "@"); 289 if (!bank_name) { 290 pr_err("missing sdram bank index"); 291 return -EINVAL; 292 } 293 294 bank_params = ¶ms->bank_params[bank]; 295 strict_strtoul(bank_name, 10, 296 (long unsigned int *)&bank_params->target_bank); 297 298 if (bank_params->target_bank >= MAX_SDRAM_BANK) { 299 pr_err("Found bank %d , but only bank 0 and 1 are supported", 300 bank_params->target_bank); 301 return -EINVAL; 302 } 303 304 debug("Find bank %s %u\n", bank_name, bank_params->target_bank); 305 306 params->bank_params[bank].sdram_control = 307 (struct stm32_sdram_control *) 308 ofnode_read_u8_array_ptr(bank_node, 309 "st,sdram-control", 310 sizeof(struct stm32_sdram_control)); 311 312 if (!params->bank_params[bank].sdram_control) { 313 pr_err("st,sdram-control not found for %s", 314 ofnode_get_name(bank_node)); 315 return -EINVAL; 316 } 317 318 319 params->bank_params[bank].sdram_timing = 320 (struct stm32_sdram_timing *) 321 ofnode_read_u8_array_ptr(bank_node, 322 "st,sdram-timing", 323 sizeof(struct stm32_sdram_timing)); 324 325 if (!params->bank_params[bank].sdram_timing) { 326 pr_err("st,sdram-timing not found for %s", 327 ofnode_get_name(bank_node)); 328 return -EINVAL; 329 } 330 331 332 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, 333 "st,sdram-refcount", 8196); 334 bank++; 335 } 336 337 params->no_sdram_banks = bank; 338 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); 339 340 return 0; 341 } 342 343 static int stm32_fmc_probe(struct udevice *dev) 344 { 345 struct stm32_sdram_params *params = dev_get_platdata(dev); 346 int ret; 347 fdt_addr_t addr; 348 349 addr = dev_read_addr(dev); 350 if (addr == FDT_ADDR_T_NONE) 351 return -EINVAL; 352 353 params->base = (struct stm32_fmc_regs *)addr; 354 params->family = dev_get_driver_data(dev); 355 356 #ifdef CONFIG_CLK 357 struct clk clk; 358 359 ret = clk_get_by_index(dev, 0, &clk); 360 if (ret < 0) 361 return ret; 362 363 ret = clk_enable(&clk); 364 365 if (ret) { 366 dev_err(dev, "failed to enable clock\n"); 367 return ret; 368 } 369 #endif 370 ret = stm32_sdram_init(dev); 371 if (ret) 372 return ret; 373 374 return 0; 375 } 376 377 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) 378 { 379 return 0; 380 } 381 382 static struct ram_ops stm32_fmc_ops = { 383 .get_info = stm32_fmc_get_info, 384 }; 385 386 static const struct udevice_id stm32_fmc_ids[] = { 387 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, 388 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, 389 { } 390 }; 391 392 U_BOOT_DRIVER(stm32_fmc) = { 393 .name = "stm32_fmc", 394 .id = UCLASS_RAM, 395 .of_match = stm32_fmc_ids, 396 .ops = &stm32_fmc_ops, 397 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, 398 .probe = stm32_fmc_probe, 399 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), 400 }; 401