1403e9cbcSPhilipp Tomsich /* 2403e9cbcSPhilipp Tomsich * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 3403e9cbcSPhilipp Tomsich * 4403e9cbcSPhilipp Tomsich * SPDX-License-Identifier: GPL-2.0 5403e9cbcSPhilipp Tomsich */ 6403e9cbcSPhilipp Tomsich 7403e9cbcSPhilipp Tomsich #include <common.h> 8403e9cbcSPhilipp Tomsich #include <clk.h> 9403e9cbcSPhilipp Tomsich #include <dm.h> 10403e9cbcSPhilipp Tomsich #include <dt-bindings/memory/rk3368-dmc.h> 11403e9cbcSPhilipp Tomsich #include <dt-structs.h> 12403e9cbcSPhilipp Tomsich #include <ram.h> 13403e9cbcSPhilipp Tomsich #include <regmap.h> 14403e9cbcSPhilipp Tomsich #include <syscon.h> 15403e9cbcSPhilipp Tomsich #include <asm/io.h> 16403e9cbcSPhilipp Tomsich #include <asm/arch/clock.h> 17403e9cbcSPhilipp Tomsich #include <asm/arch/cru_rk3368.h> 18403e9cbcSPhilipp Tomsich #include <asm/arch/grf_rk3368.h> 19403e9cbcSPhilipp Tomsich #include <asm/arch/ddr_rk3368.h> 20403e9cbcSPhilipp Tomsich #include <asm/arch/sdram.h> 21403e9cbcSPhilipp Tomsich #include <asm/arch/sdram_common.h> 22403e9cbcSPhilipp Tomsich 23403e9cbcSPhilipp Tomsich DECLARE_GLOBAL_DATA_PTR; 24403e9cbcSPhilipp Tomsich 25403e9cbcSPhilipp Tomsich struct dram_info { 26403e9cbcSPhilipp Tomsich struct ram_info info; 27403e9cbcSPhilipp Tomsich struct clk ddr_clk; 28403e9cbcSPhilipp Tomsich struct rk3368_cru *cru; 29403e9cbcSPhilipp Tomsich struct rk3368_grf *grf; 30403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl; 31403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *phy; 32403e9cbcSPhilipp Tomsich struct rk3368_pmu_grf *pmugrf; 33403e9cbcSPhilipp Tomsich struct rk3368_msch *msch; 34403e9cbcSPhilipp Tomsich }; 35403e9cbcSPhilipp Tomsich 36403e9cbcSPhilipp Tomsich struct rk3368_sdram_params { 37403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA) 38403e9cbcSPhilipp Tomsich struct dtd_rockchip_rk3368_dmc of_plat; 39403e9cbcSPhilipp Tomsich #endif 40403e9cbcSPhilipp Tomsich struct rk3288_sdram_pctl_timing pctl_timing; 41403e9cbcSPhilipp Tomsich u32 trefi_mem_ddr3; 42403e9cbcSPhilipp Tomsich struct rk3288_sdram_channel chan; 43403e9cbcSPhilipp Tomsich struct regmap *map; 44403e9cbcSPhilipp Tomsich u32 ddr_freq; 45403e9cbcSPhilipp Tomsich u32 memory_schedule; 46403e9cbcSPhilipp Tomsich u32 ddr_speed_bin; 47403e9cbcSPhilipp Tomsich u32 tfaw_mult; 48403e9cbcSPhilipp Tomsich }; 49403e9cbcSPhilipp Tomsich 50403e9cbcSPhilipp Tomsich /* PTCL bits */ 51403e9cbcSPhilipp Tomsich enum { 52403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG0 */ 53403e9cbcSPhilipp Tomsich DFI_INIT_START = BIT(0), 54403e9cbcSPhilipp Tomsich DFI_DATA_BYTE_DISABLE_EN = BIT(2), 55403e9cbcSPhilipp Tomsich 56403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG1 */ 57403e9cbcSPhilipp Tomsich DFI_DRAM_CLK_SR_EN = BIT(0), 58403e9cbcSPhilipp Tomsich DFI_DRAM_CLK_DPD_EN = BIT(1), 59403e9cbcSPhilipp Tomsich ODT_LEN_BL8_W_SHIFT = 16, 60403e9cbcSPhilipp Tomsich 61403e9cbcSPhilipp Tomsich /* PCTL_DFISTCFG2 */ 62403e9cbcSPhilipp Tomsich DFI_PARITY_INTR_EN = BIT(0), 63403e9cbcSPhilipp Tomsich DFI_PARITY_EN = BIT(1), 64403e9cbcSPhilipp Tomsich 65403e9cbcSPhilipp Tomsich /* PCTL_DFILPCFG0 */ 66403e9cbcSPhilipp Tomsich TLP_RESP_TIME_SHIFT = 16, 67403e9cbcSPhilipp Tomsich LP_SR_EN = BIT(8), 68403e9cbcSPhilipp Tomsich LP_PD_EN = BIT(0), 69403e9cbcSPhilipp Tomsich 70403e9cbcSPhilipp Tomsich /* PCTL_DFIODTCFG */ 71403e9cbcSPhilipp Tomsich RANK0_ODT_WRITE_SEL = BIT(3), 72403e9cbcSPhilipp Tomsich RANK1_ODT_WRITE_SEL = BIT(11), 73403e9cbcSPhilipp Tomsich 74403e9cbcSPhilipp Tomsich /* PCTL_SCFG */ 75403e9cbcSPhilipp Tomsich HW_LOW_POWER_EN = BIT(0), 76403e9cbcSPhilipp Tomsich 77403e9cbcSPhilipp Tomsich /* PCTL_MCMD */ 78403e9cbcSPhilipp Tomsich START_CMD = BIT(31), 79403e9cbcSPhilipp Tomsich MCMD_RANK0 = BIT(20), 80403e9cbcSPhilipp Tomsich MCMD_RANK1 = BIT(21), 81403e9cbcSPhilipp Tomsich DESELECT_CMD = 0, 82403e9cbcSPhilipp Tomsich PREA_CMD, 83403e9cbcSPhilipp Tomsich REF_CMD, 84403e9cbcSPhilipp Tomsich MRS_CMD, 85403e9cbcSPhilipp Tomsich ZQCS_CMD, 86403e9cbcSPhilipp Tomsich ZQCL_CMD, 87403e9cbcSPhilipp Tomsich RSTL_CMD, 88403e9cbcSPhilipp Tomsich MRR_CMD = 8, 89403e9cbcSPhilipp Tomsich DPDE_CMD, 90403e9cbcSPhilipp Tomsich 91403e9cbcSPhilipp Tomsich /* PCTL_POWCTL */ 92403e9cbcSPhilipp Tomsich POWER_UP_START = BIT(0), 93403e9cbcSPhilipp Tomsich 94403e9cbcSPhilipp Tomsich /* PCTL_POWSTAT */ 95403e9cbcSPhilipp Tomsich POWER_UP_DONE = BIT(0), 96403e9cbcSPhilipp Tomsich 97403e9cbcSPhilipp Tomsich /* PCTL_SCTL */ 98403e9cbcSPhilipp Tomsich INIT_STATE = 0, 99403e9cbcSPhilipp Tomsich CFG_STATE, 100403e9cbcSPhilipp Tomsich GO_STATE, 101403e9cbcSPhilipp Tomsich SLEEP_STATE, 102403e9cbcSPhilipp Tomsich WAKEUP_STATE, 103403e9cbcSPhilipp Tomsich 104403e9cbcSPhilipp Tomsich /* PCTL_STAT */ 105403e9cbcSPhilipp Tomsich LP_TRIG_SHIFT = 4, 106403e9cbcSPhilipp Tomsich LP_TRIG_MASK = 7, 107403e9cbcSPhilipp Tomsich PCTL_STAT_MSK = 7, 108403e9cbcSPhilipp Tomsich INIT_MEM = 0, 109403e9cbcSPhilipp Tomsich CONFIG, 110403e9cbcSPhilipp Tomsich CONFIG_REQ, 111403e9cbcSPhilipp Tomsich ACCESS, 112403e9cbcSPhilipp Tomsich ACCESS_REQ, 113403e9cbcSPhilipp Tomsich LOW_POWER, 114403e9cbcSPhilipp Tomsich LOW_POWER_ENTRY_REQ, 115403e9cbcSPhilipp Tomsich LOW_POWER_EXIT_REQ, 116403e9cbcSPhilipp Tomsich 117403e9cbcSPhilipp Tomsich /* PCTL_MCFG */ 118403e9cbcSPhilipp Tomsich DDR2_DDR3_BL_8 = BIT(0), 119403e9cbcSPhilipp Tomsich DDR3_EN = BIT(5), 120403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT4 = (0 << 18), 121403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT5 = (1 << 18), 122403e9cbcSPhilipp Tomsich TFAW_TRRD_MULT6 = (2 << 18), 123403e9cbcSPhilipp Tomsich }; 124403e9cbcSPhilipp Tomsich 125403e9cbcSPhilipp Tomsich #define DDR3_MR0_WR(n) \ 126403e9cbcSPhilipp Tomsich ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) 127403e9cbcSPhilipp Tomsich #define DDR3_MR0_CL(n) \ 128403e9cbcSPhilipp Tomsich ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) 129403e9cbcSPhilipp Tomsich #define DDR3_MR0_BL8 \ 130403e9cbcSPhilipp Tomsich (0 << 0) 131403e9cbcSPhilipp Tomsich #define DDR3_MR0_DLL_RESET \ 132403e9cbcSPhilipp Tomsich (1 << 8) 133403e9cbcSPhilipp Tomsich #define DDR3_MR1_RTT120OHM \ 134403e9cbcSPhilipp Tomsich ((0 << 9) | (1 << 6) | (0 << 2)) 135403e9cbcSPhilipp Tomsich #define DDR3_MR2_TWL(n) \ 136403e9cbcSPhilipp Tomsich (((n - 5) & 0x7) << 3) 137403e9cbcSPhilipp Tomsich 138403e9cbcSPhilipp Tomsich 139403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD 140403e9cbcSPhilipp Tomsich 141403e9cbcSPhilipp Tomsich static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) 142403e9cbcSPhilipp Tomsich { 143403e9cbcSPhilipp Tomsich if (enable) 144403e9cbcSPhilipp Tomsich rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 145403e9cbcSPhilipp Tomsich else 146403e9cbcSPhilipp Tomsich rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); 147403e9cbcSPhilipp Tomsich } 148403e9cbcSPhilipp Tomsich 149403e9cbcSPhilipp Tomsich static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) 150403e9cbcSPhilipp Tomsich { 151403e9cbcSPhilipp Tomsich if (ddr3_mode) 152403e9cbcSPhilipp Tomsich rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 153403e9cbcSPhilipp Tomsich else 154403e9cbcSPhilipp Tomsich rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); 155403e9cbcSPhilipp Tomsich } 156403e9cbcSPhilipp Tomsich 157403e9cbcSPhilipp Tomsich static void ddrphy_config(struct rk3368_ddrphy *phy, 158403e9cbcSPhilipp Tomsich u32 tcl, u32 tal, u32 tcwl) 159403e9cbcSPhilipp Tomsich { 160403e9cbcSPhilipp Tomsich int i; 161403e9cbcSPhilipp Tomsich 162403e9cbcSPhilipp Tomsich /* Set to DDR3 mode */ 163403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[1], 0x3, 0x0); 164403e9cbcSPhilipp Tomsich 165403e9cbcSPhilipp Tomsich /* DDRPHY_REGB: CL, AL */ 166403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); 167403e9cbcSPhilipp Tomsich /* DDRPHY_REGC: CWL */ 168403e9cbcSPhilipp Tomsich clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); 169403e9cbcSPhilipp Tomsich 170403e9cbcSPhilipp Tomsich /* Update drive-strength */ 171403e9cbcSPhilipp Tomsich writel(0xcc, &phy->reg[0x11]); 172403e9cbcSPhilipp Tomsich writel(0xaa, &phy->reg[0x16]); 173403e9cbcSPhilipp Tomsich /* 174403e9cbcSPhilipp Tomsich * Update NRCOMP/PRCOMP for all 4 channels (for details of all 175403e9cbcSPhilipp Tomsich * affected registers refer to the documentation of DDRPHY_REG20 176403e9cbcSPhilipp Tomsich * and DDRPHY_REG21 in the RK3368 TRM. 177403e9cbcSPhilipp Tomsich */ 178403e9cbcSPhilipp Tomsich for (i = 0; i < 4; ++i) { 179403e9cbcSPhilipp Tomsich writel(0xcc, &phy->reg[0x20 + i * 0x10]); 180403e9cbcSPhilipp Tomsich writel(0x44, &phy->reg[0x21 + i * 0x10]); 181403e9cbcSPhilipp Tomsich } 182403e9cbcSPhilipp Tomsich 183403e9cbcSPhilipp Tomsich /* Enable write-leveling calibration bypass */ 184403e9cbcSPhilipp Tomsich setbits_le32(&phy->reg[2], BIT(3)); 185403e9cbcSPhilipp Tomsich } 186403e9cbcSPhilipp Tomsich 187403e9cbcSPhilipp Tomsich static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 188403e9cbcSPhilipp Tomsich { 189403e9cbcSPhilipp Tomsich int i; 190403e9cbcSPhilipp Tomsich 191403e9cbcSPhilipp Tomsich for (i = 0; i < n / sizeof(u32); i++) 192403e9cbcSPhilipp Tomsich writel(*src++, dest++); 193403e9cbcSPhilipp Tomsich } 194403e9cbcSPhilipp Tomsich 195403e9cbcSPhilipp Tomsich static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) 196403e9cbcSPhilipp Tomsich { 197403e9cbcSPhilipp Tomsich u32 mcmd = START_CMD | cmd | rank; 198403e9cbcSPhilipp Tomsich 199403e9cbcSPhilipp Tomsich debug("%s: writing %x to MCMD\n", __func__, mcmd); 200403e9cbcSPhilipp Tomsich writel(mcmd, &pctl->mcmd); 201403e9cbcSPhilipp Tomsich while (readl(&pctl->mcmd) & START_CMD) 202403e9cbcSPhilipp Tomsich /* spin */; 203403e9cbcSPhilipp Tomsich } 204403e9cbcSPhilipp Tomsich 205403e9cbcSPhilipp Tomsich static void send_mrs(struct rk3368_ddr_pctl *pctl, 206403e9cbcSPhilipp Tomsich u32 rank, u32 mr_num, u32 mr_data) 207403e9cbcSPhilipp Tomsich { 208403e9cbcSPhilipp Tomsich u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4); 209403e9cbcSPhilipp Tomsich 210403e9cbcSPhilipp Tomsich debug("%s: writing %x to MCMD\n", __func__, mcmd); 211403e9cbcSPhilipp Tomsich writel(mcmd, &pctl->mcmd); 212403e9cbcSPhilipp Tomsich while (readl(&pctl->mcmd) & START_CMD) 213403e9cbcSPhilipp Tomsich /* spin */; 214403e9cbcSPhilipp Tomsich } 215403e9cbcSPhilipp Tomsich 216403e9cbcSPhilipp Tomsich static int memory_init(struct rk3368_ddr_pctl *pctl, 217403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params) 218403e9cbcSPhilipp Tomsich { 219403e9cbcSPhilipp Tomsich u32 mr[4]; 220403e9cbcSPhilipp Tomsich const ulong timeout_ms = 500; 221403e9cbcSPhilipp Tomsich ulong tmp; 222403e9cbcSPhilipp Tomsich 223403e9cbcSPhilipp Tomsich /* 224403e9cbcSPhilipp Tomsich * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and 225403e9cbcSPhilipp Tomsich * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register 226403e9cbcSPhilipp Tomsich * of PCTL. 227403e9cbcSPhilipp Tomsich */ 228403e9cbcSPhilipp Tomsich writel(POWER_UP_START, &pctl->powctl); 229403e9cbcSPhilipp Tomsich 230403e9cbcSPhilipp Tomsich tmp = get_timer(0); 231403e9cbcSPhilipp Tomsich do { 232403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) { 233403e9cbcSPhilipp Tomsich error("%s: POWER_UP_START did not complete in %ld ms\n", 234403e9cbcSPhilipp Tomsich __func__, timeout_ms); 235403e9cbcSPhilipp Tomsich return -ETIME; 236403e9cbcSPhilipp Tomsich } 237403e9cbcSPhilipp Tomsich } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); 238403e9cbcSPhilipp Tomsich 239403e9cbcSPhilipp Tomsich /* Configure MR0 through MR3 */ 240403e9cbcSPhilipp Tomsich mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) | 241403e9cbcSPhilipp Tomsich DDR3_MR0_CL(params->pctl_timing.tcl) | 242403e9cbcSPhilipp Tomsich DDR3_MR0_DLL_RESET; 243403e9cbcSPhilipp Tomsich mr[1] = DDR3_MR1_RTT120OHM; 244403e9cbcSPhilipp Tomsich mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); 245403e9cbcSPhilipp Tomsich mr[3] = 0; 246403e9cbcSPhilipp Tomsich 247403e9cbcSPhilipp Tomsich /* 248403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual: 249403e9cbcSPhilipp Tomsich * "16.6.2 Initialization (DDR3 Initialization Sequence)" 250403e9cbcSPhilipp Tomsich */ 251403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); 252403e9cbcSPhilipp Tomsich udelay(1); 253403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 254403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); 255403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); 256403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); 257403e9cbcSPhilipp Tomsich send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); 258403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); 259403e9cbcSPhilipp Tomsich 260403e9cbcSPhilipp Tomsich return 0; 261403e9cbcSPhilipp Tomsich } 262403e9cbcSPhilipp Tomsich 263403e9cbcSPhilipp Tomsich static void move_to_config_state(struct rk3368_ddr_pctl *pctl) 264403e9cbcSPhilipp Tomsich { 265403e9cbcSPhilipp Tomsich /* 266403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual: 267403e9cbcSPhilipp Tomsich * "16.6.1 State transition of PCTL (Moving to Config State)" 268403e9cbcSPhilipp Tomsich */ 269403e9cbcSPhilipp Tomsich u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 270403e9cbcSPhilipp Tomsich 271403e9cbcSPhilipp Tomsich switch (state) { 272403e9cbcSPhilipp Tomsich case LOW_POWER: 273403e9cbcSPhilipp Tomsich writel(WAKEUP_STATE, &pctl->sctl); 274403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 275403e9cbcSPhilipp Tomsich /* spin */; 276403e9cbcSPhilipp Tomsich 277403e9cbcSPhilipp Tomsich /* fall-through */ 278403e9cbcSPhilipp Tomsich case ACCESS: 279403e9cbcSPhilipp Tomsich case INIT_MEM: 280403e9cbcSPhilipp Tomsich writel(CFG_STATE, &pctl->sctl); 281403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 282403e9cbcSPhilipp Tomsich /* spin */; 283403e9cbcSPhilipp Tomsich break; 284403e9cbcSPhilipp Tomsich 285403e9cbcSPhilipp Tomsich case CONFIG: 286403e9cbcSPhilipp Tomsich return; 287403e9cbcSPhilipp Tomsich 288403e9cbcSPhilipp Tomsich default: 289403e9cbcSPhilipp Tomsich break; 290403e9cbcSPhilipp Tomsich } 291403e9cbcSPhilipp Tomsich } 292403e9cbcSPhilipp Tomsich 293403e9cbcSPhilipp Tomsich static void move_to_access_state(struct rk3368_ddr_pctl *pctl) 294403e9cbcSPhilipp Tomsich { 295403e9cbcSPhilipp Tomsich /* 296403e9cbcSPhilipp Tomsich * Also see RK3368 Technical Reference Manual: 297403e9cbcSPhilipp Tomsich * "16.6.1 State transition of PCTL (Moving to Access State)" 298403e9cbcSPhilipp Tomsich */ 299403e9cbcSPhilipp Tomsich u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; 300403e9cbcSPhilipp Tomsich 301403e9cbcSPhilipp Tomsich switch (state) { 302403e9cbcSPhilipp Tomsich case LOW_POWER: 303403e9cbcSPhilipp Tomsich if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & 304403e9cbcSPhilipp Tomsich LP_TRIG_MASK) == 1) 305403e9cbcSPhilipp Tomsich return; 306403e9cbcSPhilipp Tomsich 307403e9cbcSPhilipp Tomsich writel(WAKEUP_STATE, &pctl->sctl); 308403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) 309403e9cbcSPhilipp Tomsich /* spin */; 310403e9cbcSPhilipp Tomsich 311403e9cbcSPhilipp Tomsich /* fall-through */ 312403e9cbcSPhilipp Tomsich case INIT_MEM: 313403e9cbcSPhilipp Tomsich writel(CFG_STATE, &pctl->sctl); 314403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) 315403e9cbcSPhilipp Tomsich /* spin */; 316403e9cbcSPhilipp Tomsich 317403e9cbcSPhilipp Tomsich /* fall-through */ 318403e9cbcSPhilipp Tomsich case CONFIG: 319403e9cbcSPhilipp Tomsich writel(GO_STATE, &pctl->sctl); 320403e9cbcSPhilipp Tomsich while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) 321403e9cbcSPhilipp Tomsich /* spin */; 322403e9cbcSPhilipp Tomsich break; 323403e9cbcSPhilipp Tomsich 324403e9cbcSPhilipp Tomsich case ACCESS: 325403e9cbcSPhilipp Tomsich return; 326403e9cbcSPhilipp Tomsich 327403e9cbcSPhilipp Tomsich default: 328403e9cbcSPhilipp Tomsich break; 329403e9cbcSPhilipp Tomsich } 330403e9cbcSPhilipp Tomsich } 331403e9cbcSPhilipp Tomsich 332403e9cbcSPhilipp Tomsich static void ddrctl_reset(struct rk3368_cru *cru) 333403e9cbcSPhilipp Tomsich { 334403e9cbcSPhilipp Tomsich const u32 ctl_reset = BIT(3) | BIT(2); 335403e9cbcSPhilipp Tomsich const u32 phy_reset = BIT(1) | BIT(0); 336403e9cbcSPhilipp Tomsich 337403e9cbcSPhilipp Tomsich /* 338403e9cbcSPhilipp Tomsich * The PHY reset should be released before the PCTL reset. 339403e9cbcSPhilipp Tomsich * 340403e9cbcSPhilipp Tomsich * Note that the following sequence (including the number of 341403e9cbcSPhilipp Tomsich * us to delay between releasing the PHY and PCTL reset) has 342403e9cbcSPhilipp Tomsich * been adapted per feedback received from Rockchips, so do 343403e9cbcSPhilipp Tomsich * not try to optimise. 344403e9cbcSPhilipp Tomsich */ 345403e9cbcSPhilipp Tomsich rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); 346403e9cbcSPhilipp Tomsich udelay(1); 347403e9cbcSPhilipp Tomsich rk_clrreg(&cru->softrst_con[10], phy_reset); 348403e9cbcSPhilipp Tomsich udelay(5); 349403e9cbcSPhilipp Tomsich rk_clrreg(&cru->softrst_con[10], ctl_reset); 350403e9cbcSPhilipp Tomsich } 351403e9cbcSPhilipp Tomsich 352403e9cbcSPhilipp Tomsich static void ddrphy_reset(struct rk3368_ddrphy *ddrphy) 353403e9cbcSPhilipp Tomsich { 354403e9cbcSPhilipp Tomsich /* 355403e9cbcSPhilipp Tomsich * The analog part of the PHY should be release at least 1000 356403e9cbcSPhilipp Tomsich * DRAM cycles before the digital part of the PHY (waiting for 357403e9cbcSPhilipp Tomsich * 5us will ensure this for a DRAM clock as low as 200MHz). 358403e9cbcSPhilipp Tomsich */ 359403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); 360403e9cbcSPhilipp Tomsich udelay(1); 361403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0], BIT(2)); 362403e9cbcSPhilipp Tomsich udelay(5); 363403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0], BIT(3)); 364403e9cbcSPhilipp Tomsich } 365403e9cbcSPhilipp Tomsich 366403e9cbcSPhilipp Tomsich static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) 367403e9cbcSPhilipp Tomsich { 368403e9cbcSPhilipp Tomsich u32 dqs_dll_delay; 369403e9cbcSPhilipp Tomsich 370403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x13], BIT(4)); 371403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x14], BIT(3)); 372403e9cbcSPhilipp Tomsich 373403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x26], BIT(4)); 374403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x27], BIT(3)); 375403e9cbcSPhilipp Tomsich 376403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x36], BIT(4)); 377403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x37], BIT(3)); 378403e9cbcSPhilipp Tomsich 379403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x46], BIT(4)); 380403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x47], BIT(3)); 381403e9cbcSPhilipp Tomsich 382403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0x56], BIT(4)); 383403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0x57], BIT(3)); 384403e9cbcSPhilipp Tomsich 385403e9cbcSPhilipp Tomsich if (freq <= 400000000) 386403e9cbcSPhilipp Tomsich setbits_le32(&ddrphy->reg[0xa4], 0x1f); 387403e9cbcSPhilipp Tomsich else 388403e9cbcSPhilipp Tomsich clrbits_le32(&ddrphy->reg[0xa4], 0x1f); 389403e9cbcSPhilipp Tomsich 390403e9cbcSPhilipp Tomsich if (freq < 681000000) 391403e9cbcSPhilipp Tomsich dqs_dll_delay = 3; /* 67.5 degree delay */ 392403e9cbcSPhilipp Tomsich else 393403e9cbcSPhilipp Tomsich dqs_dll_delay = 2; /* 45 degree delay */ 394403e9cbcSPhilipp Tomsich 395403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x28]); 396403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x38]); 397403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x48]); 398403e9cbcSPhilipp Tomsich writel(dqs_dll_delay, &ddrphy->reg[0x58]); 399403e9cbcSPhilipp Tomsich } 400403e9cbcSPhilipp Tomsich 401403e9cbcSPhilipp Tomsich static int dfi_cfg(struct rk3368_ddr_pctl *pctl) 402403e9cbcSPhilipp Tomsich { 403403e9cbcSPhilipp Tomsich const ulong timeout_ms = 200; 404403e9cbcSPhilipp Tomsich ulong tmp; 405403e9cbcSPhilipp Tomsich 406403e9cbcSPhilipp Tomsich writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); 407403e9cbcSPhilipp Tomsich 408403e9cbcSPhilipp Tomsich writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, 409403e9cbcSPhilipp Tomsich &pctl->dfistcfg1); 410403e9cbcSPhilipp Tomsich writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 411403e9cbcSPhilipp Tomsich writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 412403e9cbcSPhilipp Tomsich &pctl->dfilpcfg0); 413403e9cbcSPhilipp Tomsich 414403e9cbcSPhilipp Tomsich writel(1, &pctl->dfitphyupdtype0); 415403e9cbcSPhilipp Tomsich 416403e9cbcSPhilipp Tomsich writel(0x1f, &pctl->dfitphyrdlat); 417403e9cbcSPhilipp Tomsich writel(0, &pctl->dfitphywrdata); 418403e9cbcSPhilipp Tomsich writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ 419403e9cbcSPhilipp Tomsich 420403e9cbcSPhilipp Tomsich setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); 421403e9cbcSPhilipp Tomsich 422403e9cbcSPhilipp Tomsich tmp = get_timer(0); 423403e9cbcSPhilipp Tomsich do { 424403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) { 425403e9cbcSPhilipp Tomsich error("%s: DFI init did not complete within %ld ms\n", 426403e9cbcSPhilipp Tomsich __func__, timeout_ms); 427403e9cbcSPhilipp Tomsich return -ETIME; 428403e9cbcSPhilipp Tomsich } 429403e9cbcSPhilipp Tomsich } while ((readl(&pctl->dfiststat0) & 1) == 0); 430403e9cbcSPhilipp Tomsich 431403e9cbcSPhilipp Tomsich return 0; 432403e9cbcSPhilipp Tomsich } 433403e9cbcSPhilipp Tomsich 434403e9cbcSPhilipp Tomsich static inline u32 ps_to_tCK(const u32 ps, const ulong freq) 435403e9cbcSPhilipp Tomsich { 436403e9cbcSPhilipp Tomsich const ulong MHz = 1000000; 437403e9cbcSPhilipp Tomsich return DIV_ROUND_UP(ps * freq, 1000000 * MHz); 438403e9cbcSPhilipp Tomsich } 439403e9cbcSPhilipp Tomsich 440403e9cbcSPhilipp Tomsich static inline u32 ns_to_tCK(const u32 ns, const ulong freq) 441403e9cbcSPhilipp Tomsich { 442403e9cbcSPhilipp Tomsich return ps_to_tCK(ns * 1000, freq); 443403e9cbcSPhilipp Tomsich } 444403e9cbcSPhilipp Tomsich 445403e9cbcSPhilipp Tomsich static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) 446403e9cbcSPhilipp Tomsich { 447403e9cbcSPhilipp Tomsich const ulong MHz = 1000000; 448403e9cbcSPhilipp Tomsich return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); 449403e9cbcSPhilipp Tomsich } 450403e9cbcSPhilipp Tomsich 451403e9cbcSPhilipp Tomsich static int pctl_calc_timings(struct rk3368_sdram_params *params, 452403e9cbcSPhilipp Tomsich ulong freq) 453403e9cbcSPhilipp Tomsich { 454403e9cbcSPhilipp Tomsich struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; 455403e9cbcSPhilipp Tomsich const ulong MHz = 1000000; 456403e9cbcSPhilipp Tomsich u32 tccd; 457403e9cbcSPhilipp Tomsich u32 tfaw_as_ps; 458403e9cbcSPhilipp Tomsich 459403e9cbcSPhilipp Tomsich if (params->ddr_speed_bin != DDR3_1600K) { 460403e9cbcSPhilipp Tomsich error("%s: unimplemented DDR3 speed bin %d\n", 461403e9cbcSPhilipp Tomsich __func__, params->ddr_speed_bin); 462403e9cbcSPhilipp Tomsich return -1; 463403e9cbcSPhilipp Tomsich } 464403e9cbcSPhilipp Tomsich 465403e9cbcSPhilipp Tomsich /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ 466403e9cbcSPhilipp Tomsich pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz); 467403e9cbcSPhilipp Tomsich pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz); 468403e9cbcSPhilipp Tomsich 469403e9cbcSPhilipp Tomsich pctl_timing->tinit = 200; /* 200 usec */ 470403e9cbcSPhilipp Tomsich pctl_timing->trsth = 500; /* 500 usec */ 471403e9cbcSPhilipp Tomsich pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */ 472403e9cbcSPhilipp Tomsich params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq); 473403e9cbcSPhilipp Tomsich 474403e9cbcSPhilipp Tomsich if (freq <= (400 * MHz)) { 475403e9cbcSPhilipp Tomsich pctl_timing->tcl = 6; 476403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 10; 477403e9cbcSPhilipp Tomsich } else if (freq <= (533 * MHz)) { 478403e9cbcSPhilipp Tomsich pctl_timing->tcl = 8; 479403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 6; 480403e9cbcSPhilipp Tomsich } else if (freq <= (666 * MHz)) { 481403e9cbcSPhilipp Tomsich pctl_timing->tcl = 10; 482403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 7; 483403e9cbcSPhilipp Tomsich } else { 484403e9cbcSPhilipp Tomsich pctl_timing->tcl = 11; 485403e9cbcSPhilipp Tomsich pctl_timing->tcwl = 8; 486403e9cbcSPhilipp Tomsich } 487403e9cbcSPhilipp Tomsich 488403e9cbcSPhilipp Tomsich pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */ 489403e9cbcSPhilipp Tomsich pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */ 490403e9cbcSPhilipp Tomsich pctl_timing->trp = max(4u, ps_to_tCK(13750, freq)); 491403e9cbcSPhilipp Tomsich /* 492403e9cbcSPhilipp Tomsich * JESD-79: 493403e9cbcSPhilipp Tomsich * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL 494403e9cbcSPhilipp Tomsich */ 495403e9cbcSPhilipp Tomsich tccd = 4; 496403e9cbcSPhilipp Tomsich pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; 497403e9cbcSPhilipp Tomsich pctl_timing->tal = 0; 498403e9cbcSPhilipp Tomsich pctl_timing->tras = ps_to_tCK(35000, freq); 499403e9cbcSPhilipp Tomsich pctl_timing->trc = ps_to_tCK(48750, freq); 500403e9cbcSPhilipp Tomsich pctl_timing->trcd = ps_to_tCK(13750, freq); 501403e9cbcSPhilipp Tomsich pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); 502403e9cbcSPhilipp Tomsich pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq)); 503403e9cbcSPhilipp Tomsich pctl_timing->twr = ps_to_tCK(15000, freq); 504403e9cbcSPhilipp Tomsich /* The DDR3 mode-register does only support even values for tWR > 8. */ 505403e9cbcSPhilipp Tomsich if (pctl_timing->twr > 8) 506403e9cbcSPhilipp Tomsich pctl_timing->twr = (pctl_timing->twr + 1) & ~1; 507403e9cbcSPhilipp Tomsich pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq)); 508403e9cbcSPhilipp Tomsich pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */ 509403e9cbcSPhilipp Tomsich pctl_timing->txp = max(3u, ps_to_tCK(6000, freq)); 510403e9cbcSPhilipp Tomsich pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq)); 511403e9cbcSPhilipp Tomsich pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq)); 512403e9cbcSPhilipp Tomsich pctl_timing->tzqcsi = 10000; /* as used by Rockchip */ 513403e9cbcSPhilipp Tomsich pctl_timing->tdqs = 1; /* fixed for DDR3 */ 514403e9cbcSPhilipp Tomsich pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); 515403e9cbcSPhilipp Tomsich pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); 516403e9cbcSPhilipp Tomsich pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); 517403e9cbcSPhilipp Tomsich pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq)); 518403e9cbcSPhilipp Tomsich pctl_timing->trstl = ns_to_tCK(100, freq); 519403e9cbcSPhilipp Tomsich pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ 520403e9cbcSPhilipp Tomsich pctl_timing->tmrr = 0; 521403e9cbcSPhilipp Tomsich pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ 522403e9cbcSPhilipp Tomsich pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */ 523403e9cbcSPhilipp Tomsich 524403e9cbcSPhilipp Tomsich 525403e9cbcSPhilipp Tomsich /* 526403e9cbcSPhilipp Tomsich * The controller can represent tFAW as 4x, 5x or 6x tRRD only. 527403e9cbcSPhilipp Tomsich * We want to use the smallest multiplier that satisfies the tFAW 528403e9cbcSPhilipp Tomsich * requirements of the given speed-bin. If necessary, we stretch out 529403e9cbcSPhilipp Tomsich * tRRD to allow us to operate on a 6x multiplier for tFAW. 530403e9cbcSPhilipp Tomsich */ 531403e9cbcSPhilipp Tomsich tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ 532403e9cbcSPhilipp Tomsich if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { 533403e9cbcSPhilipp Tomsich /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ 534403e9cbcSPhilipp Tomsich pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); 535403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT6; 536403e9cbcSPhilipp Tomsich } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { 537403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT6; 538403e9cbcSPhilipp Tomsich } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { 539403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT5; 540403e9cbcSPhilipp Tomsich } else { 541403e9cbcSPhilipp Tomsich params->tfaw_mult = TFAW_TRRD_MULT4; 542403e9cbcSPhilipp Tomsich } 543403e9cbcSPhilipp Tomsich 544403e9cbcSPhilipp Tomsich return 0; 545403e9cbcSPhilipp Tomsich } 546403e9cbcSPhilipp Tomsich 547403e9cbcSPhilipp Tomsich static void pctl_cfg(struct rk3368_ddr_pctl *pctl, 548403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params, 549403e9cbcSPhilipp Tomsich struct rk3368_grf *grf) 550403e9cbcSPhilipp Tomsich { 551403e9cbcSPhilipp Tomsich /* Configure PCTL timing registers */ 552403e9cbcSPhilipp Tomsich params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */ 553403e9cbcSPhilipp Tomsich copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, 554403e9cbcSPhilipp Tomsich sizeof(params->pctl_timing)); 555403e9cbcSPhilipp Tomsich writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); 556403e9cbcSPhilipp Tomsich 557403e9cbcSPhilipp Tomsich /* Set up ODT write selector and ODT write length */ 558403e9cbcSPhilipp Tomsich writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); 559403e9cbcSPhilipp Tomsich writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 560403e9cbcSPhilipp Tomsich 561403e9cbcSPhilipp Tomsich /* Set up the CL/CWL-dependent timings of DFI */ 562403e9cbcSPhilipp Tomsich writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); 563403e9cbcSPhilipp Tomsich writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); 564403e9cbcSPhilipp Tomsich 565403e9cbcSPhilipp Tomsich /* DDR3 */ 566403e9cbcSPhilipp Tomsich writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); 567403e9cbcSPhilipp Tomsich writel(0x001c0004, &grf->ddrc0_con0); 568403e9cbcSPhilipp Tomsich 569403e9cbcSPhilipp Tomsich setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); 570403e9cbcSPhilipp Tomsich } 571403e9cbcSPhilipp Tomsich 572403e9cbcSPhilipp Tomsich static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, 573403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy) 574403e9cbcSPhilipp Tomsich { 575403e9cbcSPhilipp Tomsich const u32 trefi = readl(&pctl->trefi); 576403e9cbcSPhilipp Tomsich const ulong timeout_ms = 500; 577403e9cbcSPhilipp Tomsich ulong tmp; 578403e9cbcSPhilipp Tomsich 579403e9cbcSPhilipp Tomsich /* disable auto-refresh */ 580403e9cbcSPhilipp Tomsich writel(0 | BIT(31), &pctl->trefi); 581403e9cbcSPhilipp Tomsich 582403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 583403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21); 584403e9cbcSPhilipp Tomsich 585403e9cbcSPhilipp Tomsich tmp = get_timer(0); 586403e9cbcSPhilipp Tomsich do { 587403e9cbcSPhilipp Tomsich if (get_timer(tmp) > timeout_ms) { 588403e9cbcSPhilipp Tomsich error("%s: did not complete within %ld ms\n", 589403e9cbcSPhilipp Tomsich __func__, timeout_ms); 590403e9cbcSPhilipp Tomsich return -ETIME; 591403e9cbcSPhilipp Tomsich } 592403e9cbcSPhilipp Tomsich } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf); 593403e9cbcSPhilipp Tomsich 594403e9cbcSPhilipp Tomsich send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); 595403e9cbcSPhilipp Tomsich clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); 596403e9cbcSPhilipp Tomsich /* resume auto-refresh */ 597403e9cbcSPhilipp Tomsich writel(trefi | BIT(31), &pctl->trefi); 598403e9cbcSPhilipp Tomsich 599403e9cbcSPhilipp Tomsich return 0; 600403e9cbcSPhilipp Tomsich } 601403e9cbcSPhilipp Tomsich 602403e9cbcSPhilipp Tomsich static int sdram_col_row_detect(struct udevice *dev) 603403e9cbcSPhilipp Tomsich { 604403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev); 605403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev); 606403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl = priv->pctl; 607403e9cbcSPhilipp Tomsich struct rk3368_msch *msch = priv->msch; 608403e9cbcSPhilipp Tomsich const u32 test_pattern = 0x5aa5f00f; 609403e9cbcSPhilipp Tomsich int row, col; 610403e9cbcSPhilipp Tomsich uintptr_t addr; 611403e9cbcSPhilipp Tomsich 612403e9cbcSPhilipp Tomsich move_to_config_state(pctl); 613403e9cbcSPhilipp Tomsich writel(6, &msch->ddrconf); 614403e9cbcSPhilipp Tomsich move_to_access_state(pctl); 615403e9cbcSPhilipp Tomsich 616403e9cbcSPhilipp Tomsich /* Detect col */ 617403e9cbcSPhilipp Tomsich for (col = 11; col >= 9; col--) { 618403e9cbcSPhilipp Tomsich writel(0, CONFIG_SYS_SDRAM_BASE); 619403e9cbcSPhilipp Tomsich addr = CONFIG_SYS_SDRAM_BASE + 620403e9cbcSPhilipp Tomsich (1 << (col + params->chan.bw - 1)); 621403e9cbcSPhilipp Tomsich writel(test_pattern, addr); 622403e9cbcSPhilipp Tomsich if ((readl(addr) == test_pattern) && 623403e9cbcSPhilipp Tomsich (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 624403e9cbcSPhilipp Tomsich break; 625403e9cbcSPhilipp Tomsich } 626403e9cbcSPhilipp Tomsich 627403e9cbcSPhilipp Tomsich if (col == 8) { 628403e9cbcSPhilipp Tomsich error("%s: col detect error\n", __func__); 629403e9cbcSPhilipp Tomsich return -EINVAL; 630403e9cbcSPhilipp Tomsich } 631403e9cbcSPhilipp Tomsich 632403e9cbcSPhilipp Tomsich move_to_config_state(pctl); 633403e9cbcSPhilipp Tomsich writel(15, &msch->ddrconf); 634403e9cbcSPhilipp Tomsich move_to_access_state(pctl); 635403e9cbcSPhilipp Tomsich 636403e9cbcSPhilipp Tomsich /* Detect row*/ 637403e9cbcSPhilipp Tomsich for (row = 16; row >= 12; row--) { 638403e9cbcSPhilipp Tomsich writel(0, CONFIG_SYS_SDRAM_BASE); 639403e9cbcSPhilipp Tomsich addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); 640403e9cbcSPhilipp Tomsich writel(test_pattern, addr); 641403e9cbcSPhilipp Tomsich if ((readl(addr) == test_pattern) && 642403e9cbcSPhilipp Tomsich (readl(CONFIG_SYS_SDRAM_BASE) == 0)) 643403e9cbcSPhilipp Tomsich break; 644403e9cbcSPhilipp Tomsich } 645403e9cbcSPhilipp Tomsich 646403e9cbcSPhilipp Tomsich if (row == 11) { 647403e9cbcSPhilipp Tomsich error("%s: row detect error\n", __func__); 648403e9cbcSPhilipp Tomsich return -EINVAL; 649403e9cbcSPhilipp Tomsich } 650403e9cbcSPhilipp Tomsich 651403e9cbcSPhilipp Tomsich /* Record results */ 652403e9cbcSPhilipp Tomsich debug("%s: col %d, row %d\n", __func__, col, row); 653403e9cbcSPhilipp Tomsich params->chan.col = col; 654403e9cbcSPhilipp Tomsich params->chan.cs0_row = row; 655403e9cbcSPhilipp Tomsich params->chan.cs1_row = row; 656403e9cbcSPhilipp Tomsich params->chan.row_3_4 = 0; 657403e9cbcSPhilipp Tomsich 658403e9cbcSPhilipp Tomsich return 0; 659403e9cbcSPhilipp Tomsich } 660403e9cbcSPhilipp Tomsich 661403e9cbcSPhilipp Tomsich static int msch_niu_config(struct rk3368_msch *msch, 662403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params) 663403e9cbcSPhilipp Tomsich { 664403e9cbcSPhilipp Tomsich int i; 665403e9cbcSPhilipp Tomsich const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); 666403e9cbcSPhilipp Tomsich const u8 rows = params->chan.cs0_row; 667403e9cbcSPhilipp Tomsich 668403e9cbcSPhilipp Tomsich /* 669403e9cbcSPhilipp Tomsich * The DDR address-translation table always assumes a 32bit 670403e9cbcSPhilipp Tomsich * bus and the comparison below takes care of adjusting for 671403e9cbcSPhilipp Tomsich * a 16bit bus (i.e. one column-address is consumed). 672403e9cbcSPhilipp Tomsich */ 673403e9cbcSPhilipp Tomsich const struct { 674403e9cbcSPhilipp Tomsich u8 rows; 675403e9cbcSPhilipp Tomsich u8 columns; 676403e9cbcSPhilipp Tomsich u8 type; 677403e9cbcSPhilipp Tomsich } ddrconf_table[] = { 678403e9cbcSPhilipp Tomsich /* 679403e9cbcSPhilipp Tomsich * C-B-R-D patterns are first. For these we require an 680403e9cbcSPhilipp Tomsich * exact match for the columns and rows (as there's 681403e9cbcSPhilipp Tomsich * one entry per possible configuration). 682403e9cbcSPhilipp Tomsich */ 683403e9cbcSPhilipp Tomsich [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD }, 684403e9cbcSPhilipp Tomsich [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD }, 685403e9cbcSPhilipp Tomsich [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD }, 686403e9cbcSPhilipp Tomsich [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD }, 687403e9cbcSPhilipp Tomsich [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD }, 688403e9cbcSPhilipp Tomsich [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD }, 689403e9cbcSPhilipp Tomsich [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD }, 690403e9cbcSPhilipp Tomsich [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD }, 691403e9cbcSPhilipp Tomsich [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD }, 692403e9cbcSPhilipp Tomsich [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD }, 693403e9cbcSPhilipp Tomsich [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD }, 694403e9cbcSPhilipp Tomsich /* 695403e9cbcSPhilipp Tomsich * 11 through 13 are C-R-B-D patterns. These are 696403e9cbcSPhilipp Tomsich * matched for an exact number of columns and to 697403e9cbcSPhilipp Tomsich * ensure that the hardware uses at least as many rows 698403e9cbcSPhilipp Tomsich * as the pattern requires (i.e. we make sure that 699403e9cbcSPhilipp Tomsich * there's no gaps up until we hit the device/chip-select; 700403e9cbcSPhilipp Tomsich * however, these patterns can accept up to 16 rows, 701403e9cbcSPhilipp Tomsich * as the row-address continues right after the CS 702403e9cbcSPhilipp Tomsich * switching) 703403e9cbcSPhilipp Tomsich */ 704403e9cbcSPhilipp Tomsich [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD }, 705403e9cbcSPhilipp Tomsich [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD }, 706403e9cbcSPhilipp Tomsich [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD }, 707403e9cbcSPhilipp Tomsich /* 708403e9cbcSPhilipp Tomsich * 14 and 15 are catch-all variants using a C-B-D-R 709403e9cbcSPhilipp Tomsich * scheme (i.e. alternating the chip-select every time 710403e9cbcSPhilipp Tomsich * C-B overflows) and stuffing the remaining C-bits 711403e9cbcSPhilipp Tomsich * into the top. Matching needs to make sure that the 712403e9cbcSPhilipp Tomsich * number of columns is either an exact match (i.e. we 713403e9cbcSPhilipp Tomsich * can use less the the maximum number of rows) -or- 714403e9cbcSPhilipp Tomsich * that the columns exceed what is given in this table 715403e9cbcSPhilipp Tomsich * and the rows are an exact match (in which case the 716403e9cbcSPhilipp Tomsich * remaining C-bits will be stuffed onto the top after 717403e9cbcSPhilipp Tomsich * the device/chip-select switches). 718403e9cbcSPhilipp Tomsich */ 719403e9cbcSPhilipp Tomsich [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR }, 720403e9cbcSPhilipp Tomsich [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR }, 721403e9cbcSPhilipp Tomsich }; 722403e9cbcSPhilipp Tomsich 723403e9cbcSPhilipp Tomsich /* 724403e9cbcSPhilipp Tomsich * For C-B-R-D, we need an exact match (i.e. both for the number of 725403e9cbcSPhilipp Tomsich * columns and rows), while for C-B-D-R, only the the number of 726403e9cbcSPhilipp Tomsich * columns needs to match. 727403e9cbcSPhilipp Tomsich */ 728403e9cbcSPhilipp Tomsich for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) { 729403e9cbcSPhilipp Tomsich bool match = false; 730403e9cbcSPhilipp Tomsich 731403e9cbcSPhilipp Tomsich /* If this entry if for a different matcher, then skip it */ 732403e9cbcSPhilipp Tomsich if (ddrconf_table[i].type != params->memory_schedule) 733403e9cbcSPhilipp Tomsich continue; 734403e9cbcSPhilipp Tomsich 735403e9cbcSPhilipp Tomsich /* 736403e9cbcSPhilipp Tomsich * Match according to the rules (exact/inexact/at-least) 737403e9cbcSPhilipp Tomsich * documented in the ddrconf_table above. 738403e9cbcSPhilipp Tomsich */ 739403e9cbcSPhilipp Tomsich switch (params->memory_schedule) { 740403e9cbcSPhilipp Tomsich case DMC_MSCH_CBRD: 741403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) && 742403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows == rows); 743403e9cbcSPhilipp Tomsich break; 744403e9cbcSPhilipp Tomsich 745403e9cbcSPhilipp Tomsich case DMC_MSCH_CRBD: 746403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) && 747403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows <= rows); 748403e9cbcSPhilipp Tomsich break; 749403e9cbcSPhilipp Tomsich 750403e9cbcSPhilipp Tomsich case DMC_MSCH_CBDR: 751403e9cbcSPhilipp Tomsich match = (ddrconf_table[i].columns == cols) || 752403e9cbcSPhilipp Tomsich ((ddrconf_table[i].columns <= cols) && 753403e9cbcSPhilipp Tomsich (ddrconf_table[i].rows == rows)); 754403e9cbcSPhilipp Tomsich break; 755403e9cbcSPhilipp Tomsich 756403e9cbcSPhilipp Tomsich default: 757403e9cbcSPhilipp Tomsich break; 758403e9cbcSPhilipp Tomsich } 759403e9cbcSPhilipp Tomsich 760403e9cbcSPhilipp Tomsich if (match) { 761403e9cbcSPhilipp Tomsich debug("%s: setting ddrconf 0x%x\n", __func__, i); 762403e9cbcSPhilipp Tomsich writel(i, &msch->ddrconf); 763403e9cbcSPhilipp Tomsich return 0; 764403e9cbcSPhilipp Tomsich } 765403e9cbcSPhilipp Tomsich } 766403e9cbcSPhilipp Tomsich 767403e9cbcSPhilipp Tomsich error("%s: ddrconf (NIU config) not found\n", __func__); 768403e9cbcSPhilipp Tomsich return -EINVAL; 769403e9cbcSPhilipp Tomsich } 770403e9cbcSPhilipp Tomsich 771403e9cbcSPhilipp Tomsich static void dram_all_config(struct udevice *dev) 772403e9cbcSPhilipp Tomsich { 773403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev); 774403e9cbcSPhilipp Tomsich struct rk3368_pmu_grf *pmugrf = priv->pmugrf; 775403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev); 776403e9cbcSPhilipp Tomsich const struct rk3288_sdram_channel *info = ¶ms->chan; 777403e9cbcSPhilipp Tomsich u32 sys_reg = 0; 778403e9cbcSPhilipp Tomsich const int chan = 0; 779403e9cbcSPhilipp Tomsich 780403e9cbcSPhilipp Tomsich sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT; 781403e9cbcSPhilipp Tomsich sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT; 782403e9cbcSPhilipp Tomsich 783403e9cbcSPhilipp Tomsich sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); 784403e9cbcSPhilipp Tomsich sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); 785403e9cbcSPhilipp Tomsich sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); 786403e9cbcSPhilipp Tomsich sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); 787403e9cbcSPhilipp Tomsich sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); 788403e9cbcSPhilipp Tomsich sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); 789403e9cbcSPhilipp Tomsich sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); 790403e9cbcSPhilipp Tomsich sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); 791403e9cbcSPhilipp Tomsich sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); 792403e9cbcSPhilipp Tomsich 793403e9cbcSPhilipp Tomsich writel(sys_reg, &pmugrf->os_reg[2]); 794403e9cbcSPhilipp Tomsich } 795403e9cbcSPhilipp Tomsich 796403e9cbcSPhilipp Tomsich static int setup_sdram(struct udevice *dev) 797403e9cbcSPhilipp Tomsich { 798403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev); 799403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *params = dev_get_platdata(dev); 800403e9cbcSPhilipp Tomsich 801403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl = priv->pctl; 802403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy = priv->phy; 803403e9cbcSPhilipp Tomsich struct rk3368_cru *cru = priv->cru; 804403e9cbcSPhilipp Tomsich struct rk3368_grf *grf = priv->grf; 805403e9cbcSPhilipp Tomsich struct rk3368_msch *msch = priv->msch; 806403e9cbcSPhilipp Tomsich 807403e9cbcSPhilipp Tomsich int ret; 808403e9cbcSPhilipp Tomsich 809403e9cbcSPhilipp Tomsich /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ 810403e9cbcSPhilipp Tomsich ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); 811403e9cbcSPhilipp Tomsich if (ret < 0) { 812403e9cbcSPhilipp Tomsich debug("%s: could not set DDR clock: %d\n", __func__, ret); 813403e9cbcSPhilipp Tomsich return ret; 814403e9cbcSPhilipp Tomsich } 815403e9cbcSPhilipp Tomsich 816403e9cbcSPhilipp Tomsich /* Update the read-latency for the RK3368 */ 817403e9cbcSPhilipp Tomsich writel(0x32, &msch->readlatency); 818403e9cbcSPhilipp Tomsich 819403e9cbcSPhilipp Tomsich /* Initialise the DDR PCTL and DDR PHY */ 820403e9cbcSPhilipp Tomsich ddrctl_reset(cru); 821403e9cbcSPhilipp Tomsich ddrphy_reset(ddrphy); 822403e9cbcSPhilipp Tomsich ddrphy_config_delays(ddrphy, params->ddr_freq); 823403e9cbcSPhilipp Tomsich dfi_cfg(pctl); 824403e9cbcSPhilipp Tomsich /* Configure relative system information of grf_ddrc0_con0 register */ 825403e9cbcSPhilipp Tomsich ddr_set_ddr3_mode(grf, true); 826403e9cbcSPhilipp Tomsich ddr_set_noc_spr_err_stall(grf, true); 827403e9cbcSPhilipp Tomsich /* Calculate timings */ 828403e9cbcSPhilipp Tomsich pctl_calc_timings(params, params->ddr_freq); 829403e9cbcSPhilipp Tomsich /* Initialise the device timings in protocol controller */ 830403e9cbcSPhilipp Tomsich pctl_cfg(pctl, params, grf); 831403e9cbcSPhilipp Tomsich /* Configure AL, CL ... information of PHY registers */ 832403e9cbcSPhilipp Tomsich ddrphy_config(ddrphy, 833403e9cbcSPhilipp Tomsich params->pctl_timing.tcl, 834403e9cbcSPhilipp Tomsich params->pctl_timing.tal, 835403e9cbcSPhilipp Tomsich params->pctl_timing.tcwl); 836403e9cbcSPhilipp Tomsich 837403e9cbcSPhilipp Tomsich /* Initialize DRAM and configure with mode-register values */ 838403e9cbcSPhilipp Tomsich ret = memory_init(pctl, params); 839403e9cbcSPhilipp Tomsich if (ret) 840403e9cbcSPhilipp Tomsich goto error; 841403e9cbcSPhilipp Tomsich 842403e9cbcSPhilipp Tomsich move_to_config_state(pctl); 843403e9cbcSPhilipp Tomsich /* Perform data-training */ 844403e9cbcSPhilipp Tomsich ddrphy_data_training(pctl, ddrphy); 845403e9cbcSPhilipp Tomsich move_to_access_state(pctl); 846403e9cbcSPhilipp Tomsich 847403e9cbcSPhilipp Tomsich /* TODO(prt): could detect rank in training... */ 848403e9cbcSPhilipp Tomsich params->chan.rank = 2; 849403e9cbcSPhilipp Tomsich /* TODO(prt): bus width is not auto-detected (yet)... */ 850403e9cbcSPhilipp Tomsich params->chan.bw = 2; /* 32bit wide bus */ 851403e9cbcSPhilipp Tomsich params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ 852403e9cbcSPhilipp Tomsich 853403e9cbcSPhilipp Tomsich /* DDR3 is always 8 bank */ 854403e9cbcSPhilipp Tomsich params->chan.bk = 3; 855403e9cbcSPhilipp Tomsich /* Detect col and row number */ 856403e9cbcSPhilipp Tomsich ret = sdram_col_row_detect(dev); 857403e9cbcSPhilipp Tomsich if (ret) 858403e9cbcSPhilipp Tomsich goto error; 859403e9cbcSPhilipp Tomsich 860403e9cbcSPhilipp Tomsich /* Configure NIU DDR configuration */ 861403e9cbcSPhilipp Tomsich ret = msch_niu_config(msch, params); 862403e9cbcSPhilipp Tomsich if (ret) 863403e9cbcSPhilipp Tomsich goto error; 864403e9cbcSPhilipp Tomsich 865403e9cbcSPhilipp Tomsich /* set up OS_REG to communicate w/ next stage and OS */ 866403e9cbcSPhilipp Tomsich dram_all_config(dev); 867403e9cbcSPhilipp Tomsich 868403e9cbcSPhilipp Tomsich return 0; 869403e9cbcSPhilipp Tomsich 870403e9cbcSPhilipp Tomsich error: 871403e9cbcSPhilipp Tomsich printf("DRAM init failed!\n"); 872403e9cbcSPhilipp Tomsich hang(); 873403e9cbcSPhilipp Tomsich } 874403e9cbcSPhilipp Tomsich #endif 875403e9cbcSPhilipp Tomsich 876403e9cbcSPhilipp Tomsich static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev) 877403e9cbcSPhilipp Tomsich { 878403e9cbcSPhilipp Tomsich int ret = 0; 879403e9cbcSPhilipp Tomsich 880403e9cbcSPhilipp Tomsich #if !CONFIG_IS_ENABLED(OF_PLATDATA) 881403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev); 882403e9cbcSPhilipp Tomsich 883403e9cbcSPhilipp Tomsich ret = regmap_init_mem(dev, &plat->map); 884403e9cbcSPhilipp Tomsich if (ret) 885403e9cbcSPhilipp Tomsich return ret; 886403e9cbcSPhilipp Tomsich #endif 887403e9cbcSPhilipp Tomsich 888403e9cbcSPhilipp Tomsich return ret; 889403e9cbcSPhilipp Tomsich } 890403e9cbcSPhilipp Tomsich 891403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA) 892403e9cbcSPhilipp Tomsich static int conv_of_platdata(struct udevice *dev) 893403e9cbcSPhilipp Tomsich { 894403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev); 895403e9cbcSPhilipp Tomsich struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; 896403e9cbcSPhilipp Tomsich 897403e9cbcSPhilipp Tomsich plat->ddr_freq = of_plat->rockchip_ddr_frequency; 898403e9cbcSPhilipp Tomsich plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; 899403e9cbcSPhilipp Tomsich plat->memory_schedule = of_plat->rockchip_memory_schedule; 900403e9cbcSPhilipp Tomsich 901403e9cbcSPhilipp Tomsich return 0; 902403e9cbcSPhilipp Tomsich } 903403e9cbcSPhilipp Tomsich #endif 904403e9cbcSPhilipp Tomsich 905403e9cbcSPhilipp Tomsich static int rk3368_dmc_probe(struct udevice *dev) 906403e9cbcSPhilipp Tomsich { 907403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD 908403e9cbcSPhilipp Tomsich struct rk3368_sdram_params *plat = dev_get_platdata(dev); 909403e9cbcSPhilipp Tomsich struct rk3368_ddr_pctl *pctl; 910403e9cbcSPhilipp Tomsich struct rk3368_ddrphy *ddrphy; 911403e9cbcSPhilipp Tomsich struct rk3368_cru *cru; 912403e9cbcSPhilipp Tomsich struct rk3368_grf *grf; 913403e9cbcSPhilipp Tomsich struct rk3368_msch *msch; 914403e9cbcSPhilipp Tomsich int ret; 915403e9cbcSPhilipp Tomsich struct udevice *dev_clk; 916403e9cbcSPhilipp Tomsich #endif 917403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev); 918403e9cbcSPhilipp Tomsich 919403e9cbcSPhilipp Tomsich #if CONFIG_IS_ENABLED(OF_PLATDATA) 920403e9cbcSPhilipp Tomsich ret = conv_of_platdata(dev); 921403e9cbcSPhilipp Tomsich if (ret) 922403e9cbcSPhilipp Tomsich return ret; 923403e9cbcSPhilipp Tomsich #endif 924403e9cbcSPhilipp Tomsich 925403e9cbcSPhilipp Tomsich priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 926403e9cbcSPhilipp Tomsich debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); 927403e9cbcSPhilipp Tomsich 928403e9cbcSPhilipp Tomsich #ifdef CONFIG_TPL_BUILD 929*1d70f0acSPhilipp Tomsich pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0]; 930*1d70f0acSPhilipp Tomsich ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2]; 931403e9cbcSPhilipp Tomsich msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); 932403e9cbcSPhilipp Tomsich grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 933403e9cbcSPhilipp Tomsich 934403e9cbcSPhilipp Tomsich priv->pctl = pctl; 935403e9cbcSPhilipp Tomsich priv->phy = ddrphy; 936403e9cbcSPhilipp Tomsich priv->msch = msch; 937403e9cbcSPhilipp Tomsich priv->grf = grf; 938403e9cbcSPhilipp Tomsich 939403e9cbcSPhilipp Tomsich ret = rockchip_get_clk(&dev_clk); 940403e9cbcSPhilipp Tomsich if (ret) 941403e9cbcSPhilipp Tomsich return ret; 942403e9cbcSPhilipp Tomsich priv->ddr_clk.id = CLK_DDR; 943403e9cbcSPhilipp Tomsich ret = clk_request(dev_clk, &priv->ddr_clk); 944403e9cbcSPhilipp Tomsich if (ret) 945403e9cbcSPhilipp Tomsich return ret; 946403e9cbcSPhilipp Tomsich 947403e9cbcSPhilipp Tomsich cru = rockchip_get_cru(); 948403e9cbcSPhilipp Tomsich priv->cru = cru; 949403e9cbcSPhilipp Tomsich if (IS_ERR(priv->cru)) 950403e9cbcSPhilipp Tomsich return PTR_ERR(priv->cru); 951403e9cbcSPhilipp Tomsich 952403e9cbcSPhilipp Tomsich ret = setup_sdram(dev); 953403e9cbcSPhilipp Tomsich if (ret) 954403e9cbcSPhilipp Tomsich return ret; 955403e9cbcSPhilipp Tomsich #endif 956403e9cbcSPhilipp Tomsich 957403e9cbcSPhilipp Tomsich priv->info.base = 0; 958403e9cbcSPhilipp Tomsich priv->info.size = 959403e9cbcSPhilipp Tomsich rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); 960403e9cbcSPhilipp Tomsich 961403e9cbcSPhilipp Tomsich /* 962403e9cbcSPhilipp Tomsich * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff 963403e9cbcSPhilipp Tomsich * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is 964403e9cbcSPhilipp Tomsich * inaccessible for some IP controller. 965403e9cbcSPhilipp Tomsich */ 966403e9cbcSPhilipp Tomsich priv->info.size = min(priv->info.size, (size_t)0xfe000000); 967403e9cbcSPhilipp Tomsich 968403e9cbcSPhilipp Tomsich return 0; 969403e9cbcSPhilipp Tomsich } 970403e9cbcSPhilipp Tomsich 971403e9cbcSPhilipp Tomsich static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) 972403e9cbcSPhilipp Tomsich { 973403e9cbcSPhilipp Tomsich struct dram_info *priv = dev_get_priv(dev); 974403e9cbcSPhilipp Tomsich 975403e9cbcSPhilipp Tomsich *info = priv->info; 976403e9cbcSPhilipp Tomsich return 0; 977403e9cbcSPhilipp Tomsich } 978403e9cbcSPhilipp Tomsich 979403e9cbcSPhilipp Tomsich static struct ram_ops rk3368_dmc_ops = { 980403e9cbcSPhilipp Tomsich .get_info = rk3368_dmc_get_info, 981403e9cbcSPhilipp Tomsich }; 982403e9cbcSPhilipp Tomsich 983403e9cbcSPhilipp Tomsich 984403e9cbcSPhilipp Tomsich static const struct udevice_id rk3368_dmc_ids[] = { 985403e9cbcSPhilipp Tomsich { .compatible = "rockchip,rk3368-dmc" }, 986403e9cbcSPhilipp Tomsich { } 987403e9cbcSPhilipp Tomsich }; 988403e9cbcSPhilipp Tomsich 989403e9cbcSPhilipp Tomsich U_BOOT_DRIVER(dmc_rk3368) = { 990403e9cbcSPhilipp Tomsich .name = "rockchip_rk3368_dmc", 991403e9cbcSPhilipp Tomsich .id = UCLASS_RAM, 992403e9cbcSPhilipp Tomsich .of_match = rk3368_dmc_ids, 993403e9cbcSPhilipp Tomsich .ops = &rk3368_dmc_ops, 994403e9cbcSPhilipp Tomsich .probe = rk3368_dmc_probe, 995403e9cbcSPhilipp Tomsich .priv_auto_alloc_size = sizeof(struct dram_info), 996403e9cbcSPhilipp Tomsich .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata, 997403e9cbcSPhilipp Tomsich .probe = rk3368_dmc_probe, 998403e9cbcSPhilipp Tomsich .priv_auto_alloc_size = sizeof(struct dram_info), 999403e9cbcSPhilipp Tomsich .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params), 1000403e9cbcSPhilipp Tomsich }; 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