1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2018 4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <ram.h> 10 #include <dt-bindings/memory/mpc83xx-sdram.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 /* Masks for the CS config register */ 15 static const u32 CSCONFIG_ENABLE = 0x80000000; 16 17 static const u32 BANK_BITS_2; 18 static const u32 BANK_BITS_3 = 0x00004000; 19 20 static const u32 ROW_BITS_12; 21 static const u32 ROW_BITS_13 = 0x00000100; 22 static const u32 ROW_BITS_14 = 0x00000200; 23 24 static const u32 COL_BITS_8; 25 static const u32 COL_BITS_9 = 0x00000001; 26 static const u32 COL_BITS_10 = 0x00000002; 27 static const u32 COL_BITS_11 = 0x00000003; 28 29 /* Shifts for the DDR SDRAM Timing Configuration 3 register */ 30 static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15); 31 32 /* Shifts for the DDR SDRAM Timing Configuration 0 register */ 33 static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1); 34 static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3); 35 static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5); 36 static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7); 37 static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11); 38 static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15); 39 static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23); 40 static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31); 41 42 /* Shifts for the DDR SDRAM Timing Configuration 1 register */ 43 static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3); 44 static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7); 45 static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11); 46 static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15); 47 static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19); 48 static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23); 49 static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27); 50 static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31); 51 52 /* Shifts for the DDR SDRAM Timing Configuration 2 register */ 53 static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8); 54 static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21); 55 static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3); 56 static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12); 57 static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18); 58 static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25); 59 static const uint TIMING_CFG2_FOUR_ACT_SHIFT; 60 61 /* Shifts for the DDR SDRAM Control Configuration register */ 62 static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1); 63 static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2); 64 static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3); 65 static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7); 66 static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10); 67 static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12); 68 static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14); 69 static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16); 70 static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23); 71 static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27); 72 static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28); 73 static const uint SDRAM_CFG_BI_SHIFT = (31 - 31); 74 75 /* Shifts for the DDR SDRAM Control Configuration 2 register */ 76 static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0); 77 static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2); 78 static const uint SDRAM_CFG2_DQS_CFG = (31 - 5); 79 static const uint SDRAM_CFG2_ODT_CFG = (31 - 10); 80 static const uint SDRAM_CFG2_NUM_PR = (31 - 19); 81 82 /* Shifts for the DDR SDRAM Mode register */ 83 static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15); 84 static const uint SDRAM_MODE_SD_SHIFT = (31 - 31); 85 86 /* Shifts for the DDR SDRAM Mode 2 register */ 87 static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15); 88 static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31); 89 90 /* Shifts for the DDR SDRAM Interval Configuration register */ 91 static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15); 92 static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31); 93 94 /* Mask for the DDR SDRAM Mode Control register */ 95 static const u32 SDRAM_CFG_MEM_EN = 0x80000000; 96 97 int dram_init(void) 98 { 99 struct udevice *ram_ctrl; 100 int ret; 101 102 /* Current assumption: There is only one RAM controller */ 103 ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl); 104 if (ret) { 105 debug("%s: uclass_first_device_err failed: %d\n", 106 __func__, ret); 107 return ret; 108 } 109 110 /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */ 111 112 return 0; 113 } 114 115 phys_size_t get_effective_memsize(void) 116 { 117 if (!IS_ENABLED(CONFIG_VERY_BIG_RAM)) 118 return gd->ram_size; 119 120 /* Limit stack to what we can reasonable map */ 121 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? 122 CONFIG_MAX_MEM_MAPPED : gd->ram_size); 123 } 124 125 /** 126 * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers 127 * @total_size: The total size of all RAM modules associated with this RAM 128 * controller in bytes 129 */ 130 struct mpc83xx_sdram_priv { 131 ulong total_size; 132 }; 133 134 /** 135 * mpc83xx_sdram_static_init() - Statically initialize a RAM module. 136 * @node: Device tree node associated with ths module in question 137 * @cs: The chip select to use for this RAM module 138 * @mapaddr: The address where the RAM module should be mapped 139 * @size: The size of the RAM module to be mapped in bytes 140 * 141 * Return: 0 if OK, -ve on error 142 */ 143 static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) 144 { 145 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 146 u32 msize = size; 147 u32 msize_log2 = __ilog2(msize); 148 u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits, 149 col_bits; 150 u32 bank_bits_mask, row_bits_mask, col_bits_mask; 151 152 /* Configure the DDR local access window */ 153 out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000); 154 out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1)); 155 156 out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24); 157 158 auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0); 159 switch (auto_precharge) { 160 case AUTO_PRECHARGE_ENABLE: 161 case AUTO_PRECHARGE_DISABLE: 162 break; 163 default: 164 debug("%s: auto_precharge value %d invalid.\n", 165 ofnode_get_name(node), auto_precharge); 166 return -EINVAL; 167 } 168 169 odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); 170 switch (odt_rd_cfg) { 171 case ODT_RD_ONLY_OTHER_DIMM: 172 if (!IS_ENABLED(CONFIG_MPC8360) && 173 !IS_ENABLED(CONFIG_MPC837x)) { 174 debug("%s: odt_rd_cfg value %d invalid.\n", 175 ofnode_get_name(node), odt_rd_cfg); 176 return -EINVAL; 177 } 178 /* fall through */ 179 case ODT_RD_NEVER: 180 case ODT_RD_ONLY_CURRENT: 181 case ODT_RD_ONLY_OTHER_CS: 182 if (!IS_ENABLED(CONFIG_MPC830x) && 183 !IS_ENABLED(CONFIG_MPC831x) && 184 !IS_ENABLED(CONFIG_MPC8360) && 185 !IS_ENABLED(CONFIG_MPC837x)) { 186 debug("%s: odt_rd_cfg value %d invalid.\n", 187 ofnode_get_name(node), odt_rd_cfg); 188 return -EINVAL; 189 } 190 /* fall through */ 191 /* Only MPC832x knows this value */ 192 case ODT_RD_ALL: 193 break; 194 default: 195 debug("%s: odt_rd_cfg value %d invalid.\n", 196 ofnode_get_name(node), odt_rd_cfg); 197 return -EINVAL; 198 } 199 200 odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); 201 switch (odt_wr_cfg) { 202 case ODT_WR_ONLY_OTHER_DIMM: 203 if (!IS_ENABLED(CONFIG_MPC8360) && 204 !IS_ENABLED(CONFIG_MPC837x)) { 205 debug("%s: odt_wr_cfg value %d invalid.\n", 206 ofnode_get_name(node), odt_wr_cfg); 207 return -EINVAL; 208 } 209 /* fall through */ 210 case ODT_WR_NEVER: 211 case ODT_WR_ONLY_CURRENT: 212 case ODT_WR_ONLY_OTHER_CS: 213 if (!IS_ENABLED(CONFIG_MPC830x) && 214 !IS_ENABLED(CONFIG_MPC831x) && 215 !IS_ENABLED(CONFIG_MPC8360) && 216 !IS_ENABLED(CONFIG_MPC837x)) { 217 debug("%s: odt_wr_cfg value %d invalid.\n", 218 ofnode_get_name(node), odt_wr_cfg); 219 return -EINVAL; 220 } 221 /* fall through */ 222 /* MPC832x only knows this value */ 223 case ODT_WR_ALL: 224 break; 225 default: 226 debug("%s: odt_wr_cfg value %d invalid.\n", 227 ofnode_get_name(node), odt_wr_cfg); 228 return -EINVAL; 229 } 230 231 bank_bits = ofnode_read_u32_default(node, "bank_bits", 0); 232 switch (bank_bits) { 233 case 2: 234 bank_bits_mask = BANK_BITS_2; 235 break; 236 case 3: 237 bank_bits_mask = BANK_BITS_3; 238 break; 239 default: 240 debug("%s: bank_bits value %d invalid.\n", 241 ofnode_get_name(node), bank_bits); 242 return -EINVAL; 243 } 244 245 row_bits = ofnode_read_u32_default(node, "row_bits", 0); 246 switch (row_bits) { 247 case 12: 248 row_bits_mask = ROW_BITS_12; 249 break; 250 case 13: 251 row_bits_mask = ROW_BITS_13; 252 break; 253 case 14: 254 row_bits_mask = ROW_BITS_14; 255 break; 256 default: 257 debug("%s: row_bits value %d invalid.\n", 258 ofnode_get_name(node), row_bits); 259 return -EINVAL; 260 } 261 262 col_bits = ofnode_read_u32_default(node, "col_bits", 0); 263 switch (col_bits) { 264 case 8: 265 col_bits_mask = COL_BITS_8; 266 break; 267 case 9: 268 col_bits_mask = COL_BITS_9; 269 break; 270 case 10: 271 col_bits_mask = COL_BITS_10; 272 break; 273 case 11: 274 col_bits_mask = COL_BITS_11; 275 break; 276 default: 277 debug("%s: col_bits value %d invalid.\n", 278 ofnode_get_name(node), col_bits); 279 return -EINVAL; 280 } 281 282 /* Write CS config value */ 283 out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge | 284 odt_rd_cfg | odt_wr_cfg | 285 bank_bits_mask | row_bits_mask | 286 col_bits_mask); 287 return 0; 288 } 289 290 /** 291 * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash. 292 * @node: Device tree node associated with ths module in question 293 * @cs: The chip select to use for this RAM module 294 * @mapaddr: The address where the RAM module should be mapped 295 * @size: The size of the RAM module to be mapped in bytes 296 * 297 * Return: 0 if OK, -ve on error 298 */ 299 static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size) 300 { 301 /* TODO(mario.six@gdsys.cc): Implement */ 302 return 0; 303 } 304 305 static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev) 306 { 307 return 0; 308 } 309 310 static int mpc83xx_sdram_probe(struct udevice *dev) 311 { 312 struct mpc83xx_sdram_priv *priv = dev_get_priv(dev); 313 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 314 int ret = 0; 315 ofnode subnode; 316 /* DDR control driver register values */ 317 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; 318 u32 ddrcdr; 319 /* DDR SDRAM Clock Control register values */ 320 u32 clock_adjust; 321 /* DDR SDRAM Timing Configuration 3 register values */ 322 u32 ext_refresh_rec, ext_refresh_rec_mask; 323 /* DDR SDRAM Timing Configuration 0 register values */ 324 u32 read_to_write, write_to_read, read_to_read, write_to_write, 325 active_powerdown_exit, precharge_powerdown_exit, 326 odt_powerdown_exit, mode_reg_set_cycle; 327 u32 timing_cfg_0; 328 /* DDR SDRAM Timing Configuration 1 register values */ 329 u32 precharge_to_activate, activate_to_precharge, 330 activate_to_readwrite, mcas_latency, refresh_recovery, 331 last_data_to_precharge, activate_to_activate, 332 last_write_data_to_read; 333 u32 timing_cfg_1; 334 /* DDR SDRAM Timing Configuration 2 register values */ 335 u32 additive_latency, mcas_to_preamble_override, write_latency, 336 read_to_precharge, write_cmd_to_write_data, 337 minimum_cke_pulse_width, four_activates_window; 338 u32 timing_cfg_2; 339 /* DDR SDRAM Control Configuration register values */ 340 u32 self_refresh, ecc, registered_dram, sdram_type, 341 dynamic_power_management, databus_width, nc_auto_precharge, 342 timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength, 343 bypass_initialization; 344 u32 sdram_cfg; 345 /* DDR SDRAM Control Configuration 2 register values */ 346 u32 force_self_refresh, dll_reset, dqs_config, odt_config, 347 posted_refreshes; 348 u32 sdram_cfg2; 349 /* DDR SDRAM Mode Configuration register values */ 350 u32 sdmode, esdmode; 351 u32 sdram_mode; 352 /* DDR SDRAM Mode Configuration 2 register values */ 353 u32 esdmode2, esdmode3; 354 u32 sdram_mode2; 355 /* DDR SDRAM Interval Configuration register values */ 356 u32 refresh_interval, precharge_interval; 357 u32 sdram_interval; 358 359 priv->total_size = 0; 360 361 /* Disable both banks initially (might be re-enabled in loop below) */ 362 out_be32(&im->ddr.cs_config[0], 0); 363 out_be32(&im->ddr.cs_config[1], 0); 364 365 dso = dev_read_u32_default(dev, "driver_software_override", 0); 366 if (dso > 1) { 367 debug("%s: driver_software_override value %d invalid.\n", 368 dev->name, dso); 369 return -EINVAL; 370 } 371 372 pz_override = dev_read_u32_default(dev, "p_impedance_override", 0); 373 374 switch (pz_override) { 375 case DSO_P_IMPEDANCE_HIGHEST_Z: 376 case DSO_P_IMPEDANCE_MUCH_HIGHER_Z: 377 case DSO_P_IMPEDANCE_HIGHER_Z: 378 case DSO_P_IMPEDANCE_NOMINAL: 379 case DSO_P_IMPEDANCE_LOWER_Z: 380 break; 381 default: 382 debug("%s: p_impedance_override value %d invalid.\n", 383 dev->name, pz_override); 384 return -EINVAL; 385 } 386 387 nz_override = dev_read_u32_default(dev, "n_impedance_override", 0); 388 389 switch (nz_override) { 390 case DSO_N_IMPEDANCE_HIGHEST_Z: 391 case DSO_N_IMPEDANCE_MUCH_HIGHER_Z: 392 case DSO_N_IMPEDANCE_HIGHER_Z: 393 case DSO_N_IMPEDANCE_NOMINAL: 394 case DSO_N_IMPEDANCE_LOWER_Z: 395 break; 396 default: 397 debug("%s: n_impedance_override value %d invalid.\n", 398 dev->name, nz_override); 399 return -EINVAL; 400 } 401 402 odt_term = dev_read_u32_default(dev, "odt_termination_value", 0); 403 if (odt_term > 1) { 404 debug("%s: odt_termination_value value %d invalid.\n", 405 dev->name, odt_term); 406 return -EINVAL; 407 } 408 409 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); 410 if (ddr_type > 1) { 411 debug("%s: ddr_type value %d invalid.\n", 412 dev->name, ddr_type); 413 return -EINVAL; 414 } 415 416 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); 417 if (mvref_sel > 1) { 418 debug("%s: mvref_sel value %d invalid.\n", 419 dev->name, mvref_sel); 420 return -EINVAL; 421 } 422 423 m_odr = dev_read_u32_default(dev, "m_odr", 0); 424 if (mvref_sel > 1) { 425 debug("%s: m_odr value %d invalid.\n", 426 dev->name, m_odr); 427 return -EINVAL; 428 } 429 430 ddrcdr = dso << (31 - 1) | 431 pz_override << (31 - 5) | 432 nz_override << (31 - 9) | 433 odt_term << (31 - 12) | 434 ddr_type << (31 - 13) | 435 mvref_sel << (31 - 29) | 436 m_odr << (31 - 30) | 1; 437 438 /* Configure the DDR control driver register */ 439 out_be32(&im->sysconf.ddrcdr, ddrcdr); 440 441 dev_for_each_subnode(subnode, dev) { 442 u32 val[3]; 443 u32 cs, addr, size; 444 445 /* CS, map address, size -> three values */ 446 ofnode_read_u32_array(subnode, "reg", val, 3); 447 448 cs = val[0]; 449 addr = val[1]; 450 size = val[2]; 451 452 if (cs > 1) { 453 debug("%s: chip select value %d invalid.\n", 454 dev->name, cs); 455 return -EINVAL; 456 } 457 458 /* TODO(mario.six@gdsys.cc): Sanity check for size. */ 459 460 if (ofnode_read_bool(subnode, "read-spd")) 461 ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size); 462 else 463 ret = mpc83xx_sdram_static_init(subnode, cs, addr, 464 size); 465 if (ret) { 466 debug("%s: RAM init failed.\n", dev->name); 467 return ret; 468 } 469 }; 470 471 /* 472 * TODO(mario.six@gdsys.cc): This should only occur for static 473 * configuration 474 */ 475 476 clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0); 477 switch (clock_adjust) { 478 case CLOCK_ADJUST_025: 479 case CLOCK_ADJUST_05: 480 case CLOCK_ADJUST_075: 481 case CLOCK_ADJUST_1: 482 break; 483 default: 484 debug("%s: clock_adjust value %d invalid.\n", 485 dev->name, clock_adjust); 486 return -EINVAL; 487 } 488 489 /* Configure the DDR SDRAM Clock Control register */ 490 out_be32(&im->ddr.sdram_clk_cntl, clock_adjust); 491 492 ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0); 493 switch (ext_refresh_rec) { 494 case 0: 495 ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT; 496 break; 497 case 16: 498 ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT; 499 break; 500 case 32: 501 ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT; 502 break; 503 case 48: 504 ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT; 505 break; 506 case 64: 507 ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT; 508 break; 509 case 80: 510 ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT; 511 break; 512 case 96: 513 ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT; 514 break; 515 case 112: 516 ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT; 517 break; 518 default: 519 debug("%s: ext_refresh_rec value %d invalid.\n", 520 dev->name, ext_refresh_rec); 521 return -EINVAL; 522 } 523 524 /* Configure the DDR SDRAM Timing Configuration 3 register */ 525 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask); 526 527 read_to_write = dev_read_u32_default(dev, "read_to_write", 0); 528 if (read_to_write > 3) { 529 debug("%s: read_to_write value %d invalid.\n", 530 dev->name, read_to_write); 531 return -EINVAL; 532 } 533 534 write_to_read = dev_read_u32_default(dev, "write_to_read", 0); 535 if (write_to_read > 3) { 536 debug("%s: write_to_read value %d invalid.\n", 537 dev->name, write_to_read); 538 return -EINVAL; 539 } 540 541 read_to_read = dev_read_u32_default(dev, "read_to_read", 0); 542 if (read_to_read > 3) { 543 debug("%s: read_to_read value %d invalid.\n", 544 dev->name, read_to_read); 545 return -EINVAL; 546 } 547 548 write_to_write = dev_read_u32_default(dev, "write_to_write", 0); 549 if (write_to_write > 3) { 550 debug("%s: write_to_write value %d invalid.\n", 551 dev->name, write_to_write); 552 return -EINVAL; 553 } 554 555 active_powerdown_exit = 556 dev_read_u32_default(dev, "active_powerdown_exit", 0); 557 if (active_powerdown_exit > 7) { 558 debug("%s: active_powerdown_exit value %d invalid.\n", 559 dev->name, active_powerdown_exit); 560 return -EINVAL; 561 } 562 563 precharge_powerdown_exit = 564 dev_read_u32_default(dev, "precharge_powerdown_exit", 0); 565 if (precharge_powerdown_exit > 7) { 566 debug("%s: precharge_powerdown_exit value %d invalid.\n", 567 dev->name, precharge_powerdown_exit); 568 return -EINVAL; 569 } 570 571 odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0); 572 if (odt_powerdown_exit > 15) { 573 debug("%s: odt_powerdown_exit value %d invalid.\n", 574 dev->name, odt_powerdown_exit); 575 return -EINVAL; 576 } 577 578 mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0); 579 if (mode_reg_set_cycle > 15) { 580 debug("%s: mode_reg_set_cycle value %d invalid.\n", 581 dev->name, mode_reg_set_cycle); 582 return -EINVAL; 583 } 584 585 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | 586 write_to_read << TIMING_CFG0_WRT_SHIFT | 587 read_to_read << TIMING_CFG0_RRT_SHIFT | 588 write_to_write << TIMING_CFG0_WWT_SHIFT | 589 active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT | 590 precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT | 591 odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT | 592 mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT; 593 594 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); 595 596 precharge_to_activate = 597 dev_read_u32_default(dev, "precharge_to_activate", 0); 598 if (precharge_to_activate > 7 || precharge_to_activate == 0) { 599 debug("%s: precharge_to_activate value %d invalid.\n", 600 dev->name, precharge_to_activate); 601 return -EINVAL; 602 } 603 604 activate_to_precharge = 605 dev_read_u32_default(dev, "activate_to_precharge", 0); 606 if (activate_to_precharge > 19) { 607 debug("%s: activate_to_precharge value %d invalid.\n", 608 dev->name, activate_to_precharge); 609 return -EINVAL; 610 } 611 612 activate_to_readwrite = 613 dev_read_u32_default(dev, "activate_to_readwrite", 0); 614 if (activate_to_readwrite > 7 || activate_to_readwrite == 0) { 615 debug("%s: activate_to_readwrite value %d invalid.\n", 616 dev->name, activate_to_readwrite); 617 return -EINVAL; 618 } 619 620 mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0); 621 switch (mcas_latency) { 622 case CASLAT_20: 623 case CASLAT_25: 624 if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) { 625 debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n", 626 dev->name); 627 return -EINVAL; 628 } 629 /* fall through */ 630 case CASLAT_30: 631 case CASLAT_35: 632 case CASLAT_40: 633 case CASLAT_45: 634 case CASLAT_50: 635 case CASLAT_55: 636 case CASLAT_60: 637 case CASLAT_65: 638 case CASLAT_70: 639 case CASLAT_75: 640 case CASLAT_80: 641 break; 642 default: 643 debug("%s: mcas_latency value %d invalid.\n", 644 dev->name, mcas_latency); 645 return -EINVAL; 646 } 647 648 refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0); 649 if (refresh_recovery > 23 || refresh_recovery < 8) { 650 debug("%s: refresh_recovery value %d invalid.\n", 651 dev->name, refresh_recovery); 652 return -EINVAL; 653 } 654 655 last_data_to_precharge = 656 dev_read_u32_default(dev, "last_data_to_precharge", 0); 657 if (last_data_to_precharge > 7 || last_data_to_precharge == 0) { 658 debug("%s: last_data_to_precharge value %d invalid.\n", 659 dev->name, last_data_to_precharge); 660 return -EINVAL; 661 } 662 663 activate_to_activate = 664 dev_read_u32_default(dev, "activate_to_activate", 0); 665 if (activate_to_activate > 7 || activate_to_activate == 0) { 666 debug("%s: activate_to_activate value %d invalid.\n", 667 dev->name, activate_to_activate); 668 return -EINVAL; 669 } 670 671 last_write_data_to_read = 672 dev_read_u32_default(dev, "last_write_data_to_read", 0); 673 if (last_write_data_to_read > 7 || last_write_data_to_read == 0) { 674 debug("%s: last_write_data_to_read value %d invalid.\n", 675 dev->name, last_write_data_to_read); 676 return -EINVAL; 677 } 678 679 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | 680 (activate_to_precharge > 15 ? 681 activate_to_precharge - 16 : 682 activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT | 683 activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT | 684 mcas_latency << TIMING_CFG1_CASLAT_SHIFT | 685 (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT | 686 last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT | 687 activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT | 688 last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT; 689 690 /* Configure the DDR SDRAM Timing Configuration 1 register */ 691 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1); 692 693 additive_latency = dev_read_u32_default(dev, "additive_latency", 0); 694 if (additive_latency > 5) { 695 debug("%s: additive_latency value %d invalid.\n", 696 dev->name, additive_latency); 697 return -EINVAL; 698 } 699 700 mcas_to_preamble_override = 701 dev_read_u32_default(dev, "mcas_to_preamble_override", 0); 702 switch (mcas_to_preamble_override) { 703 case READ_LAT_PLUS_1: 704 case READ_LAT: 705 case READ_LAT_PLUS_1_4: 706 case READ_LAT_PLUS_1_2: 707 case READ_LAT_PLUS_3_4: 708 case READ_LAT_PLUS_5_4: 709 case READ_LAT_PLUS_3_2: 710 case READ_LAT_PLUS_7_4: 711 case READ_LAT_PLUS_2: 712 case READ_LAT_PLUS_9_4: 713 case READ_LAT_PLUS_5_2: 714 case READ_LAT_PLUS_11_4: 715 case READ_LAT_PLUS_3: 716 case READ_LAT_PLUS_13_4: 717 case READ_LAT_PLUS_7_2: 718 case READ_LAT_PLUS_15_4: 719 case READ_LAT_PLUS_4: 720 case READ_LAT_PLUS_17_4: 721 case READ_LAT_PLUS_9_2: 722 case READ_LAT_PLUS_19_4: 723 break; 724 default: 725 debug("%s: mcas_to_preamble_override value %d invalid.\n", 726 dev->name, mcas_to_preamble_override); 727 return -EINVAL; 728 } 729 730 write_latency = dev_read_u32_default(dev, "write_latency", 0); 731 if (write_latency > 7 || write_latency == 0) { 732 debug("%s: write_latency value %d invalid.\n", 733 dev->name, write_latency); 734 return -EINVAL; 735 } 736 737 read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0); 738 if (read_to_precharge > 4 || read_to_precharge == 0) { 739 debug("%s: read_to_precharge value %d invalid.\n", 740 dev->name, read_to_precharge); 741 return -EINVAL; 742 } 743 744 write_cmd_to_write_data = 745 dev_read_u32_default(dev, "write_cmd_to_write_data", 0); 746 switch (write_cmd_to_write_data) { 747 case CLOCK_DELAY_0: 748 case CLOCK_DELAY_1_4: 749 case CLOCK_DELAY_1_2: 750 case CLOCK_DELAY_3_4: 751 case CLOCK_DELAY_1: 752 case CLOCK_DELAY_5_4: 753 case CLOCK_DELAY_3_2: 754 break; 755 default: 756 debug("%s: write_cmd_to_write_data value %d invalid.\n", 757 dev->name, write_cmd_to_write_data); 758 return -EINVAL; 759 } 760 761 minimum_cke_pulse_width = 762 dev_read_u32_default(dev, "minimum_cke_pulse_width", 0); 763 if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) { 764 debug("%s: minimum_cke_pulse_width value %d invalid.\n", 765 dev->name, minimum_cke_pulse_width); 766 return -EINVAL; 767 } 768 769 four_activates_window = 770 dev_read_u32_default(dev, "four_activates_window", 0); 771 if (four_activates_window > 20 || four_activates_window == 0) { 772 debug("%s: four_activates_window value %d invalid.\n", 773 dev->name, four_activates_window); 774 return -EINVAL; 775 } 776 777 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | 778 mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT | 779 write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT | 780 read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT | 781 write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT | 782 minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT | 783 four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT; 784 785 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); 786 787 self_refresh = dev_read_u32_default(dev, "self_refresh", 0); 788 switch (self_refresh) { 789 case SREN_DISABLE: 790 case SREN_ENABLE: 791 break; 792 default: 793 debug("%s: self_refresh value %d invalid.\n", 794 dev->name, self_refresh); 795 return -EINVAL; 796 } 797 798 ecc = dev_read_u32_default(dev, "ecc", 0); 799 switch (ecc) { 800 case ECC_DISABLE: 801 case ECC_ENABLE: 802 break; 803 default: 804 debug("%s: ecc value %d invalid.\n", dev->name, ecc); 805 return -EINVAL; 806 } 807 808 registered_dram = dev_read_u32_default(dev, "registered_dram", 0); 809 switch (registered_dram) { 810 case RD_DISABLE: 811 case RD_ENABLE: 812 break; 813 default: 814 debug("%s: registered_dram value %d invalid.\n", 815 dev->name, registered_dram); 816 return -EINVAL; 817 } 818 819 sdram_type = dev_read_u32_default(dev, "sdram_type", 0); 820 switch (sdram_type) { 821 case TYPE_DDR1: 822 case TYPE_DDR2: 823 break; 824 default: 825 debug("%s: sdram_type value %d invalid.\n", 826 dev->name, sdram_type); 827 return -EINVAL; 828 } 829 830 dynamic_power_management = 831 dev_read_u32_default(dev, "dynamic_power_management", 0); 832 switch (dynamic_power_management) { 833 case DYN_PWR_DISABLE: 834 case DYN_PWR_ENABLE: 835 break; 836 default: 837 debug("%s: dynamic_power_management value %d invalid.\n", 838 dev->name, dynamic_power_management); 839 return -EINVAL; 840 } 841 842 databus_width = dev_read_u32_default(dev, "databus_width", 0); 843 switch (databus_width) { 844 case DATA_BUS_WIDTH_16: 845 case DATA_BUS_WIDTH_32: 846 break; 847 default: 848 debug("%s: databus_width value %d invalid.\n", 849 dev->name, databus_width); 850 return -EINVAL; 851 } 852 853 nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0); 854 switch (nc_auto_precharge) { 855 case NCAP_DISABLE: 856 case NCAP_ENABLE: 857 break; 858 default: 859 debug("%s: nc_auto_precharge value %d invalid.\n", 860 dev->name, nc_auto_precharge); 861 return -EINVAL; 862 } 863 864 timing_2t = dev_read_u32_default(dev, "timing_2t", 0); 865 switch (timing_2t) { 866 case TIMING_1T: 867 case TIMING_2T: 868 break; 869 default: 870 debug("%s: timing_2t value %d invalid.\n", 871 dev->name, timing_2t); 872 return -EINVAL; 873 } 874 875 bank_interleaving_ctrl = 876 dev_read_u32_default(dev, "bank_interleaving_ctrl", 0); 877 switch (bank_interleaving_ctrl) { 878 case INTERLEAVE_NONE: 879 case INTERLEAVE_1_AND_2: 880 break; 881 default: 882 debug("%s: bank_interleaving_ctrl value %d invalid.\n", 883 dev->name, bank_interleaving_ctrl); 884 return -EINVAL; 885 } 886 887 precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0); 888 switch (precharge_bit_8) { 889 case PRECHARGE_MA_10: 890 case PRECHARGE_MA_8: 891 break; 892 default: 893 debug("%s: precharge_bit_8 value %d invalid.\n", 894 dev->name, precharge_bit_8); 895 return -EINVAL; 896 } 897 898 half_strength = dev_read_u32_default(dev, "half_strength", 0); 899 switch (half_strength) { 900 case STRENGTH_FULL: 901 case STRENGTH_HALF: 902 break; 903 default: 904 debug("%s: half_strength value %d invalid.\n", 905 dev->name, half_strength); 906 return -EINVAL; 907 } 908 909 bypass_initialization = 910 dev_read_u32_default(dev, "bypass_initialization", 0); 911 switch (bypass_initialization) { 912 case INITIALIZATION_DONT_BYPASS: 913 case INITIALIZATION_BYPASS: 914 break; 915 default: 916 debug("%s: bypass_initialization value %d invalid.\n", 917 dev->name, bypass_initialization); 918 return -EINVAL; 919 } 920 921 sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT | 922 ecc << SDRAM_CFG_ECC_EN_SHIFT | 923 registered_dram << SDRAM_CFG_RD_EN_SHIFT | 924 sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT | 925 dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT | 926 databus_width << SDRAM_CFG_DBW_SHIFT | 927 nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT | 928 timing_2t << SDRAM_CFG_2T_EN_SHIFT | 929 bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT | 930 precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT | 931 half_strength << SDRAM_CFG_HSE_SHIFT | 932 bypass_initialization << SDRAM_CFG_BI_SHIFT; 933 934 out_be32(&im->ddr.sdram_cfg, sdram_cfg); 935 936 force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0); 937 switch (force_self_refresh) { 938 case MODE_NORMAL: 939 case MODE_REFRESH: 940 break; 941 default: 942 debug("%s: force_self_refresh value %d invalid.\n", 943 dev->name, force_self_refresh); 944 return -EINVAL; 945 } 946 947 dll_reset = dev_read_u32_default(dev, "dll_reset", 0); 948 switch (dll_reset) { 949 case DLL_RESET_ENABLE: 950 case DLL_RESET_DISABLE: 951 break; 952 default: 953 debug("%s: dll_reset value %d invalid.\n", 954 dev->name, dll_reset); 955 return -EINVAL; 956 } 957 958 dqs_config = dev_read_u32_default(dev, "dqs_config", 0); 959 switch (dqs_config) { 960 case DQS_TRUE: 961 break; 962 default: 963 debug("%s: dqs_config value %d invalid.\n", 964 dev->name, dqs_config); 965 return -EINVAL; 966 } 967 968 odt_config = dev_read_u32_default(dev, "odt_config", 0); 969 switch (odt_config) { 970 case ODT_ASSERT_NEVER: 971 case ODT_ASSERT_WRITES: 972 case ODT_ASSERT_READS: 973 case ODT_ASSERT_ALWAYS: 974 break; 975 default: 976 debug("%s: odt_config value %d invalid.\n", 977 dev->name, odt_config); 978 return -EINVAL; 979 } 980 981 posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0); 982 if (posted_refreshes > 8 || posted_refreshes == 0) { 983 debug("%s: posted_refreshes value %d invalid.\n", 984 dev->name, posted_refreshes); 985 return -EINVAL; 986 } 987 988 sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT | 989 dll_reset << SDRAM_CFG2_DLL_RST_DIS | 990 dqs_config << SDRAM_CFG2_DQS_CFG | 991 odt_config << SDRAM_CFG2_ODT_CFG | 992 posted_refreshes << SDRAM_CFG2_NUM_PR; 993 994 out_be32(&im->ddr.sdram_cfg2, sdram_cfg2); 995 996 sdmode = dev_read_u32_default(dev, "sdmode", 0); 997 if (sdmode > 0xFFFF) { 998 debug("%s: sdmode value %d invalid.\n", 999 dev->name, sdmode); 1000 return -EINVAL; 1001 } 1002 1003 esdmode = dev_read_u32_default(dev, "esdmode", 0); 1004 if (esdmode > 0xFFFF) { 1005 debug("%s: esdmode value %d invalid.\n", dev->name, esdmode); 1006 return -EINVAL; 1007 } 1008 1009 sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT | 1010 esdmode << SDRAM_MODE_ESD_SHIFT; 1011 1012 out_be32(&im->ddr.sdram_mode, sdram_mode); 1013 1014 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); 1015 if (esdmode2 > 0xFFFF) { 1016 debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2); 1017 return -EINVAL; 1018 } 1019 1020 esdmode3 = dev_read_u32_default(dev, "esdmode3", 0); 1021 if (esdmode3 > 0xFFFF) { 1022 debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3); 1023 return -EINVAL; 1024 } 1025 1026 sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT | 1027 esdmode3 << SDRAM_MODE2_ESD3_SHIFT; 1028 1029 out_be32(&im->ddr.sdram_mode2, sdram_mode2); 1030 1031 refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0); 1032 if (refresh_interval > 0xFFFF) { 1033 debug("%s: refresh_interval value %d invalid.\n", 1034 dev->name, refresh_interval); 1035 return -EINVAL; 1036 } 1037 1038 precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0); 1039 if (precharge_interval > 0x3FFF) { 1040 debug("%s: precharge_interval value %d invalid.\n", 1041 dev->name, precharge_interval); 1042 return -EINVAL; 1043 } 1044 1045 sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT | 1046 precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT; 1047 1048 out_be32(&im->ddr.sdram_interval, sdram_interval); 1049 sync(); 1050 1051 /* Enable DDR controller */ 1052 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 1053 sync(); 1054 1055 dev_for_each_subnode(subnode, dev) { 1056 u32 val[3]; 1057 u32 addr, size; 1058 1059 /* CS, map address, size -> three values */ 1060 ofnode_read_u32_array(subnode, "reg", val, 3); 1061 1062 addr = val[1]; 1063 size = val[2]; 1064 1065 priv->total_size += get_ram_size((long int *)addr, size); 1066 }; 1067 1068 gd->ram_size = priv->total_size; 1069 1070 return 0; 1071 } 1072 1073 static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info) 1074 { 1075 /* TODO(mario.six@gdsys.cc): Implement */ 1076 return 0; 1077 } 1078 1079 static struct ram_ops mpc83xx_sdram_ops = { 1080 .get_info = mpc83xx_sdram_get_info, 1081 }; 1082 1083 static const struct udevice_id mpc83xx_sdram_ids[] = { 1084 { .compatible = "fsl,mpc83xx-mem-controller" }, 1085 { /* sentinel */ } 1086 }; 1087 1088 U_BOOT_DRIVER(mpc83xx_sdram) = { 1089 .name = "mpc83xx_sdram", 1090 .id = UCLASS_RAM, 1091 .of_match = mpc83xx_sdram_ids, 1092 .ops = &mpc83xx_sdram_ops, 1093 .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata, 1094 .probe = mpc83xx_sdram_probe, 1095 .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv), 1096 }; 1097