1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek DDR3 driver for MT7629 SoC
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Wu Zou <wu.zou@mediatek.com>
7 * Ryder Lee <ryder.lee@mediatek.com>
8 */
9
10 #include <clk.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <ram.h>
14 #include <asm/io.h>
15
16 /* EMI */
17 #define EMI_CONA 0x000
18 #define EMI_CONF 0x028
19 #define EMI_CONM 0x060
20
21 /* DDR PHY */
22 #define DDRPHY_PLL1 0x0000
23 #define DDRPHY_PLL2 0x0004
24 #define DDRPHY_PLL3 0x0008
25 #define DDRPHY_PLL4 0x000c
26 #define DDRPHY_PLL5 0x0010
27 #define DDRPHY_PLL7 0x0018
28 #define DDRPHY_B0_DLL_ARPI0 0x0080
29 #define DDRPHY_B0_DLL_ARPI1 0x0084
30 #define DDRPHY_B0_DLL_ARPI2 0x0088
31 #define DDRPHY_B0_DLL_ARPI3 0x008c
32 #define DDRPHY_B0_DLL_ARPI4 0x0090
33 #define DDRPHY_B0_DLL_ARPI5 0x0094
34 #define DDRPHY_B0_DQ2 0x00a0
35 #define DDRPHY_B0_DQ3 0x00a4
36 #define DDRPHY_B0_DQ4 0x00a8
37 #define DDRPHY_B0_DQ5 0x00ac
38 #define DDRPHY_B0_DQ6 0x00b0
39 #define DDRPHY_B0_DQ7 0x00b4
40 #define DDRPHY_B0_DQ8 0x00b8
41 #define DDRPHY_B1_DLL_ARPI0 0x0100
42 #define DDRPHY_B1_DLL_ARPI1 0x0104
43 #define DDRPHY_B1_DLL_ARPI2 0x0108
44 #define DDRPHY_B1_DLL_ARPI3 0x010c
45 #define DDRPHY_B1_DLL_ARPI4 0x0110
46 #define DDRPHY_B1_DLL_ARPI5 0x0114
47 #define DDRPHY_B1_DQ2 0x0120
48 #define DDRPHY_B1_DQ3 0x0124
49 #define DDRPHY_B1_DQ4 0x0128
50 #define DDRPHY_B1_DQ5 0x012c
51 #define DDRPHY_B1_DQ6 0x0130
52 #define DDRPHY_B1_DQ7 0x0134
53 #define DDRPHY_B1_DQ8 0x0138
54 #define DDRPHY_CA_DLL_ARPI0 0x0180
55 #define DDRPHY_CA_DLL_ARPI1 0x0184
56 #define DDRPHY_CA_DLL_ARPI2 0x0188
57 #define DDRPHY_CA_DLL_ARPI3 0x018c
58 #define DDRPHY_CA_DLL_ARPI4 0x0190
59 #define DDRPHY_CA_DLL_ARPI5 0x0194
60 #define DDRPHY_CA_CMD2 0x01a0
61 #define DDRPHY_CA_CMD3 0x01a4
62 #define DDRPHY_CA_CMD5 0x01ac
63 #define DDRPHY_CA_CMD6 0x01b0
64 #define DDRPHY_CA_CMD7 0x01b4
65 #define DDRPHY_CA_CMD8 0x01b8
66 #define DDRPHY_MISC_VREF_CTRL 0x0264
67 #define DDRPHY_MISC_IMP_CTRL0 0x0268
68 #define DDRPHY_MISC_IMP_CTRL1 0x026c
69 #define DDRPHY_MISC_SHU_OPT 0x0270
70 #define DDRPHY_MISC_SPM_CTRL0 0x0274
71 #define DDRPHY_MISC_SPM_CTRL1 0x0278
72 #define DDRPHY_MISC_SPM_CTRL2 0x027c
73 #define DDRPHY_MISC_CG_CTRL0 0x0284
74 #define DDRPHY_MISC_CG_CTRL1 0x0288
75 #define DDRPHY_MISC_CG_CTRL2 0x028c
76 #define DDRPHY_MISC_CG_CTRL4 0x0294
77 #define DDRPHY_MISC_CTRL0 0x029c
78 #define DDRPHY_MISC_CTRL1 0x02a0
79 #define DDRPHY_MISC_CTRL3 0x02a8
80 #define DDRPHY_MISC_RXDVS1 0x05e4
81 #define DDRPHY_SHU1_B0_DQ4 0x0c10
82 #define DDRPHY_SHU1_B0_DQ5 0x0c14
83 #define DDRPHY_SHU1_B0_DQ6 0x0c18
84 #define DDRPHY_SHU1_B0_DQ7 0x0c1c
85 #define DDRPHY_SHU1_B1_DQ4 0x0c90
86 #define DDRPHY_SHU1_B1_DQ5 0x0c94
87 #define DDRPHY_SHU1_B1_DQ6 0x0c98
88 #define DDRPHY_SHU1_B1_DQ7 0x0c9c
89 #define DDRPHY_SHU1_CA_CMD2 0x0d08
90 #define DDRPHY_SHU1_CA_CMD4 0x0d10
91 #define DDRPHY_SHU1_CA_CMD5 0x0d14
92 #define DDRPHY_SHU1_CA_CMD6 0x0d18
93 #define DDRPHY_SHU1_CA_CMD7 0x0d1c
94 #define DDRPHY_SHU1_PLL0 0x0d80
95 #define DDRPHY_SHU1_PLL1 0x0d84
96 #define DDRPHY_SHU1_PLL4 0x0d90
97 #define DDRPHY_SHU1_PLL5 0x0d94
98 #define DDRPHY_SHU1_PLL6 0x0d98
99 #define DDRPHY_SHU1_PLL7 0x0d9C
100 #define DDRPHY_SHU1_PLL8 0x0da0
101 #define DDRPHY_SHU1_PLL9 0x0da4
102 #define DDRPHY_SHU1_PLL10 0x0da8
103 #define DDRPHY_SHU1_PLL11 0x0dac
104 #define DDRPHY_SHU1_R0_B0_DQ2 0x0e08
105 #define DDRPHY_SHU1_R0_B0_DQ3 0x0e0c
106 #define DDRPHY_SHU1_R0_B0_DQ4 0x0e10
107 #define DDRPHY_SHU1_R0_B0_DQ5 0x0e14
108 #define DDRPHY_SHU1_R0_B0_DQ6 0x0e18
109 #define DDRPHY_SHU1_R0_B0_DQ7 0x0e1c
110 #define DDRPHY_SHU1_R0_B1_DQ2 0x0e58
111 #define DDRPHY_SHU1_R0_B1_DQ3 0x0e5c
112 #define DDRPHY_SHU1_R0_B1_DQ4 0x0e60
113 #define DDRPHY_SHU1_R0_B1_DQ5 0x0e64
114 #define DDRPHY_SHU1_R0_B1_DQ6 0x0e68
115 #define DDRPHY_SHU1_R0_B1_DQ7 0x0e6c
116 #define DDRPHY_SHU1_R0_CA_CMD9 0x0ec4
117 #define DDRPHY_SHU1_R1_B0_DQ2 0x0f08
118 #define DDRPHY_SHU1_R1_B0_DQ3 0x0f0c
119 #define DDRPHY_SHU1_R1_B0_DQ4 0x0f10
120 #define DDRPHY_SHU1_R1_B0_DQ5 0x0f14
121 #define DDRPHY_SHU1_R1_B0_DQ6 0x0f18
122 #define DDRPHY_SHU1_R1_B0_DQ7 0x0f1c
123 #define DDRPHY_SHU1_R1_B1_DQ2 0x0f58
124 #define DDRPHY_SHU1_R1_B1_DQ3 0x0f5c
125 #define DDRPHY_SHU1_R1_B1_DQ4 0x0f60
126 #define DDRPHY_SHU1_R1_B1_DQ5 0x0f64
127 #define DDRPHY_SHU1_R1_B1_DQ6 0x0f68
128 #define DDRPHY_SHU1_R1_B1_DQ7 0x0f6c
129 #define DDRPHY_SHU1_R1_CA_CMD9 0x0fc4
130
131 /* DRAMC */
132 #define DRAMC_DDRCONF0 0x0000
133 #define DRAMC_DRAMCTRL 0x0004
134 #define DRAMC_MISCTL0 0x0008
135 #define DRAMC_PERFCTL0 0x000c
136 #define DRAMC_ARBCTL 0x0010
137 #define DRAMC_RSTMASK 0x001c
138 #define DRAMC_PADCTRL 0x0020
139 #define DRAMC_CKECTRL 0x0024
140 #define DRAMC_RKCFG 0x0034
141 #define DRAMC_DRAMC_PD_CTRL 0x0038
142 #define DRAMC_CLKAR 0x003c
143 #define DRAMC_CLKCTRL 0x0040
144 #define DRAMC_SREFCTRL 0x0048
145 #define DRAMC_REFCTRL0 0x004c
146 #define DRAMC_REFCTRL1 0x0050
147 #define DRAMC_REFRATRE_FILTER 0x0054
148 #define DRAMC_ZQCS 0x0058
149 #define DRAMC_MRS 0x005c
150 #define DRAMC_SPCMD 0x0060
151 #define DRAMC_SPCMDCTRL 0x0064
152 #define DRAMC_HW_MRR_FUN 0x0074
153 #define DRAMC_TEST2_1 0x0094
154 #define DRAMC_TEST2_2 0x0098
155 #define DRAMC_TEST2_3 0x009c
156 #define DRAMC_TEST2_4 0x00a0
157 #define DRAMC_CATRAINING1 0x00b0
158 #define DRAMC_DUMMY_RD 0x00d0
159 #define DRAMC_SHUCTRL 0x00d4
160 #define DRAMC_SHUCTRL2 0x00dc
161 #define DRAMC_STBCAL 0x0200
162 #define DRAMC_STBCAL1 0x0204
163 #define DRAMC_EYESCAN 0x020c
164 #define DRAMC_DVFSDLL 0x0210
165 #define DRAMC_SHU_ACTIM0 0x0800
166 #define DRAMC_SHU_ACTIM1 0x0804
167 #define DRAMC_SHU_ACTIM2 0x0808
168 #define DRAMC_SHU_ACTIM3 0x080c
169 #define DRAMC_SHU_ACTIM4 0x0810
170 #define DRAMC_SHU_ACTIM5 0x0814
171 #define DRAMC_SHU_ACTIM_XRT 0x081c
172 #define DRAMC_SHU_AC_TIME_05T 0x0820
173 #define DRAMC_SHU_CONF0 0x0840
174 #define DRAMC_SHU_CONF1 0x0844
175 #define DRAMC_SHU_CONF2 0x0848
176 #define DRAMC_SHU_CONF3 0x084c
177 #define DRAMC_SHU_RANKCTL 0x0858
178 #define DRAMC_SHU_CKECTRL 0x085c
179 #define DRAMC_SHU_ODTCTRL 0x0860
180 #define DRAMC_SHU_PIPE 0x0878
181 #define DRAMC_SHU_SELPH_CA1 0x0880
182 #define DRAMC_SHU_SELPH_CA2 0x0884
183 #define DRAMC_SHU_SELPH_CA3 0x0888
184 #define DRAMC_SHU_SELPH_CA4 0x088c
185 #define DRAMC_SHU_SELPH_CA5 0x0890
186 #define DRAMC_SHU_SELPH_CA6 0x0894
187 #define DRAMC_SHU_SELPH_CA7 0x0898
188 #define DRAMC_SHU_SELPH_CA8 0x089c
189 #define DRAMC_SHU_SELPH_DQS0 0x08a0
190 #define DRAMC_SHU_SELPH_DQS1 0x08a4
191 #define DRAMC_SHU1_DRVING1 0x08a8
192 #define DRAMC_SHU1_DRVING2 0x08ac
193 #define DRAMC_SHU1_WODT 0x08c0
194 #define DRAMC_SHU_SCINTV 0x08c8
195 #define DRAMC_SHURK0_DQSCTL 0x0a00
196 #define DRAMC_SHURK0_DQSIEN 0x0a04
197 #define DRAMC_SHURK0_SELPH_ODTEN0 0x0a1c
198 #define DRAMC_SHURK0_SELPH_ODTEN1 0x0a20
199 #define DRAMC_SHURK0_SELPH_DQSG0 0x0a24
200 #define DRAMC_SHURK0_SELPH_DQSG1 0x0a28
201 #define DRAMC_SHURK0_SELPH_DQ0 0x0a2c
202 #define DRAMC_SHURK0_SELPH_DQ1 0x0a30
203 #define DRAMC_SHURK0_SELPH_DQ2 0x0a34
204 #define DRAMC_SHURK0_SELPH_DQ3 0x0a38
205 #define DRAMC_SHURK1_DQSCTL 0x0b00
206 #define DRAMC_SHURK1_SELPH_ODTEN0 0x0b1c
207 #define DRAMC_SHURK1_SELPH_ODTEN1 0x0b20
208 #define DRAMC_SHURK1_SELPH_DQSG0 0x0b24
209 #define DRAMC_SHURK1_SELPH_DQSG1 0x0b28
210 #define DRAMC_SHURK1_SELPH_DQ0 0x0b2c
211 #define DRAMC_SHURK1_SELPH_DQ1 0x0b30
212 #define DRAMC_SHURK1_SELPH_DQ2 0x0b34
213 #define DRAMC_SHURK1_SELPH_DQ3 0x0b38
214 #define DRAMC_SHURK2_SELPH_ODTEN0 0x0c1c
215 #define DRAMC_SHURK2_SELPH_ODTEN1 0x0c20
216 #define DRAMC_SHU_DQSG_RETRY 0x0c54
217
218 #define EMI_COL_ADDR_MASK GENMASK(13, 12)
219 #define EMI_COL_ADDR_SHIFT 12
220 #define WALKING_PATTERN 0x12345678
221 #define WALKING_STEP 0x4000000
222
223 struct mtk_ddr3_priv {
224 fdt_addr_t emi;
225 fdt_addr_t ddrphy;
226 fdt_addr_t dramc_ao;
227 struct clk phy;
228 struct clk phy_mux;
229 struct clk mem;
230 struct clk mem_mux;
231 };
232
233 #ifdef CONFIG_SPL_BUILD
mtk_ddr3_rank_size_detect(struct udevice * dev)234 static int mtk_ddr3_rank_size_detect(struct udevice *dev)
235 {
236 struct mtk_ddr3_priv *priv = dev_get_priv(dev);
237 int step;
238 u32 start, test;
239
240 /* To detect size, we have to make sure it's single rank
241 * and it has maximum addressing region
242 */
243
244 writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
245
246 if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
247 return -EINVAL;
248
249 for (step = 0; step < 5; step++) {
250 writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
251 (WALKING_STEP << step));
252
253 start = readl(CONFIG_SYS_SDRAM_BASE);
254 test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
255 if ((test != ~WALKING_PATTERN) || test == start)
256 break;
257 }
258
259 step = step ? step - 1 : 3;
260 clrsetbits_le32(priv->emi + EMI_CONA, EMI_COL_ADDR_MASK,
261 step << EMI_COL_ADDR_SHIFT);
262
263 return 0;
264 }
265
mtk_ddr3_init(struct udevice * dev)266 static int mtk_ddr3_init(struct udevice *dev)
267 {
268 struct mtk_ddr3_priv *priv = dev_get_priv(dev);
269 int ret;
270
271 ret = clk_set_parent(&priv->phy, &priv->phy_mux);
272 if (ret)
273 return ret;
274
275 /* EMI Setting */
276 writel(0x00003010, priv->emi + EMI_CONA);
277 writel(0x00000000, priv->emi + EMI_CONF);
278 writel(0x000006b8, priv->emi + EMI_CONM);
279 /* DQS */
280 writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1);
281 /* Clock */
282 writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2);
283
284 /* DDRPHY setting */
285 writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL);
286 writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
287 writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5);
288 writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5);
289 writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1);
290 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0);
291 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2);
292 writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2);
293 writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
294
295 writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7);
296 writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
297 writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
298 writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2);
299 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
300 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2);
301 writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1);
302 writel(0x10, priv->ddrphy + DDRPHY_PLL3);
303 writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL);
304 writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0);
305 writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
306 writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
307 udelay(1);
308
309 writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3);
310 writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3);
311 writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1);
312 writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4);
313 writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
314 writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6);
315 writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
316 writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4);
317 writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
318 writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6);
319 writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
320 writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3);
321 writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6);
322 writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2);
323 writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3);
324 writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3);
325 writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8);
326 writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1);
327 writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
328 writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT);
329 writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
330
331 writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
332 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
333 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
334 writel(0x40000, priv->ddrphy + DDRPHY_PLL4);
335 writel(0x0, priv->ddrphy + DDRPHY_PLL1);
336 writel(0x0, priv->ddrphy + DDRPHY_PLL2);
337 writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
338 writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
339 writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
340 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
341 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
342 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
343 writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
344 writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
345 writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
346 writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9);
347 writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11);
348 writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0);
349 writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8);
350 writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10);
351 writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4);
352 writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6);
353
354 writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5);
355 writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7);
356
357 writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5);
358 writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7);
359 writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8);
360 writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10);
361 writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1);
362 writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
363 writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
364 writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
365 writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
366 writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
367 writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
368 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4);
369 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4);
370 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4);
371 writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1);
372 writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1);
373 writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1);
374 writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3);
375 writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3);
376 writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3);
377 writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4);
378 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4);
379 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4);
380 writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
381 writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
382 writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
383 writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
384 writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
385 writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
386 writel(0x80010000, priv->ddrphy + DDRPHY_PLL1);
387 writel(0x80000000, priv->ddrphy + DDRPHY_PLL2);
388 udelay(100);
389
390 writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
391 writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
392 writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
393 writel(0xd0000, priv->ddrphy + DDRPHY_PLL4);
394 udelay(1);
395
396 writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1);
397 writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0);
398 writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
399 writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
400 writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
401 udelay(1);
402
403 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
404 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
405 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
406 writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1);
407 writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0);
408 writel(0x80000000, priv->ddrphy + DDRPHY_PLL1);
409 udelay(1);
410
411 writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
412 udelay(1);
413
414 writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
415 udelay(1);
416
417 writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
418 udelay(1);
419
420 ret = clk_set_parent(&priv->mem, &priv->mem_mux);
421 if (ret)
422 return ret;
423
424 /* DDR PHY PLL setting */
425 writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
426 writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3);
427 writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
428 writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8);
429 writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7);
430 writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7);
431 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7);
432 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7);
433 writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
434 writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3);
435 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
436 writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2);
437
438 /* Update initial setting */
439 writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3);
440 writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3);
441 writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6);
442 writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6);
443 writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6);
444 writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2);
445 writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2);
446 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8);
447 writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8);
448 writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
449 writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
450 writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
451 writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
452 writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV);
453 writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR);
454 writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
455 writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0);
456 writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0);
457
458 /* Dramc setting PC3 */
459 writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
460
461 writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
462 writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY);
463 writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2);
464 writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL);
465 writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0);
466 writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0);
467 writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0);
468 writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL);
469 writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0);
470 writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL);
471 writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL);
472 writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE);
473 writel(0x731004, priv->dramc_ao + DRAMC_RKCFG);
474 writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2);
475 writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV);
476 writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL);
477 writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1);
478 writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER);
479
480 /* Update PCDDR3 default setting */
481 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1);
482 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2);
483 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3);
484 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4);
485 writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5);
486 writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6);
487 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7);
488 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8);
489 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9);
490 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9);
491 writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
492 writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
493 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
494 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
495 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
496 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
497 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0);
498 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1);
499 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2);
500 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3);
501 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
502 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7);
503 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
504 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7);
505 writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0);
506 writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1);
507 writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0);
508 writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1);
509 writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0);
510 writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1);
511 writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
512 writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
513 writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
514 writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0);
515 writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1);
516 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
517 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
518 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
519 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
520 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6);
521 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2);
522 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3);
523 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4);
524 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5);
525 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6);
526 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
527 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
528 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
529 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
530 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6);
531 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2);
532 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3);
533 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4);
534 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5);
535 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6);
536 writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL);
537 writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL);
538 writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL);
539 writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0);
540 writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1);
541 writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2);
542 writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3);
543 writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4);
544 writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5);
545 writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT);
546 writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T);
547 writel(0x80010000, priv->ddrphy + DDRPHY_PLL2);
548 udelay(500);
549
550 writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0);
551 writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0);
552 writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0);
553 writel(0x80, priv->dramc_ao + DRAMC_ARBCTL);
554 writel(0x9, priv->dramc_ao + DRAMC_PADCTRL);
555 writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
556 writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
557 writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0);
558 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
559 writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1);
560 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
561 writel(0x731414, priv->dramc_ao + DRAMC_RKCFG);
562 writel(0x733414, priv->dramc_ao + DRAMC_RKCFG);
563 udelay(20);
564
565 writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL);
566 udelay(100);
567
568 writel(0x400000, priv->dramc_ao + DRAMC_MRS);
569 writel(0x401800, priv->dramc_ao + DRAMC_MRS);
570 writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
571 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
572 udelay(100);
573
574 writel(0x601800, priv->dramc_ao + DRAMC_MRS);
575 writel(0x600000, priv->dramc_ao + DRAMC_MRS);
576 writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
577 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
578 udelay(100);
579
580 writel(0x200000, priv->dramc_ao + DRAMC_MRS);
581 writel(0x200400, priv->dramc_ao + DRAMC_MRS);
582 writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
583 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
584 udelay(100);
585
586 writel(0x400, priv->dramc_ao + DRAMC_MRS);
587 writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
588 writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
589 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
590 udelay(100);
591
592 writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL);
593 writel(0x10, priv->dramc_ao + DRAMC_SPCMD);
594 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
595 writel(0x20, priv->dramc_ao + DRAMC_SPCMD);
596 writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
597 writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN);
598 writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
599 writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
600 writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
601 writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3);
602 writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
603 writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
604 writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
605 writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL);
606 writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
607 writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
608 writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1);
609 writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1);
610 writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2);
611 writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3);
612 writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2);
613 writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL);
614 writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL);
615 writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD);
616 writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4);
617 writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1);
618 writel(0x0, priv->dramc_ao + DRAMC_RSTMASK);
619 writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
620 writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL);
621 writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
622
623 /* Apply config before calibration */
624 writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
625 writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
626 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
627 writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV);
628 writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3);
629 writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
630 writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
631 writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT);
632 writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
633 writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
634 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
635 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
636 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
637 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
638 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
639 writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
640 writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
641 writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
642 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
643 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
644
645 /* Write leveling */
646 writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
647 writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
648 writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
649 writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
650
651 /* RX dqs gating cal */
652 writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
653 writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
654 writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN);
655
656 /* RX window per-bit cal */
657 writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
658 writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
659 writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
660 writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
661 writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
662 writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
663 writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
664 writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
665
666 /* RX datlat cal */
667 writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1);
668
669 /* TX window per-byte with 2UI cal */
670 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
671 writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
672 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
673 writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
674 writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
675 writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
676
677 return mtk_ddr3_rank_size_detect(dev);
678 }
679 #endif
680
mtk_ddr3_probe(struct udevice * dev)681 static int mtk_ddr3_probe(struct udevice *dev)
682 {
683 struct mtk_ddr3_priv *priv = dev_get_priv(dev);
684
685 priv->emi = dev_read_addr_index(dev, 0);
686 if (priv->emi == FDT_ADDR_T_NONE)
687 return -EINVAL;
688
689 priv->ddrphy = dev_read_addr_index(dev, 1);
690 if (priv->ddrphy == FDT_ADDR_T_NONE)
691 return -EINVAL;
692
693 priv->dramc_ao = dev_read_addr_index(dev, 2);
694 if (priv->dramc_ao == FDT_ADDR_T_NONE)
695 return -EINVAL;
696
697 #ifdef CONFIG_SPL_BUILD
698 int ret;
699
700 ret = clk_get_by_index(dev, 0, &priv->phy);
701 if (ret)
702 return ret;
703
704 ret = clk_get_by_index(dev, 1, &priv->phy_mux);
705 if (ret)
706 return ret;
707
708 ret = clk_get_by_index(dev, 2, &priv->mem);
709 if (ret)
710 return ret;
711
712 ret = clk_get_by_index(dev, 3, &priv->mem_mux);
713 if (ret)
714 return ret;
715
716 ret = mtk_ddr3_init(dev);
717 if (ret)
718 return ret;
719 #endif
720 return 0;
721 }
722
mtk_ddr3_get_info(struct udevice * dev,struct ram_info * info)723 static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info)
724 {
725 struct mtk_ddr3_priv *priv = dev_get_priv(dev);
726 u32 val = readl(priv->emi + EMI_CONA);
727
728 info->base = CONFIG_SYS_SDRAM_BASE;
729
730 switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
731 case 0:
732 info->size = SZ_128M;
733 break;
734 case 1:
735 info->size = SZ_256M;
736 break;
737 case 2:
738 info->size = SZ_512M;
739 break;
740 case 3:
741 info->size = SZ_1G;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 return 0;
748 }
749
750 static struct ram_ops mtk_ddr3_ops = {
751 .get_info = mtk_ddr3_get_info,
752 };
753
754 static const struct udevice_id mtk_ddr3_ids[] = {
755 { .compatible = "mediatek,mt7629-dramc" },
756 { }
757 };
758
759 U_BOOT_DRIVER(mediatek_ddr3) = {
760 .name = "mediatek_ddr3",
761 .id = UCLASS_RAM,
762 .of_match = mtk_ddr3_ids,
763 .ops = &mtk_ddr3_ops,
764 .probe = mtk_ddr3_probe,
765 .priv_auto_alloc_size = sizeof(struct mtk_ddr3_priv),
766 };
767