1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Texas Instruments' AM654 DDRSS driver 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Lokesh Vutla <lokeshvutla@ti.com> 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <ram.h> 13 #include <asm/io.h> 14 #include <power-domain.h> 15 #include <dm.h> 16 #include <asm/arch/sys_proto.h> 17 #include <power/regulator.h> 18 #include "k3-am654-ddrss.h" 19 20 #define LDELAY 10000 21 22 /* DDRSS PHY configuration register fixed values */ 23 #define DDRSS_DDRPHY_RANKIDR_RANK0 0 24 25 /** 26 * struct am654_ddrss_desc - Description of ddrss integration. 27 * @dev: DDRSS device pointer 28 * @ddrss_ss_cfg: DDRSS wrapper logic region base address 29 * @ddrss_ctl_cfg: DDRSS controller region base address 30 * @ddrss_phy_cfg: DDRSS PHY region base address 31 * @ddrss_clk: DDRSS clock description 32 * @vtt_supply: VTT Supply regulator 33 * @ddrss_pwrdmn: DDRSS power domain description 34 * @params: SDRAM configuration parameters 35 */ 36 struct am654_ddrss_desc { 37 struct udevice *dev; 38 void __iomem *ddrss_ss_cfg; 39 void __iomem *ddrss_ctl_cfg; 40 void __iomem *ddrss_phy_cfg; 41 struct clk ddrss_clk; 42 struct udevice *vtt_supply; 43 struct power_domain ddrcfg_pwrdmn; 44 struct power_domain ddrdata_pwrdmn; 45 struct ddrss_params params; 46 }; 47 48 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset) 49 { 50 return readl(addr + offset); 51 } 52 53 static inline void ddrss_writel(void __iomem *addr, unsigned int offset, 54 u32 data) 55 { 56 debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data); 57 writel(data, addr + offset); 58 } 59 60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val) 61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off) 62 63 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss) 64 { 65 return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK; 66 } 67 68 /** 69 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete 70 * 71 * After detecting the DDR type this function will pause until the 72 * initialization is complete. Each DDR type has mask of multiple bits. 73 * The size of the field depends on the DDR Type. If the initialization 74 * does not complete and error will be returned and will cause the boot to halt. 75 * 76 */ 77 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss) 78 { 79 u32 val, mask; 80 81 val = am654_ddrss_get_type(ddrss); 82 83 switch (val) { 84 case DDR_TYPE_LPDDR4: 85 case DDR_TYPE_DDR4: 86 mask = DDR4_STAT_MODE_MASK; 87 break; 88 case DDR_TYPE_DDR3: 89 mask = DDR3_STAT_MODE_MASK; 90 break; 91 default: 92 printf("Unsupported DDR type 0x%x\n", val); 93 return -EINVAL; 94 } 95 96 if (!wait_on_value(mask, DDR_MODE_NORMAL, 97 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY)) 98 return -ETIMEDOUT; 99 100 return 0; 101 } 102 103 /** 104 * am654_ddrss_ctrl_configuration() - Configure Controller specific registers 105 * @dev: corresponding ddrss device 106 */ 107 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss) 108 { 109 struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing; 110 struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg; 111 struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc; 112 struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc; 113 struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map; 114 u32 val; 115 116 debug("%s: DDR controller register configuration started\n", __func__); 117 118 ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr); 119 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0); 120 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg); 121 122 ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0); 123 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0); 124 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1); 125 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2); 126 127 ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0); 128 ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1); 129 ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3); 130 ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4); 131 ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5); 132 ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6); 133 ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7); 134 135 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0); 136 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1); 137 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2); 138 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3); 139 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4); 140 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5); 141 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8); 142 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9); 143 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11); 144 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12); 145 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13); 146 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15); 147 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17); 148 149 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0); 150 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1); 151 152 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0); 153 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1); 154 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2); 155 156 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0); 157 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1); 158 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2); 159 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3); 160 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4); 161 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5); 162 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6); 163 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7); 164 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8); 165 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9); 166 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10); 167 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11); 168 169 ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg); 170 ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap); 171 172 /* Disable refreshes */ 173 val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3); 174 val |= 0x01; 175 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val); 176 177 debug("%s: DDR controller configuration completed\n", __func__); 178 } 179 180 #define ddrss_phy_writel(off, val) \ 181 do { \ 182 ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \ 183 sdelay(10); /* Delay at least 20 clock cycles */ \ 184 } while (0) 185 186 #define ddrss_phy_readl(off) \ 187 ({ \ 188 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \ 189 sdelay(10); /* Delay at least 20 clock cycles */ \ 190 val; \ 191 }) 192 193 /** 194 * am654_ddrss_phy_configuration() - Configure PHY specific registers 195 * @ddrss: corresponding ddrss device 196 */ 197 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) 198 { 199 struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl; 200 struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing; 201 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; 202 struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg; 203 struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq; 204 205 debug("%s: DDR phy register configuration started\n", __func__); 206 207 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1); 208 ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2); 209 ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3); 210 ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6); 211 212 ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3); 213 ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4); 214 ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5); 215 ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6); 216 217 ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0); 218 219 ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr); 220 ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr); 221 222 ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr); 223 224 ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0); 225 ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1); 226 ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2); 227 ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3); 228 ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4); 229 ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5); 230 ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6); 231 232 ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr); 233 ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0); 234 ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0); 235 236 ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0); 237 ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1); 238 ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2); 239 ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3); 240 ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4); 241 ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5); 242 ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6); 243 244 ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0); 245 246 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0); 247 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0); 248 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0); 249 250 ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0); 251 ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1); 252 253 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); 254 ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); 255 256 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0); 257 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1); 258 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2); 259 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3); 260 261 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4); 262 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4); 263 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4); 264 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4); 265 266 ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5); 267 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5); 268 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5); 269 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5); 270 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5); 271 272 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0); 273 274 ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0); 275 ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0); 276 ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0); 277 ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0); 278 ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr); 279 280 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr); 281 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr); 282 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr); 283 284 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2); 285 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2); 286 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2); 287 288 debug("%s: DDR phy register configuration completed\n", __func__); 289 } 290 291 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss, 292 u32 init_value, u32 sts_mask, 293 u32 err_mask) 294 { 295 int ret; 296 297 ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK); 298 299 sdelay(5); /* Delay at least 10 clock cycles */ 300 301 if (!wait_on_value(sts_mask, sts_mask, 302 ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY)) 303 return -ETIMEDOUT; 304 305 sdelay(16); /* Delay at least 32 clock cycles */ 306 307 ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0); 308 debug("%s: PGSR0 val = 0x%x\n", __func__, ret); 309 if (ret & err_mask) 310 return -EINVAL; 311 312 return 0; 313 } 314 315 int write_leveling(struct am654_ddrss_desc *ddrss) 316 { 317 int ret; 318 319 debug("%s: Write leveling started\n", __func__); 320 321 ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK, 322 PGSR0_WLERR_MASK); 323 if (ret) { 324 if (ret == -ETIMEDOUT) 325 printf("%s: ERROR: Write leveling timedout\n", 326 __func__); 327 else 328 printf("%s:ERROR: Write leveling failed\n", __func__); 329 return ret; 330 } 331 332 debug("%s: Write leveling completed\n", __func__); 333 return 0; 334 } 335 336 int read_dqs_training(struct am654_ddrss_desc *ddrss) 337 { 338 int ret; 339 340 debug("%s: Read DQS training started\n", __func__); 341 342 ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK, 343 PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK); 344 if (ret) { 345 if (ret == -ETIMEDOUT) 346 printf("%s: ERROR: Read DQS timedout\n", __func__); 347 else 348 printf("%s:ERROR: Read DQS Gate training failed\n", 349 __func__); 350 return ret; 351 } 352 353 debug("%s: Read DQS training completed\n", __func__); 354 return 0; 355 } 356 357 int rest_training(struct am654_ddrss_desc *ddrss) 358 { 359 int ret; 360 u32 val; 361 u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd; 362 363 debug("%s: Rest of the training started\n", __func__); 364 365 debug("%s: Write Leveling adjustment\n", __func__); 366 ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK, 367 PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK); 368 if (ret) { 369 if (ret == -ETIMEDOUT) 370 printf("%s:ERROR: Write Leveling adjustment timedout\n", 371 __func__); 372 else 373 printf("%s: ERROR: Write Leveling adjustment failed\n", 374 __func__); 375 return ret; 376 } 377 378 debug("%s: Read Deskew adjustment\n", __func__); 379 ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK, 380 PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK); 381 if (ret) { 382 if (ret == -ETIMEDOUT) 383 printf("%s: ERROR: Read Deskew timedout\n", __func__); 384 else 385 printf("%s: ERROR: Read Deskew failed\n", __func__); 386 return ret; 387 } 388 389 debug("%s: Write Deskew adjustment\n", __func__); 390 ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK, 391 PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK); 392 if (ret) { 393 if (ret == -ETIMEDOUT) 394 printf("%s: ERROR: Write Deskew timedout\n", __func__); 395 else 396 printf("%s: ERROR: Write Deskew failed\n", __func__); 397 return ret; 398 } 399 400 debug("%s: Read Eye training\n", __func__); 401 ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK, 402 PGSR0_REDONE_MASK, PGSR0_REERR_MASK); 403 if (ret) { 404 if (ret == -ETIMEDOUT) 405 printf("%s: ERROR: Read Eye training timedout\n", 406 __func__); 407 else 408 printf("%s: ERROR: Read Eye training failed\n", 409 __func__); 410 return ret; 411 } 412 413 debug("%s: Write Eye training\n", __func__); 414 ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK, 415 PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK); 416 if (ret) { 417 if (ret == -ETIMEDOUT) 418 printf("%s: ERROR: Write Eye training timedout\n", 419 __func__); 420 else 421 printf("%s: ERROR: Write Eye training failed\n", 422 __func__); 423 return ret; 424 } 425 426 debug("%s: VREF training\n", __func__); 427 ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK, 428 PGSR0_VERR_MASK); 429 if (ret) { 430 if (ret == -ETIMEDOUT) 431 printf("%s: ERROR: VREF training timedout\n", __func__); 432 else 433 printf("%s: ERROR: VREF training failed\n", __func__); 434 return ret; 435 } 436 437 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); 438 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2; 439 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2; 440 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2; 441 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2; 442 443 rddly = dgsl0; 444 if (dgsl1 < rddly) 445 rddly = dgsl1; 446 if (dgsl2 < rddly) 447 rddly = dgsl2; 448 if (dgsl3 < rddly) 449 rddly = dgsl3; 450 451 rddly += 5; 452 453 /* Update rddly based on dgsl values */ 454 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000); 455 val |= (rddly << 20); 456 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val); 457 458 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000); 459 val |= (rddly << 20); 460 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val); 461 462 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000); 463 val |= (rddly << 20); 464 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val); 465 466 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000); 467 val |= (rddly << 20); 468 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val); 469 470 /* 471 * Add system latency derived from training back into rd2wr and wr2rd 472 * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2 473 * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2 474 */ 475 476 /* Select rank 0 */ 477 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); 478 479 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F); 480 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F); 481 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F); 482 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F); 483 484 /* Find maximum value across all bytes */ 485 rd2wr_wr2rd = dgsl0; 486 if (dgsl1 > rd2wr_wr2rd) 487 rd2wr_wr2rd = dgsl1; 488 if (dgsl2 > rd2wr_wr2rd) 489 rd2wr_wr2rd = dgsl2; 490 if (dgsl3 > rd2wr_wr2rd) 491 rd2wr_wr2rd = dgsl3; 492 493 rd2wr_wr2rd >>= 1; 494 495 /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */ 496 /* Clear VSWCTL.sw_done */ 497 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, 498 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1); 499 /* Adjust rd2wr */ 500 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, 501 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + 502 (rd2wr_wr2rd << 8)); 503 /* Adjust wr2rd */ 504 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, 505 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + 506 rd2wr_wr2rd); 507 /* Set VSWCTL.sw_done */ 508 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, 509 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1); 510 /* Wait until settings are applied */ 511 while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) { 512 /* Do nothing */ 513 }; 514 515 debug("%s: Rest of the training completed\n", __func__); 516 return 0; 517 } 518 519 /** 520 * am654_ddrss_init() - Initialization sequence for enabling the SDRAM 521 * device attached to ddrss. 522 * @dev: corresponding ddrss device 523 * 524 * Does all the initialization sequence that is required to get attached 525 * ddr in a working state. After this point, ddr should be accessible. 526 * Return: 0 if all went ok, else corresponding error message. 527 */ 528 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) 529 { 530 int ret; 531 532 debug("%s(ddrss=%p)\n", __func__, ddrss); 533 534 ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF); 535 536 am654_ddrss_ctrl_configuration(ddrss); 537 538 /* Release the reset to the controller */ 539 clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG, 540 SS_CTL_REG_CTL_ARST_MASK); 541 542 am654_ddrss_phy_configuration(ddrss); 543 544 ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0); 545 if (ret) { 546 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret); 547 return ret; 548 } 549 550 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, 551 PGSR0_DRAM_INIT_MASK, 0); 552 if (ret) { 553 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret); 554 return ret; 555 } 556 557 ret = am654_ddrss_dram_wait_for_init_complt(ddrss); 558 if (ret) { 559 printf("%s: ERROR: DRAM Wait for init complete timedout\n", 560 __func__); 561 return ret; 562 } 563 564 ret = write_leveling(ddrss); 565 if (ret) 566 return ret; 567 568 ret = read_dqs_training(ddrss); 569 if (ret) 570 return ret; 571 572 ret = rest_training(ddrss); 573 if (ret) 574 return ret; 575 576 /* Enabling refreshes after training is done */ 577 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, 578 ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1); 579 580 /* Disable PUBMODE after training is done */ 581 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, 582 ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40); 583 584 return 0; 585 } 586 587 /** 588 * am654_ddrss_power_on() - Enable power and clocks for ddrss 589 * @dev: corresponding ddrss device 590 * 591 * Tries to enable all the corresponding clocks to the ddrss and sets it 592 * to the right frequency and then power on the ddrss. 593 * Return: 0 if all went ok, else corresponding error message. 594 */ 595 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss) 596 { 597 int ret; 598 599 debug("%s(ddrss=%p)\n", __func__, ddrss); 600 601 ret = clk_enable(&ddrss->ddrss_clk); 602 if (ret) { 603 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret); 604 return ret; 605 } 606 607 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); 608 if (ret) { 609 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); 610 return ret; 611 } 612 613 ret = power_domain_on(&ddrss->ddrdata_pwrdmn); 614 if (ret) { 615 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); 616 return ret; 617 } 618 619 /* VTT enable */ 620 #if CONFIG_IS_ENABLED(DM_REGULATOR) 621 device_get_supply_regulator(ddrss->dev, "vtt-supply", 622 &ddrss->vtt_supply); 623 ret = regulator_set_value(ddrss->vtt_supply, 3300000); 624 if (ret) 625 return ret; 626 debug("VTT regulator enabled\n"); 627 #endif 628 629 return 0; 630 } 631 632 /** 633 * am654_ddrss_ofdata_to_priv() - generate private data from device tree 634 * @dev: corresponding ddrss device 635 * 636 * Return: 0 if all went ok, else corresponding error message. 637 */ 638 static int am654_ddrss_ofdata_to_priv(struct udevice *dev) 639 { 640 struct am654_ddrss_desc *ddrss = dev_get_priv(dev); 641 phys_addr_t reg; 642 int ret; 643 644 debug("%s(dev=%p)\n", __func__, dev); 645 646 ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk); 647 if (ret) { 648 dev_err(dev, "clk_get failed: %d\n", ret); 649 return ret; 650 } 651 652 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); 653 if (ret) { 654 dev_err(dev, "power_domain_get() failed: %d\n", ret); 655 return ret; 656 } 657 658 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); 659 if (ret) { 660 dev_err(dev, "power_domain_get() failed: %d\n", ret); 661 return ret; 662 } 663 664 reg = devfdt_get_addr_name(dev, "ss"); 665 if (reg == FDT_ADDR_T_NONE) { 666 dev_err(dev, "No reg property for DDRSS wrapper logic\n"); 667 return -EINVAL; 668 } 669 ddrss->ddrss_ss_cfg = (void *)reg; 670 671 reg = devfdt_get_addr_name(dev, "ctl"); 672 if (reg == FDT_ADDR_T_NONE) { 673 dev_err(dev, "No reg property for Controller region\n"); 674 return -EINVAL; 675 } 676 ddrss->ddrss_ctl_cfg = (void *)reg; 677 678 reg = devfdt_get_addr_name(dev, "phy"); 679 if (reg == FDT_ADDR_T_NONE) { 680 dev_err(dev, "No reg property for PHY region\n"); 681 return -EINVAL; 682 } 683 ddrss->ddrss_phy_cfg = (void *)reg; 684 685 ret = dev_read_u32_array(dev, "ti,ctl-reg", 686 (u32 *)&ddrss->params.ctl_reg, 687 sizeof(ddrss->params.ctl_reg) / sizeof(u32)); 688 if (ret) { 689 dev_err(dev, "Cannot read ti,ctl-reg params\n"); 690 return ret; 691 } 692 693 ret = dev_read_u32_array(dev, "ti,ctl-crc", 694 (u32 *)&ddrss->params.ctl_crc, 695 sizeof(ddrss->params.ctl_crc) / sizeof(u32)); 696 if (ret) { 697 dev_err(dev, "Cannot read ti,ctl-crc params\n"); 698 return ret; 699 } 700 701 ret = dev_read_u32_array(dev, "ti,ctl-ecc", 702 (u32 *)&ddrss->params.ctl_ecc, 703 sizeof(ddrss->params.ctl_ecc) / sizeof(u32)); 704 if (ret) { 705 dev_err(dev, "Cannot read ti,ctl-ecc params\n"); 706 return ret; 707 } 708 709 ret = dev_read_u32_array(dev, "ti,ctl-map", 710 (u32 *)&ddrss->params.ctl_map, 711 sizeof(ddrss->params.ctl_map) / sizeof(u32)); 712 if (ret) { 713 dev_err(dev, "Cannot read ti,ctl-map params\n"); 714 return ret; 715 } 716 717 ret = dev_read_u32_array(dev, "ti,ctl-pwr", 718 (u32 *)&ddrss->params.ctl_pwr, 719 sizeof(ddrss->params.ctl_pwr) / sizeof(u32)); 720 if (ret) { 721 dev_err(dev, "Cannot read ti,ctl-pwr params\n"); 722 return ret; 723 } 724 725 ret = dev_read_u32_array(dev, "ti,ctl-timing", 726 (u32 *)&ddrss->params.ctl_timing, 727 sizeof(ddrss->params.ctl_timing) / 728 sizeof(u32)); 729 if (ret) { 730 dev_err(dev, "Cannot read ti,ctl-timing params\n"); 731 return ret; 732 } 733 734 ret = dev_read_u32_array(dev, "ti,phy-cfg", 735 (u32 *)&ddrss->params.phy_cfg, 736 sizeof(ddrss->params.phy_cfg) / sizeof(u32)); 737 if (ret) { 738 dev_err(dev, "Cannot read ti,phy-cfg params\n"); 739 return ret; 740 } 741 742 ret = dev_read_u32_array(dev, "ti,phy-ctl", 743 (u32 *)&ddrss->params.phy_ctrl, 744 sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); 745 if (ret) { 746 dev_err(dev, "Cannot read ti,phy-ctl params\n"); 747 return ret; 748 } 749 750 ret = dev_read_u32_array(dev, "ti,phy-ioctl", 751 (u32 *)&ddrss->params.phy_ioctl, 752 sizeof(ddrss->params.phy_ioctl) / sizeof(u32)); 753 if (ret) { 754 dev_err(dev, "Cannot read ti,phy-ioctl params\n"); 755 return ret; 756 } 757 758 ret = dev_read_u32_array(dev, "ti,phy-timing", 759 (u32 *)&ddrss->params.phy_timing, 760 sizeof(ddrss->params.phy_timing) / 761 sizeof(u32)); 762 if (ret) { 763 dev_err(dev, "Cannot read ti,phy-timing params\n"); 764 return ret; 765 } 766 767 ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq, 768 sizeof(ddrss->params.phy_zq) / sizeof(u32)); 769 if (ret) { 770 dev_err(dev, "Cannot read ti,phy-zq params\n"); 771 return ret; 772 } 773 774 return ret; 775 } 776 777 /** 778 * am654_ddrss_probe() - Basic probe 779 * @dev: corresponding ddrss device 780 * 781 * Return: 0 if all went ok, else corresponding error message 782 */ 783 static int am654_ddrss_probe(struct udevice *dev) 784 { 785 struct am654_ddrss_desc *ddrss = dev_get_priv(dev); 786 int ret; 787 788 debug("%s(dev=%p)\n", __func__, dev); 789 790 ret = am654_ddrss_ofdata_to_priv(dev); 791 if (ret) 792 return ret; 793 794 ddrss->dev = dev; 795 ret = am654_ddrss_power_on(ddrss); 796 if (ret) 797 return ret; 798 799 ret = am654_ddrss_init(ddrss); 800 801 return ret; 802 } 803 804 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info) 805 { 806 return 0; 807 } 808 809 static struct ram_ops am654_ddrss_ops = { 810 .get_info = am654_ddrss_get_info, 811 }; 812 813 static const struct udevice_id am654_ddrss_ids[] = { 814 { .compatible = "ti,am654-ddrss" }, 815 { } 816 }; 817 818 U_BOOT_DRIVER(am654_ddrss) = { 819 .name = "am654_ddrss", 820 .id = UCLASS_RAM, 821 .of_match = am654_ddrss_ids, 822 .ops = &am654_ddrss_ops, 823 .probe = am654_ddrss_probe, 824 .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc), 825 }; 826