1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 34 35 /* bit-field of AST_SCU_HW_STRAP */ 36 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 37 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 38 39 40 /* bit-field of AST_SCU_HANDSHAKE */ 41 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 42 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 43 44 /* bit-field of AST_SCU_MPLL */ 45 #define SCU_MPLL_RESET BIT(25) 46 #define SCU_MPLL_BYPASS BIT(24) 47 #define SCU_MPLL_TURN_OFF BIT(23) 48 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 49 50 #define SCU_MPLL_FREQ_400M 0x0008405F 51 #define SCU_MPLL_EXT_400M 0x00000031 52 //#define SCU_MPLL_FREQ_400M 0x0038007F 53 //#define SCU_MPLL_EXT_400M 0x0000003F 54 #define SCU_MPLL_FREQ_200M 0x0078007F 55 #define SCU_MPLL_EXT_200M 0x0000003F 56 #define SCU_MPLL_FREQ_100M 0x0078003F 57 #define SCU_MPLL_EXT_100M 0x0000001F 58 /* MPLL configuration */ 59 #if defined(CONFIG_ASPEED_DDR4_1600) 60 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 61 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 62 #elif defined(CONFIG_ASPEED_DDR4_800) 63 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 64 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 65 #elif defined(CONFIG_ASPEED_DDR4_400) 66 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 67 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 68 #else 69 #error "undefined DDR4 target rate\n" 70 #endif 71 72 /* AC timing and SDRAM mode registers */ 73 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 74 /* mode register settings for FPGA are fixed */ 75 #define DDR4_MR01_MODE 0x03010100 76 #define DDR4_MR23_MODE 0x00000000 77 #define DDR4_MR45_MODE 0x04C00000 78 #define DDR4_MR6_MODE 0x00000050 79 #define DDR4_TRFC_FPGA 0x17263434 80 81 /* FPGA need for an additional initialization procedure: search read window */ 82 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 83 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 84 #define SEARCH_RDWIN_PTRN_0 0x12345678 85 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 86 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 87 #else 88 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 89 #define DDR4_MR01_MODE 0x03010510 90 #define DDR4_MR23_MODE 0x00000000 91 #define DDR4_MR45_MODE 0x04000000 92 #define DDR4_MR6_MODE 0x00000400 93 #define DDR4_TRFC_1600 0x467299f1 94 #define DDR4_TRFC_800 0x23394c78 95 #define DDR4_TRFC_400 0x111c263c 96 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 97 defined(CONFIG_ASPEED_PALLADIUM)" */ 98 99 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 100 #define DDR4_TRFC DDR4_TRFC_FPGA 101 #else 102 /* real chip setting */ 103 #if defined(CONFIG_ASPEED_DDR4_1600) 104 #define DDR4_TRFC DDR4_TRFC_1600 105 #define DDR4_PHY_TRAIN_TRFC 0xc30 106 #elif defined(CONFIG_ASPEED_DDR4_800) 107 #define DDR4_TRFC DDR4_TRFC_800 108 #define DDR4_PHY_TRAIN_TRFC 0x618 109 #elif defined(CONFIG_ASPEED_DDR4_400) 110 #define DDR4_TRFC DDR4_TRFC_400 111 #define DDR4_PHY_TRAIN_TRFC 0x30c 112 #else 113 #error "undefined tRFC setting" 114 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 115 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 116 defined(CONFIG_ASPEED_PALLADIUM)" */ 117 118 /* supported SDRAM size */ 119 #define SDRAM_SIZE_1KB (1024U) 120 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 121 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 122 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 123 124 125 DECLARE_GLOBAL_DATA_PTR; 126 127 /* 128 * Bandwidth configuration parameters for different SDRAM requests. 129 * These are hardcoded settings taken from Aspeed SDK. 130 */ 131 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 132 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 133 0x00000140}; 134 135 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 136 0x88888888}; 137 #else 138 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 139 0x00001240}; 140 141 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 142 0x44444444}; 143 #endif 144 145 struct dram_info { 146 struct ram_info info; 147 struct clk ddr_clk; 148 struct ast2600_sdrammc_regs *regs; 149 void __iomem *scu; 150 struct ast2600_ddr_phy *phy; 151 void __iomem *phy_setting; 152 void __iomem *phy_status; 153 ulong clock_rate; 154 }; 155 156 static void ast2600_sdramphy_kick_training(struct dram_info *info) 157 { 158 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 159 struct ast2600_sdrammc_regs *regs = info->regs; 160 u32 volatile data; 161 162 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 163 udelay(5); 164 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 165 udelay(1000); 166 167 while (1) { 168 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 169 if (~data) { 170 break; 171 } 172 } 173 174 #if 0 175 while (1) { 176 data = readl(0x1e6e0400) & BIT(1); 177 if (data) { 178 break; 179 } 180 } 181 #endif 182 #endif 183 } 184 185 /** 186 * @brief load DDR-PHY configurations table to the PHY registers 187 * @param[in] p_tbl - pointer to the configuration table 188 * @param[in] info - pointer to the DRAM info struct 189 * 190 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 191 * system: one is in the SDRAM MC (memory controller) which is used in run 192 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 193 * training. 194 */ 195 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 196 { 197 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 198 u32 reg_base = (u32)info->phy_setting; 199 u32 addr = p_tbl[0]; 200 u32 data; 201 int i = 1; 202 203 writel(0, &info->regs->phy_ctrl[0]); 204 udelay(10); 205 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 206 207 debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, 208 addr); 209 210 /* load PHY configuration table into PHY-setting registers */ 211 while (1) { 212 if (addr < reg_base) { 213 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 214 break; 215 } 216 data = p_tbl[i++]; 217 218 if (DDR_PHY_TBL_END == data) { 219 break; 220 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 221 addr = p_tbl[i++]; 222 } else { 223 writel(data, addr); 224 addr += 4; 225 } 226 } 227 228 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 229 data |= DDR4_PHY_TRAIN_TRFC; 230 writel(data, info->phy_setting + 0x84); 231 #endif 232 } 233 234 static int ast2600_sdramphy_check_status(struct dram_info *info) 235 { 236 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 237 u32 value, tmp; 238 u32 reg_base = (u32)info->phy_status; 239 int need_retrain = 0; 240 241 debug("\nSDRAM PHY training report:\n"); 242 /* training status */ 243 value = readl(reg_base + 0x00); 244 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 245 if (value & BIT(3)) { 246 debug("\tinitial PVT calibration fail\n"); 247 } 248 if (value & BIT(5)) { 249 debug("\truntime calibration fail\n"); 250 } 251 252 /* PU & PD */ 253 value = readl(reg_base + 0x30); 254 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 255 debug(" PU = 0x%02x\n", value & 0xff); 256 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 257 258 /* read eye window */ 259 value = readl(reg_base + 0x68); 260 if (0 == (value & GENMASK(7, 0))) { 261 need_retrain = 1; 262 } 263 264 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 265 debug(" rising edge of read data eye training pass window\n"); 266 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 267 debug(" B0:%d%%\n", tmp); 268 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 269 debug(" B1:%d%%\n", tmp); 270 271 value = readl(reg_base + 0xC8); 272 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 273 debug(" falling edge of read data eye training pass window\n"); 274 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 275 debug(" B0:%d%%\n", tmp); 276 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 277 debug(" B1:%d%%\n", tmp); 278 279 /* write eye window */ 280 value = readl(reg_base + 0x7c); 281 if (0 == (value & GENMASK(7, 0))) { 282 need_retrain = 1; 283 } 284 285 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 286 debug(" rising edge of write data eye training pass window\n"); 287 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 288 debug(" B0:%d%%\n", tmp); 289 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 290 debug(" B1:%d%%\n", tmp); 291 292 /* read Vref training result */ 293 value = readl(reg_base + 0x88); 294 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 295 debug(" read Vref training result\n"); 296 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 297 debug(" B0:%d%%\n", tmp); 298 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 299 debug(" B1:%d%%\n", tmp); 300 301 /* write Vref training result */ 302 value = readl(reg_base + 0x90); 303 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 304 #if 0 305 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 306 debug(" write Vref training result = %d%%\n", tmp); 307 #endif 308 309 /* gate train */ 310 value = readl(reg_base + 0x50); 311 if ((0 == (value & GENMASK(15, 0))) || 312 (0 == (value & GENMASK(31, 16)))) { 313 need_retrain = 1; 314 } 315 #if 0 316 if (((value >> 24) & 0xff) < 3) 317 need_retrain = 1; 318 else 319 need_retrain = 0; 320 #endif 321 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 322 #if 0 323 debug(" gate training pass window\n"); 324 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 325 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 326 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 327 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 328 #endif 329 330 return need_retrain; 331 #else 332 return 0; 333 #endif 334 } 335 336 #define MC_TEST_PATTERN_N 8 337 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 338 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 339 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 340 341 #define TIMEOUT_DRAM 5000000 342 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 343 { 344 unsigned int data; 345 unsigned int timeout = 0; 346 struct ast2600_sdrammc_regs *regs = info->regs; 347 348 writel(0, ®s->ecc_test_ctrl); 349 if (mode == 0) { 350 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 351 } else { 352 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 353 } 354 355 do { 356 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 357 358 if (data & BIT(13)) 359 return (0); 360 361 if (++timeout > TIMEOUT_DRAM) { 362 printf("Timeout!!\n"); 363 writel(0, ®s->ecc_test_ctrl); 364 365 return (0); 366 } 367 } while (!data); 368 369 writel(0, ®s->ecc_test_ctrl); 370 371 return (1); 372 } 373 374 int ast2600_sdrammc_cbr_test(struct dram_info *info) 375 { 376 struct ast2600_sdrammc_regs *regs = info->regs; 377 u32 i; 378 379 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 380 381 /* single */ 382 for (i=0; i<8; i++) { 383 if(!ast2600_sdrammc_dg_test(info, i, 0)) return(0); 384 } 385 386 /* burst */ 387 for (i=0; i<8; i++) { 388 if(!ast2600_sdrammc_dg_test(info, i, i)) return(0); 389 } 390 391 return(1); 392 } 393 394 static int ast2600_sdrammc_test(struct dram_info *info) 395 { 396 struct ast2600_sdrammc_regs *regs = info->regs; 397 398 u32 pass_cnt = 0; 399 u32 fail_cnt = 0; 400 u32 target_cnt = 2; 401 u32 test_cnt = 0; 402 u32 pattern; 403 u32 i = 0; 404 bool finish = false; 405 406 debug("sdram mc test:\n"); 407 while (finish == false) { 408 pattern = as2600_sdrammc_test_pattern[i++]; 409 i = i % MC_TEST_PATTERN_N; 410 debug(" pattern = %08X : ",pattern); 411 writel(pattern, regs->test_init_val); 412 413 if (!ast2600_sdrammc_cbr_test(info)) { 414 debug("fail\n"); 415 fail_cnt++; 416 } else { 417 debug("pass\n"); 418 pass_cnt++; 419 } 420 421 if (++test_cnt == target_cnt) { 422 finish = true; 423 } 424 } 425 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 426 target_cnt); 427 return fail_cnt; 428 } 429 430 /** 431 * scu500[14:13] 432 * 2b'00: VGA memory size = 8MB 433 * 2b'01: VGA memory size = 16MB 434 * 2b'10: VGA memory size = 32MB 435 * 2b'11: VGA memory size = 64MB 436 * 437 * mcr04[3:2] 438 * 2b'00: VGA memory size = 8MB 439 * 2b'01: VGA memory size = 16MB 440 * 2b'10: VGA memory size = 32MB 441 * 2b'11: VGA memory size = 64MB 442 */ 443 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 444 { 445 u32 vga_hwconf; 446 size_t vga_mem_size_base = 8 * 1024 * 1024; 447 448 vga_hwconf = 449 (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >> 450 SCU_HWSTRAP_VGAMEM_SHIFT; 451 452 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 453 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 454 SDRAM_CONF_VGA_SIZE_MASK)); 455 456 return vga_mem_size_base << vga_hwconf; 457 } 458 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 459 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 460 { 461 u32 data; 462 u32 scu_base = (u32)info->scu; 463 464 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 465 466 do { 467 data = readl(scu_base + AST_SCU_FPGA_STATUS); 468 } while (!(data & 0x100)); 469 470 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 471 } 472 473 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 474 { 475 u32 pll, pll_min, pll_max, dat1, offset; 476 u32 win = 0x03, gwin = 0, gwinsize = 0; 477 u32 phy_setting = (u32)info->phy_setting; 478 479 #ifdef CONFIG_ASPEED_PALLADIUM 480 writel(0xc, phy_setting + 0x0000); 481 return (1); 482 #endif 483 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 484 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 485 486 while (gwin == 0) { 487 while (!(win & 0x80)) { 488 debug("Window = 0x%X\n", win); 489 writel(win, phy_setting + 0x0000); 490 491 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 492 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 493 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 494 ast2600_sdrammc_fpga_set_pll(info); 495 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 496 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 497 } 498 499 pll_min = 0xfff; 500 pll_max = 0x0; 501 pll = 0; 502 while (pll_max > 0 || pll < 256) { 503 ast2600_sdrammc_fpga_set_pll(info); 504 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 505 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 506 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 507 if (pll_min > pll) { 508 pll_min = pll; 509 } 510 if (pll_max < pll) { 511 pll_max = pll; 512 } 513 debug("%3d_(%3d:%3d)\n", pll, pll_min, 514 pll_max); 515 } else if (pll_max > 0) { 516 pll_min = pll_max - pll_min; 517 if (gwinsize < pll_min) { 518 gwin = win; 519 gwinsize = pll_min; 520 } 521 break; 522 } 523 pll += 1; 524 } 525 526 if (gwin != 0 && pll_max == 0) { 527 break; 528 } 529 win = win << 1; 530 } 531 if (gwin == 0) { 532 win = 0x7; 533 } 534 } 535 debug("Set PLL Read Gating Window = %x\n", gwin); 536 writel(gwin, phy_setting + 0x0000); 537 538 debug("PLL Read Window training\n"); 539 pll_min = 0xfff; 540 pll_max = 0x0; 541 542 debug("Search Window Start\n"); 543 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 544 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 545 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 546 ast2600_sdrammc_fpga_set_pll(info); 547 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 548 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 549 } 550 551 debug("Search Window Margin\n"); 552 pll = 0; 553 while (pll_max > 0 || pll < 256) { 554 ast2600_sdrammc_fpga_set_pll(info); 555 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 556 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 557 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 558 if (pll_min > pll) { 559 pll_min = pll; 560 } 561 if (pll_max < pll) { 562 pll_max = pll; 563 } 564 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 565 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 566 break; 567 } else if (pll_max > 0) { 568 pll_min = 0xfff; 569 pll_max = 0x0; 570 } 571 pll += 1; 572 } 573 if (pll_min < pll_max) { 574 debug("PLL Read window = %d\n", (pll_max - pll_min)); 575 offset = (pll_max - pll_min) >> 1; 576 pll_min = 0xfff; 577 pll = 0; 578 while (pll < (pll_min + offset)) { 579 ast2600_sdrammc_fpga_set_pll(info); 580 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 581 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 582 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 583 if (pll_min > pll) { 584 pll_min = pll; 585 } 586 debug("%d\n", pll); 587 } else { 588 pll_min = 0xfff; 589 pll_max = 0x0; 590 } 591 pll += 1; 592 } 593 return (1); 594 } else { 595 debug("PLL Read window training fail\n"); 596 return (0); 597 } 598 } 599 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 600 defined(CONFIG_ASPEED_PALLADIUM)" */ 601 602 /* 603 * Find out RAM size and save it in dram_info 604 * 605 * The procedure is taken from Aspeed SDK 606 */ 607 static void ast2600_sdrammc_calc_size(struct dram_info *info) 608 { 609 /* The controller supports 256/512/1024/2048 MB ram */ 610 size_t ram_size = SDRAM_MIN_SIZE; 611 const int write_test_offset = 0x100000; 612 u32 test_pattern = 0xdeadbeef; 613 u32 cap_param = SDRAM_CONF_CAP_2048M; 614 u32 refresh_timing_param = DDR4_TRFC; 615 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 616 617 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 618 ram_size >>= 1) { 619 writel(test_pattern, write_addr_base + (ram_size >> 1)); 620 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 621 } 622 623 /* One last write to overwrite all wrapped values */ 624 writel(test_pattern, write_addr_base); 625 626 /* Reset the pattern and see which value was really written */ 627 test_pattern = 0xdeadbeef; 628 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 629 ram_size >>= 1) { 630 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 631 break; 632 633 --cap_param; 634 refresh_timing_param >>= 8; 635 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 636 } 637 638 clrsetbits_le32(&info->regs->ac_timing[1], 639 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 640 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 641 << SDRAM_AC_TRFC_SHIFT)); 642 643 info->info.base = CONFIG_SYS_SDRAM_BASE; 644 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 645 clrsetbits_le32( 646 &info->regs->config, SDRAM_CONF_CAP_MASK, 647 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 648 } 649 650 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 651 { 652 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 653 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 654 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 655 (0x1 << MCR34_ODT_EXT_SHIFT); 656 657 /* init SDRAM-PHY only on real chip */ 658 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 659 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 660 &info->regs->power_ctrl); 661 udelay(5); 662 ast2600_sdramphy_kick_training(info); 663 udelay(500); 664 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 665 666 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 667 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 668 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 669 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 670 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 671 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 672 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 673 &info->regs->mode_setting_control); 674 675 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 676 677 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 678 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 679 &info->regs->refresh_timing); 680 #else 681 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 682 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 683 &info->regs->refresh_timing); 684 #endif 685 686 /* wait self-refresh idle */ 687 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 688 ; 689 690 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 691 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 692 SDRAM_REFRESH_ZQCS_EN | 693 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 694 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 695 &info->regs->refresh_timing); 696 #else 697 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 698 SDRAM_REFRESH_ZQCS_EN | 699 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 700 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 701 &info->regs->refresh_timing); 702 #endif 703 704 writel(power_ctrl, &info->regs->power_ctrl); 705 udelay(500); 706 707 #if defined(CONFIG_FPGA_ASPEED) 708 /* toggle Vref training */ 709 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 710 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 711 &info->regs->mode_setting_control); 712 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 713 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 714 &info->regs->mode_setting_control); 715 #endif 716 return 0; 717 } 718 719 static void ast2600_sdrammc_unlock(struct dram_info *info) 720 { 721 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 722 while (!readl(&info->regs->protection_key)) 723 ; 724 } 725 726 static void ast2600_sdrammc_lock(struct dram_info *info) 727 { 728 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 729 while (readl(&info->regs->protection_key)) 730 ; 731 } 732 733 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 734 { 735 int i; 736 737 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 738 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 739 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 740 ®s->arbitration_ctrl); 741 writel(0xFFBBFFF4, ®s->req_limit_mask); 742 743 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 744 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 745 746 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 747 748 /* FIXME: the sample code does NOT match the datasheet */ 749 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 750 751 writel(0, ®s->ecc_test_ctrl); 752 writel(0, ®s->test_addr); 753 writel(0, ®s->test_fail_dq_bit); 754 writel(0, ®s->test_init_val); 755 756 writel(0xFFFFFFFF, ®s->req_input_ctrl); 757 writel(0, ®s->req_high_pri_ctrl); 758 759 udelay(600); 760 761 #ifdef CONFIG_ASPEED_DDR4_DUALX8 762 writel(0x37, ®s->config); 763 #else 764 writel(0x17, ®s->config); 765 #endif 766 767 /* load controller setting */ 768 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 769 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 770 771 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 772 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 773 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 774 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 775 } 776 777 #ifdef CONFIG_ASPEED_ECC 778 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 779 { 780 struct ast2600_sdrammc_regs *regs = info->regs; 781 u32 reg; 782 783 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 784 reg = readl(®s->config) | 785 (SDRAM_CONF_ECC_EN | SDRAM_CONF_ECC_AUTO_SCRUBBING); 786 writel(reg, ®s->config); 787 788 writel(0, ®s->test_init_val); 789 writel(0, ®s->test_addr); 790 writel(0x221, ®s->ecc_test_ctrl); 791 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 792 ; 793 writel(0, ®s->ecc_test_ctrl); 794 writel(BIT(31), ®s->intr_ctrl); 795 writel(0, ®s->intr_ctrl); 796 797 /* reported size is updated */ 798 info->info.size -= (CONFIG_ASPEED_VIDEO_SIZE + CONFIG_ASPEED_CRT_SIZE) * 799 SDRAM_SIZE_1MB; 800 info->info.size = (info->info.size / 9) * 8; 801 printf("ECC enable, "); 802 } 803 #endif 804 805 static int ast2600_sdrammc_probe(struct udevice *dev) 806 { 807 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 808 struct ast2600_sdrammc_regs *regs = priv->regs; 809 struct udevice *clk_dev; 810 int ret; 811 volatile uint32_t reg; 812 813 /* find SCU base address from clock device */ 814 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 815 &clk_dev); 816 if (ret) { 817 debug("clock device not defined\n"); 818 return ret; 819 } 820 821 priv->scu = devfdt_get_addr_ptr(clk_dev); 822 if (IS_ERR(priv->scu)) { 823 debug("%s(): can't get SCU\n", __func__); 824 return PTR_ERR(priv->scu); 825 } 826 827 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 828 printf("already initialized, "); 829 ast2600_sdrammc_calc_size(priv); 830 #ifdef CONFIG_ASPEED_ECC 831 ast2600_sdrammc_ecc_enable(priv); 832 #endif 833 return 0; 834 } 835 836 #ifdef AST2600_SDRAMMC_MANUAL_CLK 837 reg = readl(priv->scu + AST_SCU_MPLL); 838 reg &= ~(BIT(24) | GENMASK(22, 0)); 839 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 840 writel(reg, priv->scu + AST_SCU_MPLL); 841 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 842 udelay(100); 843 reg &= ~(BIT(25) | BIT(23)); 844 writel(reg, priv->scu + AST_SCU_MPLL); 845 while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))); 846 #else 847 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 848 if (ret) { 849 debug("DDR:No CLK\n"); 850 return ret; 851 } 852 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 853 #endif 854 855 #if 0 856 /* FIXME: enable the following code if reset-driver is ready */ 857 struct reset_ctl reset_ctl; 858 ret = reset_get_by_index(dev, 0, &reset_ctl); 859 if (ret) { 860 debug("%s(): Failed to get reset signal\n", __func__); 861 return ret; 862 } 863 864 ret = reset_assert(&reset_ctl); 865 if (ret) { 866 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 867 return ret; 868 } 869 #endif 870 871 ast2600_sdrammc_unlock(priv); 872 ast2600_sdrammc_common_init(regs); 873 L_ast2600_sdramphy_train: 874 ast2600_sdrammc_init_ddr4(priv); 875 876 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 877 ast2600_sdrammc_search_read_window(priv); 878 #else 879 /* make sure DDR-PHY is ready before access */ 880 do { 881 reg = readl(priv->phy_status) & BIT(1); 882 } while(reg == 0); 883 #endif 884 885 if (0 != ast2600_sdramphy_check_status(priv)) { 886 printf("DDR4 PHY training fail, retrain\n"); 887 goto L_ast2600_sdramphy_train; 888 } 889 890 ast2600_sdrammc_calc_size(priv); 891 892 if (0 != ast2600_sdrammc_test(priv)) { 893 printf("%s: DDR4 init fail\n", __func__); 894 return -EINVAL; 895 } 896 897 #ifdef CONFIG_ASPEED_ECC 898 ast2600_sdrammc_ecc_enable(priv); 899 #endif 900 901 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 902 priv->scu + AST_SCU_HANDSHAKE); 903 904 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 905 ast2600_sdrammc_lock(priv); 906 return 0; 907 } 908 909 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 910 { 911 struct dram_info *priv = dev_get_priv(dev); 912 913 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 914 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 915 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 916 917 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 918 "clock-frequency", 0); 919 if (!priv->clock_rate) { 920 debug("DDR Clock Rate not defined\n"); 921 return -EINVAL; 922 } 923 924 return 0; 925 } 926 927 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 928 { 929 struct dram_info *priv = dev_get_priv(dev); 930 931 *info = priv->info; 932 933 return 0; 934 } 935 936 static struct ram_ops ast2600_sdrammc_ops = { 937 .get_info = ast2600_sdrammc_get_info, 938 }; 939 940 static const struct udevice_id ast2600_sdrammc_ids[] = { 941 { .compatible = "aspeed,ast2600-sdrammc" }, 942 { } 943 }; 944 945 U_BOOT_DRIVER(sdrammc_ast2600) = { 946 .name = "aspeed_ast2600_sdrammc", 947 .id = UCLASS_RAM, 948 .of_match = ast2600_sdrammc_ids, 949 .ops = &ast2600_sdrammc_ops, 950 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 951 .probe = ast2600_sdrammc_probe, 952 .priv_auto_alloc_size = sizeof(struct dram_info), 953 }; 954