1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 45 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 46 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 47 #define SCU_HANDSHAKE_MASK \ 48 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 49 SCU_P2A_BRIDGE_DISABLE) 50 51 /* bit-field of AST_SCU_MPLL */ 52 #define SCU_MPLL_RESET BIT(25) 53 #define SCU_MPLL_BYPASS BIT(24) 54 #define SCU_MPLL_TURN_OFF BIT(23) 55 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 56 57 #define SCU_MPLL_FREQ_400M 0x0008405F 58 #define SCU_MPLL_EXT_400M 0x0000002F 59 //#define SCU_MPLL_FREQ_400M 0x0038007F 60 //#define SCU_MPLL_EXT_400M 0x0000003F 61 #define SCU_MPLL_FREQ_333M 0x00488299 62 #define SCU_MPLL_EXT_333M 0x0000014C 63 #define SCU_MPLL_FREQ_200M 0x0078007F 64 #define SCU_MPLL_EXT_200M 0x0000003F 65 #define SCU_MPLL_FREQ_100M 0x0078003F 66 #define SCU_MPLL_EXT_100M 0x0000001F 67 /* MPLL configuration */ 68 #if defined(CONFIG_ASPEED_DDR4_1600) 69 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 70 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 71 #elif defined(CONFIG_ASPEED_DDR4_1333) 72 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 73 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 74 #elif defined(CONFIG_ASPEED_DDR4_800) 75 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 76 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 77 #elif defined(CONFIG_ASPEED_DDR4_400) 78 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 79 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 80 #else 81 #error "undefined DDR4 target rate\n" 82 #endif 83 84 /* AC timing and SDRAM mode registers */ 85 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 86 /* mode register settings for FPGA are fixed */ 87 #define DDR4_MR01_MODE 0x03010100 88 #define DDR4_MR23_MODE 0x00000000 89 #define DDR4_MR45_MODE 0x04C00000 90 #define DDR4_MR6_MODE 0x00000050 91 #define DDR4_TRFC_FPGA 0x17263434 92 93 /* FPGA need for an additional initialization procedure: search read window */ 94 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 95 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 96 #define SEARCH_RDWIN_PTRN_0 0x12345678 97 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 98 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 99 #else 100 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 101 #define DDR4_MR01_MODE 0x03010510 102 #define DDR4_MR23_MODE 0x00000000 103 #define DDR4_MR45_MODE 0x04000000 104 #define DDR4_MR6_MODE 0x00000400 105 #define DDR4_TRFC_1600 0x467299f1 106 #define DDR4_TRFC_1333 0x3a5f80c9 107 #define DDR4_TRFC_800 0x23394c78 108 #define DDR4_TRFC_400 0x111c263c 109 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 110 defined(CONFIG_ASPEED_PALLADIUM)" */ 111 112 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 113 #define DDR4_TRFC DDR4_TRFC_FPGA 114 #else 115 /* real chip setting */ 116 #if defined(CONFIG_ASPEED_DDR4_1600) 117 #define DDR4_TRFC DDR4_TRFC_1600 118 #define DDR4_PHY_TRAIN_TRFC 0xc30 119 #elif defined(CONFIG_ASPEED_DDR4_1333) 120 #define DDR4_TRFC DDR4_TRFC_1333 121 #define DDR4_PHY_TRAIN_TRFC 0xa25 122 #elif defined(CONFIG_ASPEED_DDR4_800) 123 #define DDR4_TRFC DDR4_TRFC_800 124 #define DDR4_PHY_TRAIN_TRFC 0x618 125 #elif defined(CONFIG_ASPEED_DDR4_400) 126 #define DDR4_TRFC DDR4_TRFC_400 127 #define DDR4_PHY_TRAIN_TRFC 0x30c 128 #else 129 #error "undefined tRFC setting" 130 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 131 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 132 defined(CONFIG_ASPEED_PALLADIUM)" */ 133 134 /* supported SDRAM size */ 135 #define SDRAM_SIZE_1KB (1024U) 136 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 137 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 138 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 139 140 141 DECLARE_GLOBAL_DATA_PTR; 142 143 /* 144 * Bandwidth configuration parameters for different SDRAM requests. 145 * These are hardcoded settings taken from Aspeed SDK. 146 */ 147 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 148 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 149 0x00000140 }; 150 151 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 152 0x88888888 }; 153 #else 154 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 155 0x00001240 }; 156 157 static const u32 ddr_max_grant_params[4] = { 0x44444444, 0x44444466, 0x44444444, 158 0x44444444 }; 159 #endif 160 161 struct dram_info { 162 struct ram_info info; 163 struct clk ddr_clk; 164 struct ast2600_sdrammc_regs *regs; 165 void __iomem *scu; 166 struct ast2600_ddr_phy *phy; 167 void __iomem *phy_setting; 168 void __iomem *phy_status; 169 ulong clock_rate; 170 }; 171 172 static void ast2600_sdramphy_kick_training(struct dram_info *info) 173 { 174 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 175 struct ast2600_sdrammc_regs *regs = info->regs; 176 u32 volatile data; 177 178 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 179 udelay(5); 180 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 181 udelay(1000); 182 183 while (1) { 184 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 185 if (~data) { 186 break; 187 } 188 } 189 190 #if 0 191 while (1) { 192 data = readl(0x1e6e0400) & BIT(1); 193 if (data) { 194 break; 195 } 196 } 197 #endif 198 #endif 199 } 200 201 /** 202 * @brief load DDR-PHY configurations table to the PHY registers 203 * @param[in] p_tbl - pointer to the configuration table 204 * @param[in] info - pointer to the DRAM info struct 205 * 206 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 207 * system: one is in the SDRAM MC (memory controller) which is used in run 208 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 209 * training. 210 */ 211 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 212 { 213 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 214 u32 reg_base = (u32)info->phy_setting; 215 u32 addr = p_tbl[0]; 216 u32 data; 217 int i = 1; 218 219 writel(0, &info->regs->phy_ctrl[0]); 220 udelay(10); 221 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 222 223 /* load PHY configuration table into PHY-setting registers */ 224 while (1) { 225 if (addr < reg_base) { 226 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 227 break; 228 } 229 data = p_tbl[i++]; 230 231 if (data == DDR_PHY_TBL_END) { 232 break; 233 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 234 addr = p_tbl[i++]; 235 } else { 236 writel(data, addr); 237 addr += 4; 238 } 239 } 240 241 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 242 data |= DDR4_PHY_TRAIN_TRFC; 243 writel(data, info->phy_setting + 0x84); 244 #endif 245 } 246 247 static int ast2600_sdramphy_check_status(struct dram_info *info) 248 { 249 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 250 u32 value, tmp; 251 u32 reg_base = (u32)info->phy_status; 252 int need_retrain = 0; 253 254 debug("\nSDRAM PHY training report:\n"); 255 /* training status */ 256 value = readl(reg_base + 0x00); 257 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 258 if (value & BIT(3)) { 259 debug("\tinitial PVT calibration fail\n"); 260 } 261 if (value & BIT(5)) { 262 debug("\truntime calibration fail\n"); 263 } 264 265 /* PU & PD */ 266 value = readl(reg_base + 0x30); 267 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 268 debug(" PU = 0x%02x\n", value & 0xff); 269 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 270 271 /* read eye window */ 272 value = readl(reg_base + 0x68); 273 if (0 == (value & GENMASK(7, 0))) { 274 need_retrain = 1; 275 } 276 277 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 278 debug(" rising edge of read data eye training pass window\n"); 279 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 280 debug(" B0:%d%%\n", tmp); 281 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 282 debug(" B1:%d%%\n", tmp); 283 284 value = readl(reg_base + 0xC8); 285 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 286 debug(" falling edge of read data eye training pass window\n"); 287 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 288 debug(" B0:%d%%\n", tmp); 289 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 290 debug(" B1:%d%%\n", tmp); 291 292 /* write eye window */ 293 value = readl(reg_base + 0x7c); 294 if (0 == (value & GENMASK(7, 0))) { 295 need_retrain = 1; 296 } 297 298 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 299 debug(" rising edge of write data eye training pass window\n"); 300 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 301 debug(" B0:%d%%\n", tmp); 302 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 303 debug(" B1:%d%%\n", tmp); 304 305 /* read Vref training result */ 306 value = readl(reg_base + 0x88); 307 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 308 debug(" read Vref training result\n"); 309 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 310 debug(" B0:%d%%\n", tmp); 311 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 312 debug(" B1:%d%%\n", tmp); 313 314 /* write Vref training result */ 315 value = readl(reg_base + 0x90); 316 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 317 #if 0 318 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 319 debug(" write Vref training result = %d%%\n", tmp); 320 #endif 321 322 /* gate train */ 323 value = readl(reg_base + 0x50); 324 if ((0 == (value & GENMASK(15, 0))) || 325 (0 == (value & GENMASK(31, 16)))) { 326 need_retrain = 1; 327 } 328 #if 0 329 if (((value >> 24) & 0xff) < 3) 330 need_retrain = 1; 331 else 332 need_retrain = 0; 333 #endif 334 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 335 #if 0 336 debug(" gate training pass window\n"); 337 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 338 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 339 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 340 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 341 #endif 342 343 return need_retrain; 344 #else 345 return 0; 346 #endif 347 } 348 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 349 #define MC_TEST_PATTERN_N 8 350 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 351 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 352 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 353 }; 354 355 #define TIMEOUT_DRAM 5000000 356 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 357 { 358 unsigned int data; 359 unsigned int timeout = 0; 360 struct ast2600_sdrammc_regs *regs = info->regs; 361 362 writel(0, ®s->ecc_test_ctrl); 363 if (mode == 0) 364 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 365 else 366 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 367 368 do { 369 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 370 371 if (data & BIT(13)) 372 return 0; 373 374 if (++timeout > TIMEOUT_DRAM) { 375 printf("Timeout!!\n"); 376 writel(0, ®s->ecc_test_ctrl); 377 378 return 0; 379 } 380 } while (!data); 381 382 writel(0, ®s->ecc_test_ctrl); 383 384 return 1; 385 } 386 387 int ast2600_sdrammc_cbr_test(struct dram_info *info) 388 { 389 struct ast2600_sdrammc_regs *regs = info->regs; 390 u32 i; 391 392 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 393 394 /* single */ 395 for (i = 0; i < 8; i++) { 396 if (!ast2600_sdrammc_dg_test(info, i, 0)) 397 return (0); 398 } 399 400 /* burst */ 401 for (i = 0; i < 8; i++) { 402 if (!ast2600_sdrammc_dg_test(info, i, i)) 403 return (0); 404 } 405 406 return(1); 407 } 408 409 static int ast2600_sdrammc_test(struct dram_info *info) 410 { 411 struct ast2600_sdrammc_regs *regs = info->regs; 412 413 u32 pass_cnt = 0; 414 u32 fail_cnt = 0; 415 u32 target_cnt = 2; 416 u32 test_cnt = 0; 417 u32 pattern; 418 u32 i = 0; 419 bool finish = false; 420 421 debug("sdram mc test:\n"); 422 while (finish == false) { 423 pattern = as2600_sdrammc_test_pattern[i++]; 424 i = i % MC_TEST_PATTERN_N; 425 debug(" pattern = %08X : ", pattern); 426 writel(pattern, ®s->test_init_val); 427 428 if (!ast2600_sdrammc_cbr_test(info)) { 429 debug("fail\n"); 430 fail_cnt++; 431 } else { 432 debug("pass\n"); 433 pass_cnt++; 434 } 435 436 if (++test_cnt == target_cnt) { 437 finish = true; 438 } 439 } 440 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 441 target_cnt); 442 return fail_cnt; 443 } 444 #endif 445 /** 446 * scu500[14:13] 447 * 2b'00: VGA memory size = 16MB 448 * 2b'01: VGA memory size = 16MB 449 * 2b'10: VGA memory size = 32MB 450 * 2b'11: VGA memory size = 64MB 451 * 452 * mcr04[3:2] 453 * 2b'00: VGA memory size = 8MB 454 * 2b'01: VGA memory size = 16MB 455 * 2b'10: VGA memory size = 32MB 456 * 2b'11: VGA memory size = 64MB 457 */ 458 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 459 { 460 u32 vga_hwconf; 461 size_t vga_mem_size_base = 8 * 1024 * 1024; 462 463 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 464 SCU_HWSTRAP_VGAMEM_MASK) >> 465 SCU_HWSTRAP_VGAMEM_SHIFT; 466 467 if (vga_hwconf == 0) { 468 vga_hwconf = 1; 469 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 470 info->scu + AST_SCU_HW_STRAP); 471 } 472 473 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 474 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 475 SDRAM_CONF_VGA_SIZE_MASK)); 476 477 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 478 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 479 return 0; 480 481 return vga_mem_size_base << vga_hwconf; 482 } 483 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 484 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 485 { 486 u32 data; 487 u32 scu_base = (u32)info->scu; 488 489 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 490 491 do { 492 data = readl(scu_base + AST_SCU_FPGA_STATUS); 493 } while (!(data & 0x100)); 494 495 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 496 } 497 498 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 499 { 500 u32 pll, pll_min, pll_max, dat1, offset; 501 u32 win = 0x03, gwin = 0, gwinsize = 0; 502 u32 phy_setting = (u32)info->phy_setting; 503 504 #ifdef CONFIG_ASPEED_PALLADIUM 505 writel(0xc, phy_setting + 0x0000); 506 return 1; 507 #endif 508 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 509 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 510 511 while (gwin == 0) { 512 while (!(win & 0x80)) { 513 debug("Window = 0x%X\n", win); 514 writel(win, phy_setting + 0x0000); 515 516 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 517 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 518 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 519 ast2600_sdrammc_fpga_set_pll(info); 520 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 521 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 522 } 523 524 pll_min = 0xfff; 525 pll_max = 0x0; 526 pll = 0; 527 while (pll_max > 0 || pll < 256) { 528 ast2600_sdrammc_fpga_set_pll(info); 529 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 530 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 531 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 532 if (pll_min > pll) 533 pll_min = pll; 534 535 if (pll_max < pll) 536 pll_max = pll; 537 538 debug("%3d_(%3d:%3d)\n", pll, pll_min, 539 pll_max); 540 } else if (pll_max > 0) { 541 pll_min = pll_max - pll_min; 542 if (gwinsize < pll_min) { 543 gwin = win; 544 gwinsize = pll_min; 545 } 546 break; 547 } 548 pll += 1; 549 } 550 551 if (gwin != 0 && pll_max == 0) 552 break; 553 554 win = win << 1; 555 } 556 if (gwin == 0) 557 win = 0x7; 558 } 559 debug("Set PLL Read Gating Window = %x\n", gwin); 560 writel(gwin, phy_setting + 0x0000); 561 562 debug("PLL Read Window training\n"); 563 pll_min = 0xfff; 564 pll_max = 0x0; 565 566 debug("Search Window Start\n"); 567 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 568 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 569 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 570 ast2600_sdrammc_fpga_set_pll(info); 571 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 572 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 573 } 574 575 debug("Search Window Margin\n"); 576 pll = 0; 577 while (pll_max > 0 || pll < 256) { 578 ast2600_sdrammc_fpga_set_pll(info); 579 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 580 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 581 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 582 if (pll_min > pll) 583 pll_min = pll; 584 585 if (pll_max < pll) 586 pll_max = pll; 587 588 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 589 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 590 break; 591 } else if (pll_max > 0) { 592 pll_min = 0xfff; 593 pll_max = 0x0; 594 } 595 pll += 1; 596 } 597 if (pll_min < pll_max) { 598 debug("PLL Read window = %d\n", (pll_max - pll_min)); 599 offset = (pll_max - pll_min) >> 1; 600 pll_min = 0xfff; 601 pll = 0; 602 while (pll < (pll_min + offset)) { 603 ast2600_sdrammc_fpga_set_pll(info); 604 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 605 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 606 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 607 if (pll_min > pll) { 608 pll_min = pll; 609 } 610 debug("%d\n", pll); 611 } else { 612 pll_min = 0xfff; 613 pll_max = 0x0; 614 } 615 pll += 1; 616 } 617 return (1); 618 } else { 619 debug("PLL Read window training fail\n"); 620 return 0; 621 } 622 } 623 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 624 defined(CONFIG_ASPEED_PALLADIUM)" */ 625 626 /* 627 * Find out RAM size and save it in dram_info 628 * 629 * The procedure is taken from Aspeed SDK 630 */ 631 static void ast2600_sdrammc_calc_size(struct dram_info *info) 632 { 633 /* The controller supports 256/512/1024/2048 MB ram */ 634 size_t ram_size = SDRAM_MIN_SIZE; 635 const int write_test_offset = 0x100000; 636 u32 test_pattern = 0xdeadbeef; 637 u32 cap_param = SDRAM_CONF_CAP_2048M; 638 u32 refresh_timing_param = DDR4_TRFC; 639 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 640 641 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 642 ram_size >>= 1) { 643 writel(test_pattern, write_addr_base + (ram_size >> 1)); 644 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 645 } 646 647 /* One last write to overwrite all wrapped values */ 648 writel(test_pattern, write_addr_base); 649 650 /* Reset the pattern and see which value was really written */ 651 test_pattern = 0xdeadbeef; 652 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 653 ram_size >>= 1) { 654 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 655 break; 656 657 --cap_param; 658 refresh_timing_param >>= 8; 659 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 660 } 661 662 clrsetbits_le32(&info->regs->ac_timing[1], 663 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 664 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 665 << SDRAM_AC_TRFC_SHIFT)); 666 667 info->info.base = CONFIG_SYS_SDRAM_BASE; 668 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 669 670 clrsetbits_le32( 671 &info->regs->config, SDRAM_CONF_CAP_MASK, 672 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 673 } 674 675 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 676 { 677 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 678 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 679 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 680 (0x1 << MCR34_ODT_EXT_SHIFT); 681 682 /* init SDRAM-PHY only on real chip */ 683 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 684 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 685 &info->regs->power_ctrl); 686 udelay(5); 687 ast2600_sdramphy_kick_training(info); 688 udelay(500); 689 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 690 691 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 692 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 693 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 694 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 695 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 696 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 697 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 698 &info->regs->mode_setting_control); 699 700 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 701 702 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 703 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 704 &info->regs->refresh_timing); 705 #else 706 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 707 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 708 &info->regs->refresh_timing); 709 #endif 710 711 /* wait self-refresh idle */ 712 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 713 ; 714 715 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 716 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 717 SDRAM_REFRESH_ZQCS_EN | 718 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 719 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 720 &info->regs->refresh_timing); 721 #else 722 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 723 SDRAM_REFRESH_ZQCS_EN | 724 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 725 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 726 &info->regs->refresh_timing); 727 #endif 728 729 writel(power_ctrl, &info->regs->power_ctrl); 730 udelay(500); 731 732 #if defined(CONFIG_FPGA_ASPEED) 733 /* toggle Vref training */ 734 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 735 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 736 &info->regs->mode_setting_control); 737 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 738 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 739 &info->regs->mode_setting_control); 740 #endif 741 return 0; 742 } 743 744 static void ast2600_sdrammc_unlock(struct dram_info *info) 745 { 746 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 747 while (!readl(&info->regs->protection_key)) 748 ; 749 } 750 751 static void ast2600_sdrammc_lock(struct dram_info *info) 752 { 753 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 754 while (readl(&info->regs->protection_key)) 755 ; 756 } 757 758 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 759 { 760 int i; 761 762 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 763 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 764 writel(0x101010, ®s->arbitration_ctrl); 765 writel(0x0FFFFCFC, ®s->req_limit_mask); 766 767 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 768 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 769 770 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 771 772 /* FIXME: the sample code does NOT match the datasheet */ 773 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 774 775 writel(0, ®s->ecc_test_ctrl); 776 writel(0x80000001, ®s->test_addr); 777 writel(0, ®s->test_fail_dq_bit); 778 writel(0, ®s->test_init_val); 779 780 writel(0xFFFFFFFF, ®s->req_input_ctrl); 781 writel(0x0, ®s->req_high_pri_ctrl); 782 783 udelay(600); 784 785 #ifdef CONFIG_ASPEED_DDR4_DUALX8 786 writel(0x37, ®s->config); 787 #else 788 writel(0x17, ®s->config); 789 #endif 790 791 /* load controller setting */ 792 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 793 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 794 795 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 796 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 797 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 798 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 799 } 800 /* 801 * Update size info according to the ECC HW setting 802 * 803 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 804 * don't need to calculate the ECC size again but read from MCR04 and derive the 805 * size from its value. 806 */ 807 static void ast2600_sdrammc_update_size(struct dram_info *info) 808 { 809 struct ast2600_sdrammc_regs *regs = info->regs; 810 size_t hw_size; 811 size_t ram_size = SDRAM_MAX_SIZE; 812 u32 cap_param; 813 814 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 815 switch (cap_param) 816 { 817 case SDRAM_CONF_CAP_2048M: 818 ram_size = 2048 * SDRAM_SIZE_1MB; 819 break; 820 case SDRAM_CONF_CAP_1024M: 821 ram_size = 1024 * SDRAM_SIZE_1MB; 822 break; 823 case SDRAM_CONF_CAP_512M: 824 ram_size = 512 * SDRAM_SIZE_1MB; 825 break; 826 case SDRAM_CONF_CAP_256M: 827 ram_size = 256 * SDRAM_SIZE_1MB; 828 break; 829 } 830 831 info->info.base = CONFIG_SYS_SDRAM_BASE; 832 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 833 834 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 835 return; 836 837 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 838 hw_size += (1 << 20); 839 840 info->info.size = hw_size; 841 } 842 #ifdef CONFIG_ASPEED_ECC 843 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 844 { 845 struct ast2600_sdrammc_regs *regs = info->regs; 846 size_t conf_size; 847 u32 reg; 848 849 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 850 if (conf_size > info->info.size) { 851 printf("warning: ECC configured %dMB but actual size is %dMB\n", 852 CONFIG_ASPEED_ECC_SIZE, 853 info->info.size / SDRAM_SIZE_1MB); 854 conf_size = info->info.size; 855 } else if (conf_size == 0) { 856 conf_size = info->info.size; 857 } 858 859 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 860 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 861 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 862 writel(reg, ®s->config); 863 864 writel(0, ®s->test_init_val); 865 writel(0x80000001, ®s->test_addr); 866 writel(0x221, ®s->ecc_test_ctrl); 867 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 868 ; 869 writel(0, ®s->ecc_test_ctrl); 870 writel(BIT(31), ®s->intr_ctrl); 871 writel(0, ®s->intr_ctrl); 872 } 873 #endif 874 875 static int ast2600_sdrammc_probe(struct udevice *dev) 876 { 877 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 878 struct ast2600_sdrammc_regs *regs = priv->regs; 879 struct udevice *clk_dev; 880 int ret; 881 volatile uint32_t reg; 882 883 /* find SCU base address from clock device */ 884 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 885 &clk_dev); 886 if (ret) { 887 debug("clock device not defined\n"); 888 return ret; 889 } 890 891 priv->scu = devfdt_get_addr_ptr(clk_dev); 892 if (IS_ERR(priv->scu)) { 893 debug("%s(): can't get SCU\n", __func__); 894 return PTR_ERR(priv->scu); 895 } 896 897 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 898 printf("already initialized, "); 899 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 900 ast2600_sdrammc_update_size(priv); 901 return 0; 902 } 903 904 #ifdef AST2600_SDRAMMC_MANUAL_CLK 905 reg = readl(priv->scu + AST_SCU_MPLL); 906 reg &= ~(BIT(24) | GENMASK(22, 0)); 907 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 908 writel(reg, priv->scu + AST_SCU_MPLL); 909 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 910 udelay(100); 911 reg &= ~(BIT(25) | BIT(23)); 912 writel(reg, priv->scu + AST_SCU_MPLL); 913 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 914 ; 915 #else 916 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 917 if (ret) { 918 debug("DDR:No CLK\n"); 919 return ret; 920 } 921 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 922 #endif 923 924 #if 0 925 /* FIXME: enable the following code if reset-driver is ready */ 926 struct reset_ctl reset_ctl; 927 ret = reset_get_by_index(dev, 0, &reset_ctl); 928 if (ret) { 929 debug("%s(): Failed to get reset signal\n", __func__); 930 return ret; 931 } 932 933 ret = reset_assert(&reset_ctl); 934 if (ret) { 935 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 936 return ret; 937 } 938 #endif 939 940 ast2600_sdrammc_unlock(priv); 941 ast2600_sdrammc_common_init(regs); 942 L_ast2600_sdramphy_train: 943 ast2600_sdrammc_init_ddr4(priv); 944 945 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 946 ast2600_sdrammc_search_read_window(priv); 947 #else 948 /* make sure DDR-PHY is ready before access */ 949 do { 950 reg = readl(priv->phy_status) & BIT(1); 951 } while (reg == 0); 952 #endif 953 954 if (0 != ast2600_sdramphy_check_status(priv)) { 955 printf("DDR4 PHY training fail, retrain\n"); 956 goto L_ast2600_sdramphy_train; 957 } 958 959 ast2600_sdrammc_calc_size(priv); 960 961 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 962 if (0 != ast2600_sdrammc_test(priv)) { 963 printf("%s: DDR4 init fail\n", __func__); 964 return -EINVAL; 965 } 966 #endif 967 968 #ifdef CONFIG_ASPEED_ECC 969 ast2600_sdrammc_ecc_enable(priv); 970 #endif 971 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 972 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 973 ast2600_sdrammc_lock(priv); 974 return 0; 975 } 976 977 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 978 { 979 struct dram_info *priv = dev_get_priv(dev); 980 981 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 982 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 983 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 984 985 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 986 "clock-frequency", 0); 987 if (!priv->clock_rate) { 988 debug("DDR Clock Rate not defined\n"); 989 return -EINVAL; 990 } 991 992 return 0; 993 } 994 995 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 996 { 997 struct dram_info *priv = dev_get_priv(dev); 998 999 *info = priv->info; 1000 1001 return 0; 1002 } 1003 1004 static struct ram_ops ast2600_sdrammc_ops = { 1005 .get_info = ast2600_sdrammc_get_info, 1006 }; 1007 1008 static const struct udevice_id ast2600_sdrammc_ids[] = { 1009 { .compatible = "aspeed,ast2600-sdrammc" }, 1010 { } 1011 }; 1012 1013 U_BOOT_DRIVER(sdrammc_ast2600) = { 1014 .name = "aspeed_ast2600_sdrammc", 1015 .id = UCLASS_RAM, 1016 .of_match = ast2600_sdrammc_ids, 1017 .ops = &ast2600_sdrammc_ops, 1018 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1019 .probe = ast2600_sdrammc_probe, 1020 .priv_auto_alloc_size = sizeof(struct dram_info), 1021 }; 1022