1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 34 35 /* bit-field of AST_SCU_HW_STRAP */ 36 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 37 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 38 39 40 /* bit-field of AST_SCU_HANDSHAKE */ 41 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 42 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 43 44 /* bit-field of AST_SCU_MPLL */ 45 #define SCU_MPLL_RESET BIT(25) 46 #define SCU_MPLL_BYPASS BIT(24) 47 #define SCU_MPLL_TURN_OFF BIT(23) 48 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 49 50 #define SCU_MPLL_FREQ_400M 0x0008405F 51 #define SCU_MPLL_EXT_400M 0x00000031 52 //#define SCU_MPLL_FREQ_400M 0x0038007F 53 //#define SCU_MPLL_EXT_400M 0x0000003F 54 #define SCU_MPLL_FREQ_333M 0x00488299 55 #define SCU_MPLL_EXT_333M 0x0000014C 56 #define SCU_MPLL_FREQ_200M 0x0078007F 57 #define SCU_MPLL_EXT_200M 0x0000003F 58 #define SCU_MPLL_FREQ_100M 0x0078003F 59 #define SCU_MPLL_EXT_100M 0x0000001F 60 /* MPLL configuration */ 61 #if defined(CONFIG_ASPEED_DDR4_1600) 62 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 63 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 64 #elif defined(CONFIG_ASPEED_DDR4_1333) 65 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 66 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 67 #elif defined(CONFIG_ASPEED_DDR4_800) 68 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 69 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 70 #elif defined(CONFIG_ASPEED_DDR4_400) 71 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 72 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 73 #else 74 #error "undefined DDR4 target rate\n" 75 #endif 76 77 /* AC timing and SDRAM mode registers */ 78 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 79 /* mode register settings for FPGA are fixed */ 80 #define DDR4_MR01_MODE 0x03010100 81 #define DDR4_MR23_MODE 0x00000000 82 #define DDR4_MR45_MODE 0x04C00000 83 #define DDR4_MR6_MODE 0x00000050 84 #define DDR4_TRFC_FPGA 0x17263434 85 86 /* FPGA need for an additional initialization procedure: search read window */ 87 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 88 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 89 #define SEARCH_RDWIN_PTRN_0 0x12345678 90 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 91 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 92 #else 93 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 94 #define DDR4_MR01_MODE 0x03010510 95 #define DDR4_MR23_MODE 0x00000000 96 #define DDR4_MR45_MODE 0x04000000 97 #define DDR4_MR6_MODE 0x00000400 98 #define DDR4_TRFC_1600 0x467299f1 99 #define DDR4_TRFC_1333 0x3a5f80c9 100 #define DDR4_TRFC_800 0x23394c78 101 #define DDR4_TRFC_400 0x111c263c 102 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 103 defined(CONFIG_ASPEED_PALLADIUM)" */ 104 105 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 106 #define DDR4_TRFC DDR4_TRFC_FPGA 107 #else 108 /* real chip setting */ 109 #if defined(CONFIG_ASPEED_DDR4_1600) 110 #define DDR4_TRFC DDR4_TRFC_1600 111 #define DDR4_PHY_TRAIN_TRFC 0xc30 112 #elif defined(CONFIG_ASPEED_DDR4_1333) 113 #define DDR4_TRFC DDR4_TRFC_1333 114 #define DDR4_PHY_TRAIN_TRFC 0xa25 115 #elif defined(CONFIG_ASPEED_DDR4_800) 116 #define DDR4_TRFC DDR4_TRFC_800 117 #define DDR4_PHY_TRAIN_TRFC 0x618 118 #elif defined(CONFIG_ASPEED_DDR4_400) 119 #define DDR4_TRFC DDR4_TRFC_400 120 #define DDR4_PHY_TRAIN_TRFC 0x30c 121 #else 122 #error "undefined tRFC setting" 123 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 124 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 125 defined(CONFIG_ASPEED_PALLADIUM)" */ 126 127 /* supported SDRAM size */ 128 #define SDRAM_SIZE_1KB (1024U) 129 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 130 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 131 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 132 133 134 DECLARE_GLOBAL_DATA_PTR; 135 136 /* 137 * Bandwidth configuration parameters for different SDRAM requests. 138 * These are hardcoded settings taken from Aspeed SDK. 139 */ 140 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 141 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 142 0x00000140}; 143 144 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 145 0x88888888}; 146 #else 147 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 148 0x00001240}; 149 150 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 151 0x44444444}; 152 #endif 153 154 struct dram_info { 155 struct ram_info info; 156 struct clk ddr_clk; 157 struct ast2600_sdrammc_regs *regs; 158 void __iomem *scu; 159 struct ast2600_ddr_phy *phy; 160 void __iomem *phy_setting; 161 void __iomem *phy_status; 162 ulong clock_rate; 163 }; 164 165 static void ast2600_sdramphy_kick_training(struct dram_info *info) 166 { 167 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 168 struct ast2600_sdrammc_regs *regs = info->regs; 169 u32 volatile data; 170 171 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 172 udelay(5); 173 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 174 udelay(1000); 175 176 while (1) { 177 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 178 if (~data) { 179 break; 180 } 181 } 182 183 #if 0 184 while (1) { 185 data = readl(0x1e6e0400) & BIT(1); 186 if (data) { 187 break; 188 } 189 } 190 #endif 191 #endif 192 } 193 194 /** 195 * @brief load DDR-PHY configurations table to the PHY registers 196 * @param[in] p_tbl - pointer to the configuration table 197 * @param[in] info - pointer to the DRAM info struct 198 * 199 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 200 * system: one is in the SDRAM MC (memory controller) which is used in run 201 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 202 * training. 203 */ 204 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 205 { 206 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 207 u32 reg_base = (u32)info->phy_setting; 208 u32 addr = p_tbl[0]; 209 u32 data; 210 int i = 1; 211 212 writel(0, &info->regs->phy_ctrl[0]); 213 udelay(10); 214 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 215 216 debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, 217 addr); 218 219 /* load PHY configuration table into PHY-setting registers */ 220 while (1) { 221 if (addr < reg_base) { 222 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 223 break; 224 } 225 data = p_tbl[i++]; 226 227 if (DDR_PHY_TBL_END == data) { 228 break; 229 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 230 addr = p_tbl[i++]; 231 } else { 232 writel(data, addr); 233 addr += 4; 234 } 235 } 236 237 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 238 data |= DDR4_PHY_TRAIN_TRFC; 239 writel(data, info->phy_setting + 0x84); 240 #endif 241 } 242 243 static int ast2600_sdramphy_check_status(struct dram_info *info) 244 { 245 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 246 u32 value, tmp; 247 u32 reg_base = (u32)info->phy_status; 248 int need_retrain = 0; 249 250 debug("\nSDRAM PHY training report:\n"); 251 /* training status */ 252 value = readl(reg_base + 0x00); 253 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 254 if (value & BIT(3)) { 255 debug("\tinitial PVT calibration fail\n"); 256 } 257 if (value & BIT(5)) { 258 debug("\truntime calibration fail\n"); 259 } 260 261 /* PU & PD */ 262 value = readl(reg_base + 0x30); 263 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 264 debug(" PU = 0x%02x\n", value & 0xff); 265 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 266 267 /* read eye window */ 268 value = readl(reg_base + 0x68); 269 if (0 == (value & GENMASK(7, 0))) { 270 need_retrain = 1; 271 } 272 273 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 274 debug(" rising edge of read data eye training pass window\n"); 275 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 276 debug(" B0:%d%%\n", tmp); 277 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 278 debug(" B1:%d%%\n", tmp); 279 280 value = readl(reg_base + 0xC8); 281 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 282 debug(" falling edge of read data eye training pass window\n"); 283 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 284 debug(" B0:%d%%\n", tmp); 285 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 286 debug(" B1:%d%%\n", tmp); 287 288 /* write eye window */ 289 value = readl(reg_base + 0x7c); 290 if (0 == (value & GENMASK(7, 0))) { 291 need_retrain = 1; 292 } 293 294 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 295 debug(" rising edge of write data eye training pass window\n"); 296 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 297 debug(" B0:%d%%\n", tmp); 298 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 299 debug(" B1:%d%%\n", tmp); 300 301 /* read Vref training result */ 302 value = readl(reg_base + 0x88); 303 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 304 debug(" read Vref training result\n"); 305 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 306 debug(" B0:%d%%\n", tmp); 307 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 308 debug(" B1:%d%%\n", tmp); 309 310 /* write Vref training result */ 311 value = readl(reg_base + 0x90); 312 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 313 #if 0 314 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 315 debug(" write Vref training result = %d%%\n", tmp); 316 #endif 317 318 /* gate train */ 319 value = readl(reg_base + 0x50); 320 if ((0 == (value & GENMASK(15, 0))) || 321 (0 == (value & GENMASK(31, 16)))) { 322 need_retrain = 1; 323 } 324 #if 0 325 if (((value >> 24) & 0xff) < 3) 326 need_retrain = 1; 327 else 328 need_retrain = 0; 329 #endif 330 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 331 #if 0 332 debug(" gate training pass window\n"); 333 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 334 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 335 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 336 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 337 #endif 338 339 return need_retrain; 340 #else 341 return 0; 342 #endif 343 } 344 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 345 #define MC_TEST_PATTERN_N 8 346 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 347 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 348 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 349 350 #define TIMEOUT_DRAM 5000000 351 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 352 { 353 unsigned int data; 354 unsigned int timeout = 0; 355 struct ast2600_sdrammc_regs *regs = info->regs; 356 357 writel(0, ®s->ecc_test_ctrl); 358 if (mode == 0) { 359 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 360 } else { 361 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 362 } 363 364 do { 365 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 366 367 if (data & BIT(13)) 368 return (0); 369 370 if (++timeout > TIMEOUT_DRAM) { 371 printf("Timeout!!\n"); 372 writel(0, ®s->ecc_test_ctrl); 373 374 return (0); 375 } 376 } while (!data); 377 378 writel(0, ®s->ecc_test_ctrl); 379 380 return (1); 381 } 382 383 int ast2600_sdrammc_cbr_test(struct dram_info *info) 384 { 385 struct ast2600_sdrammc_regs *regs = info->regs; 386 u32 i; 387 388 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 389 390 /* single */ 391 for (i=0; i<8; i++) { 392 if(!ast2600_sdrammc_dg_test(info, i, 0)) return(0); 393 } 394 395 /* burst */ 396 for (i=0; i<8; i++) { 397 if(!ast2600_sdrammc_dg_test(info, i, i)) return(0); 398 } 399 400 return(1); 401 } 402 403 static int ast2600_sdrammc_test(struct dram_info *info) 404 { 405 struct ast2600_sdrammc_regs *regs = info->regs; 406 407 u32 pass_cnt = 0; 408 u32 fail_cnt = 0; 409 u32 target_cnt = 2; 410 u32 test_cnt = 0; 411 u32 pattern; 412 u32 i = 0; 413 bool finish = false; 414 415 debug("sdram mc test:\n"); 416 while (finish == false) { 417 pattern = as2600_sdrammc_test_pattern[i++]; 418 i = i % MC_TEST_PATTERN_N; 419 debug(" pattern = %08X : ",pattern); 420 writel(pattern, regs->test_init_val); 421 422 if (!ast2600_sdrammc_cbr_test(info)) { 423 debug("fail\n"); 424 fail_cnt++; 425 } else { 426 debug("pass\n"); 427 pass_cnt++; 428 } 429 430 if (++test_cnt == target_cnt) { 431 finish = true; 432 } 433 } 434 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 435 target_cnt); 436 return fail_cnt; 437 } 438 #endif 439 /** 440 * scu500[14:13] 441 * 2b'00: VGA memory size = 16MB 442 * 2b'01: VGA memory size = 16MB 443 * 2b'10: VGA memory size = 32MB 444 * 2b'11: VGA memory size = 64MB 445 * 446 * mcr04[3:2] 447 * 2b'00: VGA memory size = 8MB 448 * 2b'01: VGA memory size = 16MB 449 * 2b'10: VGA memory size = 32MB 450 * 2b'11: VGA memory size = 64MB 451 */ 452 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 453 { 454 u32 vga_hwconf; 455 size_t vga_mem_size_base = 8 * 1024 * 1024; 456 457 vga_hwconf = 458 (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >> 459 SCU_HWSTRAP_VGAMEM_SHIFT; 460 461 vga_hwconf = (vga_hwconf == 0) ? 1 : vga_hwconf; 462 463 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 464 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 465 SDRAM_CONF_VGA_SIZE_MASK)); 466 467 return vga_mem_size_base << vga_hwconf; 468 } 469 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 470 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 471 { 472 u32 data; 473 u32 scu_base = (u32)info->scu; 474 475 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 476 477 do { 478 data = readl(scu_base + AST_SCU_FPGA_STATUS); 479 } while (!(data & 0x100)); 480 481 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 482 } 483 484 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 485 { 486 u32 pll, pll_min, pll_max, dat1, offset; 487 u32 win = 0x03, gwin = 0, gwinsize = 0; 488 u32 phy_setting = (u32)info->phy_setting; 489 490 #ifdef CONFIG_ASPEED_PALLADIUM 491 writel(0xc, phy_setting + 0x0000); 492 return (1); 493 #endif 494 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 495 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 496 497 while (gwin == 0) { 498 while (!(win & 0x80)) { 499 debug("Window = 0x%X\n", win); 500 writel(win, phy_setting + 0x0000); 501 502 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 503 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 504 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 505 ast2600_sdrammc_fpga_set_pll(info); 506 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 507 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 508 } 509 510 pll_min = 0xfff; 511 pll_max = 0x0; 512 pll = 0; 513 while (pll_max > 0 || pll < 256) { 514 ast2600_sdrammc_fpga_set_pll(info); 515 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 516 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 517 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 518 if (pll_min > pll) { 519 pll_min = pll; 520 } 521 if (pll_max < pll) { 522 pll_max = pll; 523 } 524 debug("%3d_(%3d:%3d)\n", pll, pll_min, 525 pll_max); 526 } else if (pll_max > 0) { 527 pll_min = pll_max - pll_min; 528 if (gwinsize < pll_min) { 529 gwin = win; 530 gwinsize = pll_min; 531 } 532 break; 533 } 534 pll += 1; 535 } 536 537 if (gwin != 0 && pll_max == 0) { 538 break; 539 } 540 win = win << 1; 541 } 542 if (gwin == 0) { 543 win = 0x7; 544 } 545 } 546 debug("Set PLL Read Gating Window = %x\n", gwin); 547 writel(gwin, phy_setting + 0x0000); 548 549 debug("PLL Read Window training\n"); 550 pll_min = 0xfff; 551 pll_max = 0x0; 552 553 debug("Search Window Start\n"); 554 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 555 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 556 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 557 ast2600_sdrammc_fpga_set_pll(info); 558 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 559 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 560 } 561 562 debug("Search Window Margin\n"); 563 pll = 0; 564 while (pll_max > 0 || pll < 256) { 565 ast2600_sdrammc_fpga_set_pll(info); 566 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 567 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 568 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 569 if (pll_min > pll) { 570 pll_min = pll; 571 } 572 if (pll_max < pll) { 573 pll_max = pll; 574 } 575 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 576 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 577 break; 578 } else if (pll_max > 0) { 579 pll_min = 0xfff; 580 pll_max = 0x0; 581 } 582 pll += 1; 583 } 584 if (pll_min < pll_max) { 585 debug("PLL Read window = %d\n", (pll_max - pll_min)); 586 offset = (pll_max - pll_min) >> 1; 587 pll_min = 0xfff; 588 pll = 0; 589 while (pll < (pll_min + offset)) { 590 ast2600_sdrammc_fpga_set_pll(info); 591 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 592 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 593 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 594 if (pll_min > pll) { 595 pll_min = pll; 596 } 597 debug("%d\n", pll); 598 } else { 599 pll_min = 0xfff; 600 pll_max = 0x0; 601 } 602 pll += 1; 603 } 604 return (1); 605 } else { 606 debug("PLL Read window training fail\n"); 607 return (0); 608 } 609 } 610 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 611 defined(CONFIG_ASPEED_PALLADIUM)" */ 612 613 /* 614 * Find out RAM size and save it in dram_info 615 * 616 * The procedure is taken from Aspeed SDK 617 */ 618 static void ast2600_sdrammc_calc_size(struct dram_info *info) 619 { 620 /* The controller supports 256/512/1024/2048 MB ram */ 621 size_t ram_size = SDRAM_MIN_SIZE; 622 const int write_test_offset = 0x100000; 623 u32 test_pattern = 0xdeadbeef; 624 u32 cap_param = SDRAM_CONF_CAP_2048M; 625 u32 refresh_timing_param = DDR4_TRFC; 626 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 627 628 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 629 ram_size >>= 1) { 630 writel(test_pattern, write_addr_base + (ram_size >> 1)); 631 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 632 } 633 634 /* One last write to overwrite all wrapped values */ 635 writel(test_pattern, write_addr_base); 636 637 /* Reset the pattern and see which value was really written */ 638 test_pattern = 0xdeadbeef; 639 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 640 ram_size >>= 1) { 641 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 642 break; 643 644 --cap_param; 645 refresh_timing_param >>= 8; 646 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 647 } 648 649 clrsetbits_le32(&info->regs->ac_timing[1], 650 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 651 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 652 << SDRAM_AC_TRFC_SHIFT)); 653 654 info->info.base = CONFIG_SYS_SDRAM_BASE; 655 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 656 clrsetbits_le32( 657 &info->regs->config, SDRAM_CONF_CAP_MASK, 658 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 659 } 660 661 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 662 { 663 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 664 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 665 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 666 (0x1 << MCR34_ODT_EXT_SHIFT); 667 668 /* init SDRAM-PHY only on real chip */ 669 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 670 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 671 &info->regs->power_ctrl); 672 udelay(5); 673 ast2600_sdramphy_kick_training(info); 674 udelay(500); 675 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 676 677 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 678 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 679 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 680 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 681 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 682 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 683 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 684 &info->regs->mode_setting_control); 685 686 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 687 688 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 689 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 690 &info->regs->refresh_timing); 691 #else 692 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 693 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 694 &info->regs->refresh_timing); 695 #endif 696 697 /* wait self-refresh idle */ 698 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 699 ; 700 701 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 702 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 703 SDRAM_REFRESH_ZQCS_EN | 704 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 705 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 706 &info->regs->refresh_timing); 707 #else 708 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 709 SDRAM_REFRESH_ZQCS_EN | 710 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 711 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 712 &info->regs->refresh_timing); 713 #endif 714 715 writel(power_ctrl, &info->regs->power_ctrl); 716 udelay(500); 717 718 #if defined(CONFIG_FPGA_ASPEED) 719 /* toggle Vref training */ 720 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 721 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 722 &info->regs->mode_setting_control); 723 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 724 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 725 &info->regs->mode_setting_control); 726 #endif 727 return 0; 728 } 729 730 static void ast2600_sdrammc_unlock(struct dram_info *info) 731 { 732 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 733 while (!readl(&info->regs->protection_key)) 734 ; 735 } 736 737 static void ast2600_sdrammc_lock(struct dram_info *info) 738 { 739 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 740 while (readl(&info->regs->protection_key)) 741 ; 742 } 743 744 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 745 { 746 int i; 747 748 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 749 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 750 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 751 ®s->arbitration_ctrl); 752 writel(0xFFBBFFF4, ®s->req_limit_mask); 753 754 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 755 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 756 757 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 758 759 /* FIXME: the sample code does NOT match the datasheet */ 760 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 761 762 writel(0, ®s->ecc_test_ctrl); 763 writel(0, ®s->test_addr); 764 writel(0, ®s->test_fail_dq_bit); 765 writel(0, ®s->test_init_val); 766 767 writel(0xFFFFFFFF, ®s->req_input_ctrl); 768 writel(0, ®s->req_high_pri_ctrl); 769 770 udelay(600); 771 772 #ifdef CONFIG_ASPEED_DDR4_DUALX8 773 writel(0x37, ®s->config); 774 #else 775 writel(0x17, ®s->config); 776 #endif 777 778 /* load controller setting */ 779 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 780 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 781 782 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 783 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 784 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 785 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 786 } 787 788 #ifdef CONFIG_ASPEED_ECC 789 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 790 { 791 struct ast2600_sdrammc_regs *regs = info->regs; 792 size_t conf_size; 793 u32 reg; 794 795 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 796 if (conf_size > info->info.size) { 797 printf("warning: ECC configured %dMB but actual size is %dMB\n", 798 CONFIG_ASPEED_ECC_SIZE, 799 info->info.size / SDRAM_SIZE_1MB); 800 conf_size = info->info.size; 801 } else if (conf_size == 0) { 802 conf_size = info->info.size; 803 } 804 805 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 806 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 807 reg = readl(®s->config) | 808 (SDRAM_CONF_ECC_EN | SDRAM_CONF_ECC_AUTO_SCRUBBING); 809 writel(reg, ®s->config); 810 811 writel(0, ®s->test_init_val); 812 writel(0, ®s->test_addr); 813 writel(0x221, ®s->ecc_test_ctrl); 814 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 815 ; 816 writel(0, ®s->ecc_test_ctrl); 817 writel(BIT(31), ®s->intr_ctrl); 818 writel(0, ®s->intr_ctrl); 819 printf("ECC enable, "); 820 } 821 #endif 822 823 static int ast2600_sdrammc_probe(struct udevice *dev) 824 { 825 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 826 struct ast2600_sdrammc_regs *regs = priv->regs; 827 struct udevice *clk_dev; 828 int ret; 829 volatile uint32_t reg; 830 831 /* find SCU base address from clock device */ 832 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 833 &clk_dev); 834 if (ret) { 835 debug("clock device not defined\n"); 836 return ret; 837 } 838 839 priv->scu = devfdt_get_addr_ptr(clk_dev); 840 if (IS_ERR(priv->scu)) { 841 debug("%s(): can't get SCU\n", __func__); 842 return PTR_ERR(priv->scu); 843 } 844 845 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 846 printf("already initialized, "); 847 ast2600_sdrammc_calc_size(priv); 848 #ifdef CONFIG_ASPEED_ECC 849 ast2600_sdrammc_ecc_enable(priv); 850 #endif 851 return 0; 852 } 853 854 #ifdef AST2600_SDRAMMC_MANUAL_CLK 855 reg = readl(priv->scu + AST_SCU_MPLL); 856 reg &= ~(BIT(24) | GENMASK(22, 0)); 857 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 858 writel(reg, priv->scu + AST_SCU_MPLL); 859 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 860 udelay(100); 861 reg &= ~(BIT(25) | BIT(23)); 862 writel(reg, priv->scu + AST_SCU_MPLL); 863 while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))); 864 #else 865 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 866 if (ret) { 867 debug("DDR:No CLK\n"); 868 return ret; 869 } 870 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 871 #endif 872 873 #if 0 874 /* FIXME: enable the following code if reset-driver is ready */ 875 struct reset_ctl reset_ctl; 876 ret = reset_get_by_index(dev, 0, &reset_ctl); 877 if (ret) { 878 debug("%s(): Failed to get reset signal\n", __func__); 879 return ret; 880 } 881 882 ret = reset_assert(&reset_ctl); 883 if (ret) { 884 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 885 return ret; 886 } 887 #endif 888 889 ast2600_sdrammc_unlock(priv); 890 ast2600_sdrammc_common_init(regs); 891 L_ast2600_sdramphy_train: 892 ast2600_sdrammc_init_ddr4(priv); 893 894 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 895 ast2600_sdrammc_search_read_window(priv); 896 #else 897 /* make sure DDR-PHY is ready before access */ 898 do { 899 reg = readl(priv->phy_status) & BIT(1); 900 } while(reg == 0); 901 #endif 902 903 if (0 != ast2600_sdramphy_check_status(priv)) { 904 printf("DDR4 PHY training fail, retrain\n"); 905 goto L_ast2600_sdramphy_train; 906 } 907 908 ast2600_sdrammc_calc_size(priv); 909 910 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 911 if (0 != ast2600_sdrammc_test(priv)) { 912 printf("%s: DDR4 init fail\n", __func__); 913 return -EINVAL; 914 } 915 #endif 916 917 #ifdef CONFIG_ASPEED_ECC 918 ast2600_sdrammc_ecc_enable(priv); 919 #endif 920 921 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 922 priv->scu + AST_SCU_HANDSHAKE); 923 924 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 925 ast2600_sdrammc_lock(priv); 926 return 0; 927 } 928 929 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 930 { 931 struct dram_info *priv = dev_get_priv(dev); 932 933 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 934 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 935 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 936 937 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 938 "clock-frequency", 0); 939 if (!priv->clock_rate) { 940 debug("DDR Clock Rate not defined\n"); 941 return -EINVAL; 942 } 943 944 return 0; 945 } 946 947 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 948 { 949 struct dram_info *priv = dev_get_priv(dev); 950 951 *info = priv->info; 952 953 return 0; 954 } 955 956 static struct ram_ops ast2600_sdrammc_ops = { 957 .get_info = ast2600_sdrammc_get_info, 958 }; 959 960 static const struct udevice_id ast2600_sdrammc_ids[] = { 961 { .compatible = "aspeed,ast2600-sdrammc" }, 962 { } 963 }; 964 965 U_BOOT_DRIVER(sdrammc_ast2600) = { 966 .name = "aspeed_ast2600_sdrammc", 967 .id = UCLASS_RAM, 968 .of_match = ast2600_sdrammc_ids, 969 .ops = &ast2600_sdrammc_ops, 970 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 971 .probe = ast2600_sdrammc_probe, 972 .priv_auto_alloc_size = sizeof(struct dram_info), 973 }; 974