1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 45 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 46 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 47 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 48 #define SCU_HANDSHAKE_MASK \ 49 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 50 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 51 52 /* bit-field of AST_SCU_MPLL */ 53 #define SCU_MPLL_RESET BIT(25) 54 #define SCU_MPLL_BYPASS BIT(24) 55 #define SCU_MPLL_TURN_OFF BIT(23) 56 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 57 58 #define SCU_MPLL_FREQ_400M 0x0008405F 59 #define SCU_MPLL_EXT_400M 0x0000002F 60 //#define SCU_MPLL_FREQ_400M 0x0038007F 61 //#define SCU_MPLL_EXT_400M 0x0000003F 62 #define SCU_MPLL_FREQ_333M 0x00488299 63 #define SCU_MPLL_EXT_333M 0x0000014C 64 #define SCU_MPLL_FREQ_200M 0x0078007F 65 #define SCU_MPLL_EXT_200M 0x0000003F 66 #define SCU_MPLL_FREQ_100M 0x0078003F 67 #define SCU_MPLL_EXT_100M 0x0000001F 68 /* MPLL configuration */ 69 #if defined(CONFIG_ASPEED_DDR4_1600) 70 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 71 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 72 #elif defined(CONFIG_ASPEED_DDR4_1333) 73 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 74 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 75 #elif defined(CONFIG_ASPEED_DDR4_800) 76 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 77 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 78 #elif defined(CONFIG_ASPEED_DDR4_400) 79 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 80 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 81 #else 82 #error "undefined DDR4 target rate\n" 83 #endif 84 85 /* AC timing and SDRAM mode registers */ 86 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 87 /* mode register settings for FPGA are fixed */ 88 #define DDR4_MR01_MODE 0x03010100 89 #define DDR4_MR23_MODE 0x00000000 90 #define DDR4_MR45_MODE 0x04C00000 91 #define DDR4_MR6_MODE 0x00000050 92 #define DDR4_TRFC_FPGA 0x17263434 93 94 /* FPGA need for an additional initialization procedure: search read window */ 95 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 96 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 97 #define SEARCH_RDWIN_PTRN_0 0x12345678 98 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 99 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 100 #else 101 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 102 #define DDR4_MR01_MODE 0x03010510 103 #define DDR4_MR23_MODE 0x00000000 104 #define DDR4_MR45_MODE 0x04000000 105 #define DDR4_MR6_MODE 0x00000400 106 #define DDR4_TRFC_1600 0x467299f1 107 #define DDR4_TRFC_1333 0x3a5f80c9 108 #define DDR4_TRFC_800 0x23394c78 109 #define DDR4_TRFC_400 0x111c263c 110 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 111 defined(CONFIG_ASPEED_PALLADIUM)" */ 112 113 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 114 #define DDR4_TRFC DDR4_TRFC_FPGA 115 #else 116 /* real chip setting */ 117 #if defined(CONFIG_ASPEED_DDR4_1600) 118 #define DDR4_TRFC DDR4_TRFC_1600 119 #define DDR4_PHY_TRAIN_TRFC 0xc30 120 #elif defined(CONFIG_ASPEED_DDR4_1333) 121 #define DDR4_TRFC DDR4_TRFC_1333 122 #define DDR4_PHY_TRAIN_TRFC 0xa25 123 #elif defined(CONFIG_ASPEED_DDR4_800) 124 #define DDR4_TRFC DDR4_TRFC_800 125 #define DDR4_PHY_TRAIN_TRFC 0x618 126 #elif defined(CONFIG_ASPEED_DDR4_400) 127 #define DDR4_TRFC DDR4_TRFC_400 128 #define DDR4_PHY_TRAIN_TRFC 0x30c 129 #else 130 #error "undefined tRFC setting" 131 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 132 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 133 defined(CONFIG_ASPEED_PALLADIUM)" */ 134 135 /* supported SDRAM size */ 136 #define SDRAM_SIZE_1KB (1024U) 137 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 138 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 139 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 140 141 142 DECLARE_GLOBAL_DATA_PTR; 143 144 /* 145 * Bandwidth configuration parameters for different SDRAM requests. 146 * These are hardcoded settings taken from Aspeed SDK. 147 */ 148 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 149 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 150 0x00000140 }; 151 152 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 153 0x88888888 }; 154 #else 155 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 156 0x00001240 }; 157 158 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 159 0x44444444 }; 160 #endif 161 162 struct dram_info { 163 struct ram_info info; 164 struct clk ddr_clk; 165 struct ast2600_sdrammc_regs *regs; 166 void __iomem *scu; 167 struct ast2600_ddr_phy *phy; 168 void __iomem *phy_setting; 169 void __iomem *phy_status; 170 ulong clock_rate; 171 }; 172 173 static void ast2600_sdramphy_kick_training(struct dram_info *info) 174 { 175 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 176 struct ast2600_sdrammc_regs *regs = info->regs; 177 u32 volatile data; 178 179 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 180 udelay(5); 181 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 182 udelay(1000); 183 184 while (1) { 185 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 186 if (~data) { 187 break; 188 } 189 } 190 191 #if 0 192 while (1) { 193 data = readl(0x1e6e0400) & BIT(1); 194 if (data) { 195 break; 196 } 197 } 198 #endif 199 #endif 200 } 201 202 /** 203 * @brief load DDR-PHY configurations table to the PHY registers 204 * @param[in] p_tbl - pointer to the configuration table 205 * @param[in] info - pointer to the DRAM info struct 206 * 207 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 208 * system: one is in the SDRAM MC (memory controller) which is used in run 209 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 210 * training. 211 */ 212 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 213 { 214 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 215 u32 reg_base = (u32)info->phy_setting; 216 u32 addr = p_tbl[0]; 217 u32 data; 218 int i = 1; 219 220 writel(0, &info->regs->phy_ctrl[0]); 221 udelay(10); 222 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 223 224 /* load PHY configuration table into PHY-setting registers */ 225 while (1) { 226 if (addr < reg_base) { 227 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 228 break; 229 } 230 data = p_tbl[i++]; 231 232 if (data == DDR_PHY_TBL_END) { 233 break; 234 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 235 addr = p_tbl[i++]; 236 } else { 237 writel(data, addr); 238 addr += 4; 239 } 240 } 241 242 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 243 data |= DDR4_PHY_TRAIN_TRFC; 244 writel(data, info->phy_setting + 0x84); 245 #endif 246 } 247 248 static int ast2600_sdramphy_check_status(struct dram_info *info) 249 { 250 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 251 u32 value, tmp; 252 u32 reg_base = (u32)info->phy_status; 253 int need_retrain = 0; 254 255 debug("\nSDRAM PHY training report:\n"); 256 /* training status */ 257 value = readl(reg_base + 0x00); 258 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 259 if (value & BIT(3)) { 260 debug("\tinitial PVT calibration fail\n"); 261 } 262 if (value & BIT(5)) { 263 debug("\truntime calibration fail\n"); 264 } 265 266 /* PU & PD */ 267 value = readl(reg_base + 0x30); 268 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 269 debug(" PU = 0x%02x\n", value & 0xff); 270 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 271 272 /* read eye window */ 273 value = readl(reg_base + 0x68); 274 if (0 == (value & GENMASK(7, 0))) { 275 need_retrain = 1; 276 } 277 278 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 279 debug(" rising edge of read data eye training pass window\n"); 280 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 281 debug(" B0:%d%%\n", tmp); 282 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 283 debug(" B1:%d%%\n", tmp); 284 285 value = readl(reg_base + 0xC8); 286 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 287 debug(" falling edge of read data eye training pass window\n"); 288 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 289 debug(" B0:%d%%\n", tmp); 290 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 291 debug(" B1:%d%%\n", tmp); 292 293 /* write eye window */ 294 value = readl(reg_base + 0x7c); 295 if (0 == (value & GENMASK(7, 0))) { 296 need_retrain = 1; 297 } 298 299 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 300 debug(" rising edge of write data eye training pass window\n"); 301 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 302 debug(" B0:%d%%\n", tmp); 303 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 304 debug(" B1:%d%%\n", tmp); 305 306 /* read Vref training result */ 307 value = readl(reg_base + 0x88); 308 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 309 debug(" read Vref training result\n"); 310 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 311 debug(" B0:%d%%\n", tmp); 312 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 313 debug(" B1:%d%%\n", tmp); 314 315 /* write Vref training result */ 316 value = readl(reg_base + 0x90); 317 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 318 #if 0 319 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 320 debug(" write Vref training result = %d%%\n", tmp); 321 #endif 322 323 /* gate train */ 324 value = readl(reg_base + 0x50); 325 if ((0 == (value & GENMASK(15, 0))) || 326 (0 == (value & GENMASK(31, 16)))) { 327 need_retrain = 1; 328 } 329 #if 0 330 if (((value >> 24) & 0xff) < 3) 331 need_retrain = 1; 332 else 333 need_retrain = 0; 334 #endif 335 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 336 #if 0 337 debug(" gate training pass window\n"); 338 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 339 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 340 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 341 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 342 #endif 343 344 return need_retrain; 345 #else 346 return 0; 347 #endif 348 } 349 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 350 #define MC_TEST_PATTERN_N 8 351 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 352 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 353 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 354 }; 355 356 #define TIMEOUT_DRAM 5000000 357 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 358 { 359 unsigned int data; 360 unsigned int timeout = 0; 361 struct ast2600_sdrammc_regs *regs = info->regs; 362 363 writel(0, ®s->ecc_test_ctrl); 364 if (mode == 0) 365 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 366 else 367 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 368 369 do { 370 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 371 372 if (data & BIT(13)) 373 return 0; 374 375 if (++timeout > TIMEOUT_DRAM) { 376 printf("Timeout!!\n"); 377 writel(0, ®s->ecc_test_ctrl); 378 379 return 0; 380 } 381 } while (!data); 382 383 writel(0, ®s->ecc_test_ctrl); 384 385 return 1; 386 } 387 388 int ast2600_sdrammc_cbr_test(struct dram_info *info) 389 { 390 struct ast2600_sdrammc_regs *regs = info->regs; 391 u32 i; 392 393 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 394 395 /* single */ 396 for (i = 0; i < 8; i++) { 397 if (!ast2600_sdrammc_dg_test(info, i, 0)) 398 return (0); 399 } 400 401 /* burst */ 402 for (i = 0; i < 8; i++) { 403 if (!ast2600_sdrammc_dg_test(info, i, i)) 404 return (0); 405 } 406 407 return(1); 408 } 409 410 static int ast2600_sdrammc_test(struct dram_info *info) 411 { 412 struct ast2600_sdrammc_regs *regs = info->regs; 413 414 u32 pass_cnt = 0; 415 u32 fail_cnt = 0; 416 u32 target_cnt = 2; 417 u32 test_cnt = 0; 418 u32 pattern; 419 u32 i = 0; 420 bool finish = false; 421 422 debug("sdram mc test:\n"); 423 while (finish == false) { 424 pattern = as2600_sdrammc_test_pattern[i++]; 425 i = i % MC_TEST_PATTERN_N; 426 debug(" pattern = %08X : ", pattern); 427 writel(pattern, ®s->test_init_val); 428 429 if (!ast2600_sdrammc_cbr_test(info)) { 430 debug("fail\n"); 431 fail_cnt++; 432 } else { 433 debug("pass\n"); 434 pass_cnt++; 435 } 436 437 if (++test_cnt == target_cnt) { 438 finish = true; 439 } 440 } 441 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 442 target_cnt); 443 return fail_cnt; 444 } 445 #endif 446 /** 447 * scu500[14:13] 448 * 2b'00: VGA memory size = 16MB 449 * 2b'01: VGA memory size = 16MB 450 * 2b'10: VGA memory size = 32MB 451 * 2b'11: VGA memory size = 64MB 452 * 453 * mcr04[3:2] 454 * 2b'00: VGA memory size = 8MB 455 * 2b'01: VGA memory size = 16MB 456 * 2b'10: VGA memory size = 32MB 457 * 2b'11: VGA memory size = 64MB 458 */ 459 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 460 { 461 u32 vga_hwconf; 462 size_t vga_mem_size_base = 8 * 1024 * 1024; 463 464 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 465 SCU_HWSTRAP_VGAMEM_MASK) >> 466 SCU_HWSTRAP_VGAMEM_SHIFT; 467 468 if (vga_hwconf == 0) { 469 vga_hwconf = 1; 470 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 471 info->scu + AST_SCU_HW_STRAP); 472 } 473 474 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 475 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 476 SDRAM_CONF_VGA_SIZE_MASK)); 477 478 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 479 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 480 return 0; 481 482 return vga_mem_size_base << vga_hwconf; 483 } 484 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 485 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 486 { 487 u32 data; 488 u32 scu_base = (u32)info->scu; 489 490 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 491 492 do { 493 data = readl(scu_base + AST_SCU_FPGA_STATUS); 494 } while (!(data & 0x100)); 495 496 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 497 } 498 499 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 500 { 501 u32 pll, pll_min, pll_max, dat1, offset; 502 u32 win = 0x03, gwin = 0, gwinsize = 0; 503 u32 phy_setting = (u32)info->phy_setting; 504 505 #ifdef CONFIG_ASPEED_PALLADIUM 506 writel(0xc, phy_setting + 0x0000); 507 return 1; 508 #endif 509 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 510 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 511 512 while (gwin == 0) { 513 while (!(win & 0x80)) { 514 debug("Window = 0x%X\n", win); 515 writel(win, phy_setting + 0x0000); 516 517 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 518 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 519 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 520 ast2600_sdrammc_fpga_set_pll(info); 521 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 522 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 523 } 524 525 pll_min = 0xfff; 526 pll_max = 0x0; 527 pll = 0; 528 while (pll_max > 0 || pll < 256) { 529 ast2600_sdrammc_fpga_set_pll(info); 530 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 531 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 532 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 533 if (pll_min > pll) 534 pll_min = pll; 535 536 if (pll_max < pll) 537 pll_max = pll; 538 539 debug("%3d_(%3d:%3d)\n", pll, pll_min, 540 pll_max); 541 } else if (pll_max > 0) { 542 pll_min = pll_max - pll_min; 543 if (gwinsize < pll_min) { 544 gwin = win; 545 gwinsize = pll_min; 546 } 547 break; 548 } 549 pll += 1; 550 } 551 552 if (gwin != 0 && pll_max == 0) 553 break; 554 555 win = win << 1; 556 } 557 if (gwin == 0) 558 win = 0x7; 559 } 560 debug("Set PLL Read Gating Window = %x\n", gwin); 561 writel(gwin, phy_setting + 0x0000); 562 563 debug("PLL Read Window training\n"); 564 pll_min = 0xfff; 565 pll_max = 0x0; 566 567 debug("Search Window Start\n"); 568 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 569 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 570 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 571 ast2600_sdrammc_fpga_set_pll(info); 572 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 573 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 574 } 575 576 debug("Search Window Margin\n"); 577 pll = 0; 578 while (pll_max > 0 || pll < 256) { 579 ast2600_sdrammc_fpga_set_pll(info); 580 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 581 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 582 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 583 if (pll_min > pll) 584 pll_min = pll; 585 586 if (pll_max < pll) 587 pll_max = pll; 588 589 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 590 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 591 break; 592 } else if (pll_max > 0) { 593 pll_min = 0xfff; 594 pll_max = 0x0; 595 } 596 pll += 1; 597 } 598 if (pll_min < pll_max) { 599 debug("PLL Read window = %d\n", (pll_max - pll_min)); 600 offset = (pll_max - pll_min) >> 1; 601 pll_min = 0xfff; 602 pll = 0; 603 while (pll < (pll_min + offset)) { 604 ast2600_sdrammc_fpga_set_pll(info); 605 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 606 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 607 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 608 if (pll_min > pll) { 609 pll_min = pll; 610 } 611 debug("%d\n", pll); 612 } else { 613 pll_min = 0xfff; 614 pll_max = 0x0; 615 } 616 pll += 1; 617 } 618 return (1); 619 } else { 620 debug("PLL Read window training fail\n"); 621 return 0; 622 } 623 } 624 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 625 defined(CONFIG_ASPEED_PALLADIUM)" */ 626 627 /* 628 * Find out RAM size and save it in dram_info 629 * 630 * The procedure is taken from Aspeed SDK 631 */ 632 static void ast2600_sdrammc_calc_size(struct dram_info *info) 633 { 634 /* The controller supports 256/512/1024/2048 MB ram */ 635 size_t ram_size = SDRAM_MIN_SIZE; 636 const int write_test_offset = 0x100000; 637 u32 test_pattern = 0xdeadbeef; 638 u32 cap_param = SDRAM_CONF_CAP_2048M; 639 u32 refresh_timing_param = DDR4_TRFC; 640 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 641 642 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 643 ram_size >>= 1) { 644 writel(test_pattern, write_addr_base + (ram_size >> 1)); 645 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 646 } 647 648 /* One last write to overwrite all wrapped values */ 649 writel(test_pattern, write_addr_base); 650 651 /* Reset the pattern and see which value was really written */ 652 test_pattern = 0xdeadbeef; 653 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 654 ram_size >>= 1) { 655 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 656 break; 657 658 --cap_param; 659 refresh_timing_param >>= 8; 660 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 661 } 662 663 clrsetbits_le32(&info->regs->ac_timing[1], 664 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 665 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 666 << SDRAM_AC_TRFC_SHIFT)); 667 668 info->info.base = CONFIG_SYS_SDRAM_BASE; 669 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 670 671 clrsetbits_le32( 672 &info->regs->config, SDRAM_CONF_CAP_MASK, 673 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 674 } 675 676 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 677 { 678 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 679 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 680 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 681 (0x1 << MCR34_ODT_EXT_SHIFT); 682 683 /* init SDRAM-PHY only on real chip */ 684 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 685 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 686 &info->regs->power_ctrl); 687 udelay(5); 688 ast2600_sdramphy_kick_training(info); 689 udelay(500); 690 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 691 692 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 693 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 694 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 695 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 696 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 697 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 698 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 699 &info->regs->mode_setting_control); 700 701 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 702 703 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 704 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 705 &info->regs->refresh_timing); 706 #else 707 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 708 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 709 &info->regs->refresh_timing); 710 #endif 711 712 /* wait self-refresh idle */ 713 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 714 ; 715 716 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 717 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 718 SDRAM_REFRESH_ZQCS_EN | 719 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 720 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 721 &info->regs->refresh_timing); 722 #else 723 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 724 SDRAM_REFRESH_ZQCS_EN | 725 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 726 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 727 &info->regs->refresh_timing); 728 #endif 729 730 writel(power_ctrl, &info->regs->power_ctrl); 731 udelay(500); 732 733 #if defined(CONFIG_FPGA_ASPEED) 734 /* toggle Vref training */ 735 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 736 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 737 &info->regs->mode_setting_control); 738 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 739 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 740 &info->regs->mode_setting_control); 741 #endif 742 return 0; 743 } 744 745 static void ast2600_sdrammc_unlock(struct dram_info *info) 746 { 747 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 748 while (!readl(&info->regs->protection_key)) 749 ; 750 } 751 752 static void ast2600_sdrammc_lock(struct dram_info *info) 753 { 754 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 755 while (readl(&info->regs->protection_key)) 756 ; 757 } 758 759 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 760 { 761 int i; 762 763 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 764 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 765 /* [6:0] : Group 1 request queued number = 16 766 * [14:8] : Group 2 request queued number = 16 767 * [20:16] : R/W max-grant count for RQ output arbitration = 16 768 */ 769 writel(0x101010, ®s->arbitration_ctrl); 770 /* Request Queued Limitation for REQ8/9 USB1/2 */ 771 writel(0x0FFF3CEF, ®s->req_limit_mask); 772 773 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 774 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 775 776 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 777 778 /* FIXME: the sample code does NOT match the datasheet */ 779 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 780 781 writel(0, ®s->ecc_test_ctrl); 782 writel(0x80000001, ®s->test_addr); 783 writel(0, ®s->test_fail_dq_bit); 784 writel(0, ®s->test_init_val); 785 786 writel(0xFFFFFFFF, ®s->req_input_ctrl); 787 writel(0x300, ®s->req_high_pri_ctrl); 788 789 udelay(600); 790 791 #ifdef CONFIG_ASPEED_DDR4_DUALX8 792 writel(0xa037, ®s->config); 793 #else 794 writel(0xa017, ®s->config); 795 #endif 796 797 /* load controller setting */ 798 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 799 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 800 801 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 802 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 803 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 804 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 805 } 806 /* 807 * Update size info according to the ECC HW setting 808 * 809 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 810 * don't need to calculate the ECC size again but read from MCR04 and derive the 811 * size from its value. 812 */ 813 static void ast2600_sdrammc_update_size(struct dram_info *info) 814 { 815 struct ast2600_sdrammc_regs *regs = info->regs; 816 size_t hw_size; 817 size_t ram_size = SDRAM_MAX_SIZE; 818 u32 cap_param; 819 820 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 821 switch (cap_param) 822 { 823 case SDRAM_CONF_CAP_2048M: 824 ram_size = 2048 * SDRAM_SIZE_1MB; 825 break; 826 case SDRAM_CONF_CAP_1024M: 827 ram_size = 1024 * SDRAM_SIZE_1MB; 828 break; 829 case SDRAM_CONF_CAP_512M: 830 ram_size = 512 * SDRAM_SIZE_1MB; 831 break; 832 case SDRAM_CONF_CAP_256M: 833 ram_size = 256 * SDRAM_SIZE_1MB; 834 break; 835 } 836 837 info->info.base = CONFIG_SYS_SDRAM_BASE; 838 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 839 840 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 841 return; 842 843 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 844 hw_size += (1 << 20); 845 846 info->info.size = hw_size; 847 } 848 #ifdef CONFIG_ASPEED_ECC 849 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 850 { 851 struct ast2600_sdrammc_regs *regs = info->regs; 852 size_t conf_size; 853 u32 reg; 854 855 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 856 if (conf_size > info->info.size) { 857 printf("warning: ECC configured %dMB but actual size is %dMB\n", 858 CONFIG_ASPEED_ECC_SIZE, 859 info->info.size / SDRAM_SIZE_1MB); 860 conf_size = info->info.size; 861 } else if (conf_size == 0) { 862 conf_size = info->info.size; 863 } 864 865 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 866 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 867 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 868 writel(reg, ®s->config); 869 870 writel(0, ®s->test_init_val); 871 writel(0x80000001, ®s->test_addr); 872 writel(0x221, ®s->ecc_test_ctrl); 873 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 874 ; 875 writel(0, ®s->ecc_test_ctrl); 876 writel(BIT(31), ®s->intr_ctrl); 877 writel(0, ®s->intr_ctrl); 878 } 879 #endif 880 881 static int ast2600_sdrammc_probe(struct udevice *dev) 882 { 883 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 884 struct ast2600_sdrammc_regs *regs = priv->regs; 885 struct udevice *clk_dev; 886 int ret; 887 volatile uint32_t reg; 888 889 /* find SCU base address from clock device */ 890 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 891 &clk_dev); 892 if (ret) { 893 debug("clock device not defined\n"); 894 return ret; 895 } 896 897 priv->scu = devfdt_get_addr_ptr(clk_dev); 898 if (IS_ERR(priv->scu)) { 899 debug("%s(): can't get SCU\n", __func__); 900 return PTR_ERR(priv->scu); 901 } 902 903 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 904 printf("already initialized, "); 905 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 906 ast2600_sdrammc_update_size(priv); 907 return 0; 908 } 909 910 #ifdef AST2600_SDRAMMC_MANUAL_CLK 911 reg = readl(priv->scu + AST_SCU_MPLL); 912 reg &= ~(BIT(24) | GENMASK(22, 0)); 913 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 914 writel(reg, priv->scu + AST_SCU_MPLL); 915 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 916 udelay(100); 917 reg &= ~(BIT(25) | BIT(23)); 918 writel(reg, priv->scu + AST_SCU_MPLL); 919 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 920 ; 921 #else 922 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 923 if (ret) { 924 debug("DDR:No CLK\n"); 925 return ret; 926 } 927 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 928 #endif 929 930 #if 0 931 /* FIXME: enable the following code if reset-driver is ready */ 932 struct reset_ctl reset_ctl; 933 ret = reset_get_by_index(dev, 0, &reset_ctl); 934 if (ret) { 935 debug("%s(): Failed to get reset signal\n", __func__); 936 return ret; 937 } 938 939 ret = reset_assert(&reset_ctl); 940 if (ret) { 941 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 942 return ret; 943 } 944 #endif 945 946 ast2600_sdrammc_unlock(priv); 947 ast2600_sdrammc_common_init(regs); 948 L_ast2600_sdramphy_train: 949 ast2600_sdrammc_init_ddr4(priv); 950 951 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 952 ast2600_sdrammc_search_read_window(priv); 953 #else 954 /* make sure DDR-PHY is ready before access */ 955 do { 956 reg = readl(priv->phy_status) & BIT(1); 957 } while (reg == 0); 958 #endif 959 960 if (0 != ast2600_sdramphy_check_status(priv)) { 961 printf("DDR4 PHY training fail, retrain\n"); 962 goto L_ast2600_sdramphy_train; 963 } 964 965 ast2600_sdrammc_calc_size(priv); 966 967 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 968 if (0 != ast2600_sdrammc_test(priv)) { 969 printf("%s: DDR4 init fail\n", __func__); 970 return -EINVAL; 971 } 972 #endif 973 974 #ifdef CONFIG_ASPEED_ECC 975 ast2600_sdrammc_ecc_enable(priv); 976 #endif 977 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 978 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 979 ast2600_sdrammc_lock(priv); 980 return 0; 981 } 982 983 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 984 { 985 struct dram_info *priv = dev_get_priv(dev); 986 987 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 988 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 989 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 990 991 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 992 "clock-frequency", 0); 993 if (!priv->clock_rate) { 994 debug("DDR Clock Rate not defined\n"); 995 return -EINVAL; 996 } 997 998 return 0; 999 } 1000 1001 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 1002 { 1003 struct dram_info *priv = dev_get_priv(dev); 1004 1005 *info = priv->info; 1006 1007 return 0; 1008 } 1009 1010 static struct ram_ops ast2600_sdrammc_ops = { 1011 .get_info = ast2600_sdrammc_get_info, 1012 }; 1013 1014 static const struct udevice_id ast2600_sdrammc_ids[] = { 1015 { .compatible = "aspeed,ast2600-sdrammc" }, 1016 { } 1017 }; 1018 1019 U_BOOT_DRIVER(sdrammc_ast2600) = { 1020 .name = "aspeed_ast2600_sdrammc", 1021 .id = UCLASS_RAM, 1022 .of_match = ast2600_sdrammc_ids, 1023 .ops = &ast2600_sdrammc_ops, 1024 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1025 .probe = ast2600_sdrammc_probe, 1026 .priv_auto_alloc_size = sizeof(struct dram_info), 1027 }; 1028