1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 34 35 /* bit-field of AST_SCU_HW_STRAP */ 36 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 37 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 38 39 40 /* bit-field of AST_SCU_HANDSHAKE */ 41 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 42 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 43 44 /* bit-field of AST_SCU_MPLL */ 45 #define SCU_MPLL_RESET BIT(25) 46 #define SCU_MPLL_BYPASS BIT(24) 47 #define SCU_MPLL_TURN_OFF BIT(23) 48 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 49 50 #define SCU_MPLL_FREQ_400M 0x0008405F 51 #define SCU_MPLL_EXT_400M 0x00000031 52 //#define SCU_MPLL_FREQ_400M 0x0038007F 53 //#define SCU_MPLL_EXT_400M 0x0000003F 54 #define SCU_MPLL_FREQ_333M 0x00488299 55 #define SCU_MPLL_EXT_333M 0x0000014C 56 #define SCU_MPLL_FREQ_200M 0x0078007F 57 #define SCU_MPLL_EXT_200M 0x0000003F 58 #define SCU_MPLL_FREQ_100M 0x0078003F 59 #define SCU_MPLL_EXT_100M 0x0000001F 60 /* MPLL configuration */ 61 #if defined(CONFIG_ASPEED_DDR4_1600) 62 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 63 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 64 #elif defined(CONFIG_ASPEED_DDR4_1333) 65 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 66 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 67 #elif defined(CONFIG_ASPEED_DDR4_800) 68 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 69 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 70 #elif defined(CONFIG_ASPEED_DDR4_400) 71 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 72 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 73 #else 74 #error "undefined DDR4 target rate\n" 75 #endif 76 77 /* AC timing and SDRAM mode registers */ 78 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 79 /* mode register settings for FPGA are fixed */ 80 #define DDR4_MR01_MODE 0x03010100 81 #define DDR4_MR23_MODE 0x00000000 82 #define DDR4_MR45_MODE 0x04C00000 83 #define DDR4_MR6_MODE 0x00000050 84 #define DDR4_TRFC_FPGA 0x17263434 85 86 /* FPGA need for an additional initialization procedure: search read window */ 87 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 88 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 89 #define SEARCH_RDWIN_PTRN_0 0x12345678 90 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 91 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 92 #else 93 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 94 #define DDR4_MR01_MODE 0x03010510 95 #define DDR4_MR23_MODE 0x00000000 96 #define DDR4_MR45_MODE 0x04000000 97 #define DDR4_MR6_MODE 0x00000400 98 #define DDR4_TRFC_1600 0x467299f1 99 #define DDR4_TRFC_1333 0x3a5f80c9 100 #define DDR4_TRFC_800 0x23394c78 101 #define DDR4_TRFC_400 0x111c263c 102 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 103 defined(CONFIG_ASPEED_PALLADIUM)" */ 104 105 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 106 #define DDR4_TRFC DDR4_TRFC_FPGA 107 #else 108 /* real chip setting */ 109 #if defined(CONFIG_ASPEED_DDR4_1600) 110 #define DDR4_TRFC DDR4_TRFC_1600 111 #define DDR4_PHY_TRAIN_TRFC 0xc30 112 #elif defined(CONFIG_ASPEED_DDR4_1333) 113 #define DDR4_TRFC DDR4_TRFC_1333 114 #define DDR4_PHY_TRAIN_TRFC 0xa25 115 #elif defined(CONFIG_ASPEED_DDR4_800) 116 #define DDR4_TRFC DDR4_TRFC_800 117 #define DDR4_PHY_TRAIN_TRFC 0x618 118 #elif defined(CONFIG_ASPEED_DDR4_400) 119 #define DDR4_TRFC DDR4_TRFC_400 120 #define DDR4_PHY_TRAIN_TRFC 0x30c 121 #else 122 #error "undefined tRFC setting" 123 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 124 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 125 defined(CONFIG_ASPEED_PALLADIUM)" */ 126 127 /* supported SDRAM size */ 128 #define SDRAM_SIZE_1KB (1024U) 129 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 130 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 131 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 132 133 134 DECLARE_GLOBAL_DATA_PTR; 135 136 /* 137 * Bandwidth configuration parameters for different SDRAM requests. 138 * These are hardcoded settings taken from Aspeed SDK. 139 */ 140 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 141 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 142 0x00000140}; 143 144 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 145 0x88888888}; 146 #else 147 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 148 0x00001240}; 149 150 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 151 0x44444444}; 152 #endif 153 154 struct dram_info { 155 struct ram_info info; 156 struct clk ddr_clk; 157 struct ast2600_sdrammc_regs *regs; 158 void __iomem *scu; 159 struct ast2600_ddr_phy *phy; 160 void __iomem *phy_setting; 161 void __iomem *phy_status; 162 ulong clock_rate; 163 }; 164 165 static void ast2600_sdramphy_kick_training(struct dram_info *info) 166 { 167 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 168 struct ast2600_sdrammc_regs *regs = info->regs; 169 u32 volatile data; 170 171 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 172 udelay(5); 173 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 174 udelay(1000); 175 176 while (1) { 177 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 178 if (~data) { 179 break; 180 } 181 } 182 183 #if 0 184 while (1) { 185 data = readl(0x1e6e0400) & BIT(1); 186 if (data) { 187 break; 188 } 189 } 190 #endif 191 #endif 192 } 193 194 /** 195 * @brief load DDR-PHY configurations table to the PHY registers 196 * @param[in] p_tbl - pointer to the configuration table 197 * @param[in] info - pointer to the DRAM info struct 198 * 199 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 200 * system: one is in the SDRAM MC (memory controller) which is used in run 201 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 202 * training. 203 */ 204 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 205 { 206 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 207 u32 reg_base = (u32)info->phy_setting; 208 u32 addr = p_tbl[0]; 209 u32 data; 210 int i = 1; 211 212 writel(0, &info->regs->phy_ctrl[0]); 213 udelay(10); 214 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 215 216 217 /* load PHY configuration table into PHY-setting registers */ 218 while (1) { 219 if (addr < reg_base) { 220 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 221 break; 222 } 223 data = p_tbl[i++]; 224 225 if (DDR_PHY_TBL_END == data) { 226 break; 227 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 228 addr = p_tbl[i++]; 229 } else { 230 writel(data, addr); 231 addr += 4; 232 } 233 } 234 235 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 236 data |= DDR4_PHY_TRAIN_TRFC; 237 writel(data, info->phy_setting + 0x84); 238 #endif 239 } 240 241 static int ast2600_sdramphy_check_status(struct dram_info *info) 242 { 243 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 244 u32 value, tmp; 245 u32 reg_base = (u32)info->phy_status; 246 int need_retrain = 0; 247 248 debug("\nSDRAM PHY training report:\n"); 249 /* training status */ 250 value = readl(reg_base + 0x00); 251 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 252 if (value & BIT(3)) { 253 debug("\tinitial PVT calibration fail\n"); 254 } 255 if (value & BIT(5)) { 256 debug("\truntime calibration fail\n"); 257 } 258 259 /* PU & PD */ 260 value = readl(reg_base + 0x30); 261 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 262 debug(" PU = 0x%02x\n", value & 0xff); 263 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 264 265 /* read eye window */ 266 value = readl(reg_base + 0x68); 267 if (0 == (value & GENMASK(7, 0))) { 268 need_retrain = 1; 269 } 270 271 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 272 debug(" rising edge of read data eye training pass window\n"); 273 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 274 debug(" B0:%d%%\n", tmp); 275 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 276 debug(" B1:%d%%\n", tmp); 277 278 value = readl(reg_base + 0xC8); 279 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 280 debug(" falling edge of read data eye training pass window\n"); 281 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 282 debug(" B0:%d%%\n", tmp); 283 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 284 debug(" B1:%d%%\n", tmp); 285 286 /* write eye window */ 287 value = readl(reg_base + 0x7c); 288 if (0 == (value & GENMASK(7, 0))) { 289 need_retrain = 1; 290 } 291 292 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 293 debug(" rising edge of write data eye training pass window\n"); 294 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 295 debug(" B0:%d%%\n", tmp); 296 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 297 debug(" B1:%d%%\n", tmp); 298 299 /* read Vref training result */ 300 value = readl(reg_base + 0x88); 301 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 302 debug(" read Vref training result\n"); 303 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 304 debug(" B0:%d%%\n", tmp); 305 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 306 debug(" B1:%d%%\n", tmp); 307 308 /* write Vref training result */ 309 value = readl(reg_base + 0x90); 310 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 311 #if 0 312 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 313 debug(" write Vref training result = %d%%\n", tmp); 314 #endif 315 316 /* gate train */ 317 value = readl(reg_base + 0x50); 318 if ((0 == (value & GENMASK(15, 0))) || 319 (0 == (value & GENMASK(31, 16)))) { 320 need_retrain = 1; 321 } 322 #if 0 323 if (((value >> 24) & 0xff) < 3) 324 need_retrain = 1; 325 else 326 need_retrain = 0; 327 #endif 328 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 329 #if 0 330 debug(" gate training pass window\n"); 331 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 332 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 333 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 334 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 335 #endif 336 337 return need_retrain; 338 #else 339 return 0; 340 #endif 341 } 342 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 343 #define MC_TEST_PATTERN_N 8 344 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 345 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 346 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 347 348 #define TIMEOUT_DRAM 5000000 349 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 350 { 351 unsigned int data; 352 unsigned int timeout = 0; 353 struct ast2600_sdrammc_regs *regs = info->regs; 354 355 writel(0, ®s->ecc_test_ctrl); 356 if (mode == 0) { 357 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 358 } else { 359 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 360 } 361 362 do { 363 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 364 365 if (data & BIT(13)) 366 return (0); 367 368 if (++timeout > TIMEOUT_DRAM) { 369 printf("Timeout!!\n"); 370 writel(0, ®s->ecc_test_ctrl); 371 372 return (0); 373 } 374 } while (!data); 375 376 writel(0, ®s->ecc_test_ctrl); 377 378 return (1); 379 } 380 381 int ast2600_sdrammc_cbr_test(struct dram_info *info) 382 { 383 struct ast2600_sdrammc_regs *regs = info->regs; 384 u32 i; 385 386 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 387 388 /* single */ 389 for (i=0; i<8; i++) { 390 if(!ast2600_sdrammc_dg_test(info, i, 0)) return(0); 391 } 392 393 /* burst */ 394 for (i=0; i<8; i++) { 395 if(!ast2600_sdrammc_dg_test(info, i, i)) return(0); 396 } 397 398 return(1); 399 } 400 401 static int ast2600_sdrammc_test(struct dram_info *info) 402 { 403 struct ast2600_sdrammc_regs *regs = info->regs; 404 405 u32 pass_cnt = 0; 406 u32 fail_cnt = 0; 407 u32 target_cnt = 2; 408 u32 test_cnt = 0; 409 u32 pattern; 410 u32 i = 0; 411 bool finish = false; 412 413 debug("sdram mc test:\n"); 414 while (finish == false) { 415 pattern = as2600_sdrammc_test_pattern[i++]; 416 i = i % MC_TEST_PATTERN_N; 417 debug(" pattern = %08X : ",pattern); 418 writel(pattern, ®s->test_init_val); 419 420 if (!ast2600_sdrammc_cbr_test(info)) { 421 debug("fail\n"); 422 fail_cnt++; 423 } else { 424 debug("pass\n"); 425 pass_cnt++; 426 } 427 428 if (++test_cnt == target_cnt) { 429 finish = true; 430 } 431 } 432 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 433 target_cnt); 434 return fail_cnt; 435 } 436 #endif 437 /** 438 * scu500[14:13] 439 * 2b'00: VGA memory size = 16MB 440 * 2b'01: VGA memory size = 16MB 441 * 2b'10: VGA memory size = 32MB 442 * 2b'11: VGA memory size = 64MB 443 * 444 * mcr04[3:2] 445 * 2b'00: VGA memory size = 8MB 446 * 2b'01: VGA memory size = 16MB 447 * 2b'10: VGA memory size = 32MB 448 * 2b'11: VGA memory size = 64MB 449 */ 450 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 451 { 452 u32 vga_hwconf; 453 size_t vga_mem_size_base = 8 * 1024 * 1024; 454 455 vga_hwconf = 456 (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >> 457 SCU_HWSTRAP_VGAMEM_SHIFT; 458 459 if (vga_hwconf == 0) { 460 vga_hwconf = 1; 461 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 462 info->scu + AST_SCU_HW_STRAP); 463 } 464 465 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 466 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 467 SDRAM_CONF_VGA_SIZE_MASK)); 468 469 return vga_mem_size_base << vga_hwconf; 470 } 471 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 472 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 473 { 474 u32 data; 475 u32 scu_base = (u32)info->scu; 476 477 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 478 479 do { 480 data = readl(scu_base + AST_SCU_FPGA_STATUS); 481 } while (!(data & 0x100)); 482 483 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 484 } 485 486 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 487 { 488 u32 pll, pll_min, pll_max, dat1, offset; 489 u32 win = 0x03, gwin = 0, gwinsize = 0; 490 u32 phy_setting = (u32)info->phy_setting; 491 492 #ifdef CONFIG_ASPEED_PALLADIUM 493 writel(0xc, phy_setting + 0x0000); 494 return (1); 495 #endif 496 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 497 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 498 499 while (gwin == 0) { 500 while (!(win & 0x80)) { 501 debug("Window = 0x%X\n", win); 502 writel(win, phy_setting + 0x0000); 503 504 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 505 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 506 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 507 ast2600_sdrammc_fpga_set_pll(info); 508 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 509 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 510 } 511 512 pll_min = 0xfff; 513 pll_max = 0x0; 514 pll = 0; 515 while (pll_max > 0 || pll < 256) { 516 ast2600_sdrammc_fpga_set_pll(info); 517 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 518 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 519 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 520 if (pll_min > pll) { 521 pll_min = pll; 522 } 523 if (pll_max < pll) { 524 pll_max = pll; 525 } 526 debug("%3d_(%3d:%3d)\n", pll, pll_min, 527 pll_max); 528 } else if (pll_max > 0) { 529 pll_min = pll_max - pll_min; 530 if (gwinsize < pll_min) { 531 gwin = win; 532 gwinsize = pll_min; 533 } 534 break; 535 } 536 pll += 1; 537 } 538 539 if (gwin != 0 && pll_max == 0) { 540 break; 541 } 542 win = win << 1; 543 } 544 if (gwin == 0) { 545 win = 0x7; 546 } 547 } 548 debug("Set PLL Read Gating Window = %x\n", gwin); 549 writel(gwin, phy_setting + 0x0000); 550 551 debug("PLL Read Window training\n"); 552 pll_min = 0xfff; 553 pll_max = 0x0; 554 555 debug("Search Window Start\n"); 556 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 557 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 558 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 559 ast2600_sdrammc_fpga_set_pll(info); 560 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 561 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 562 } 563 564 debug("Search Window Margin\n"); 565 pll = 0; 566 while (pll_max > 0 || pll < 256) { 567 ast2600_sdrammc_fpga_set_pll(info); 568 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 569 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 570 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 571 if (pll_min > pll) { 572 pll_min = pll; 573 } 574 if (pll_max < pll) { 575 pll_max = pll; 576 } 577 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 578 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 579 break; 580 } else if (pll_max > 0) { 581 pll_min = 0xfff; 582 pll_max = 0x0; 583 } 584 pll += 1; 585 } 586 if (pll_min < pll_max) { 587 debug("PLL Read window = %d\n", (pll_max - pll_min)); 588 offset = (pll_max - pll_min) >> 1; 589 pll_min = 0xfff; 590 pll = 0; 591 while (pll < (pll_min + offset)) { 592 ast2600_sdrammc_fpga_set_pll(info); 593 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 594 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 595 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 596 if (pll_min > pll) { 597 pll_min = pll; 598 } 599 debug("%d\n", pll); 600 } else { 601 pll_min = 0xfff; 602 pll_max = 0x0; 603 } 604 pll += 1; 605 } 606 return (1); 607 } else { 608 debug("PLL Read window training fail\n"); 609 return (0); 610 } 611 } 612 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 613 defined(CONFIG_ASPEED_PALLADIUM)" */ 614 615 /* 616 * Find out RAM size and save it in dram_info 617 * 618 * The procedure is taken from Aspeed SDK 619 */ 620 static void ast2600_sdrammc_calc_size(struct dram_info *info) 621 { 622 /* The controller supports 256/512/1024/2048 MB ram */ 623 size_t ram_size = SDRAM_MIN_SIZE; 624 const int write_test_offset = 0x100000; 625 u32 test_pattern = 0xdeadbeef; 626 u32 cap_param = SDRAM_CONF_CAP_2048M; 627 u32 refresh_timing_param = DDR4_TRFC; 628 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 629 630 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 631 ram_size >>= 1) { 632 writel(test_pattern, write_addr_base + (ram_size >> 1)); 633 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 634 } 635 636 /* One last write to overwrite all wrapped values */ 637 writel(test_pattern, write_addr_base); 638 639 /* Reset the pattern and see which value was really written */ 640 test_pattern = 0xdeadbeef; 641 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 642 ram_size >>= 1) { 643 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 644 break; 645 646 --cap_param; 647 refresh_timing_param >>= 8; 648 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 649 } 650 651 clrsetbits_le32(&info->regs->ac_timing[1], 652 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 653 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 654 << SDRAM_AC_TRFC_SHIFT)); 655 656 info->info.base = CONFIG_SYS_SDRAM_BASE; 657 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 658 clrsetbits_le32( 659 &info->regs->config, SDRAM_CONF_CAP_MASK, 660 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 661 } 662 663 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 664 { 665 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 666 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 667 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 668 (0x1 << MCR34_ODT_EXT_SHIFT); 669 670 /* init SDRAM-PHY only on real chip */ 671 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 672 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 673 &info->regs->power_ctrl); 674 udelay(5); 675 ast2600_sdramphy_kick_training(info); 676 udelay(500); 677 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 678 679 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 680 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 681 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 682 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 683 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 684 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 685 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 686 &info->regs->mode_setting_control); 687 688 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 689 690 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 691 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 692 &info->regs->refresh_timing); 693 #else 694 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 695 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 696 &info->regs->refresh_timing); 697 #endif 698 699 /* wait self-refresh idle */ 700 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 701 ; 702 703 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 704 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 705 SDRAM_REFRESH_ZQCS_EN | 706 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 707 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 708 &info->regs->refresh_timing); 709 #else 710 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 711 SDRAM_REFRESH_ZQCS_EN | 712 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 713 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 714 &info->regs->refresh_timing); 715 #endif 716 717 writel(power_ctrl, &info->regs->power_ctrl); 718 udelay(500); 719 720 #if defined(CONFIG_FPGA_ASPEED) 721 /* toggle Vref training */ 722 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 723 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 724 &info->regs->mode_setting_control); 725 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 726 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 727 &info->regs->mode_setting_control); 728 #endif 729 return 0; 730 } 731 732 static void ast2600_sdrammc_unlock(struct dram_info *info) 733 { 734 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 735 while (!readl(&info->regs->protection_key)) 736 ; 737 } 738 739 static void ast2600_sdrammc_lock(struct dram_info *info) 740 { 741 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 742 while (readl(&info->regs->protection_key)) 743 ; 744 } 745 746 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 747 { 748 int i; 749 750 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 751 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 752 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 753 ®s->arbitration_ctrl); 754 writel(0xFFBBFFF4, ®s->req_limit_mask); 755 756 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 757 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 758 759 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 760 761 /* FIXME: the sample code does NOT match the datasheet */ 762 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 763 764 writel(0, ®s->ecc_test_ctrl); 765 writel(0x80000001, ®s->test_addr); 766 writel(0, ®s->test_fail_dq_bit); 767 writel(0, ®s->test_init_val); 768 769 writel(0xFFFFFFFF, ®s->req_input_ctrl); 770 writel(0, ®s->req_high_pri_ctrl); 771 772 udelay(600); 773 774 #ifdef CONFIG_ASPEED_DDR4_DUALX8 775 writel(0x37, ®s->config); 776 #else 777 writel(0x17, ®s->config); 778 #endif 779 780 /* load controller setting */ 781 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 782 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 783 784 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 785 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 786 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 787 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 788 } 789 /* 790 * Update size info according to the ECC HW setting 791 * 792 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 793 * don't need to calculate the ECC size again but read from MCR04 and derive the 794 * size from its value. 795 */ 796 static void ast2600_sdrammc_update_size(struct dram_info *info) 797 { 798 struct ast2600_sdrammc_regs *regs = info->regs; 799 size_t hw_size; 800 801 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 802 return; 803 804 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 805 hw_size += (1 << 20); 806 807 info->info.size = hw_size; 808 } 809 #ifdef CONFIG_ASPEED_ECC 810 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 811 { 812 struct ast2600_sdrammc_regs *regs = info->regs; 813 size_t conf_size; 814 u32 reg; 815 816 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 817 if (conf_size > info->info.size) { 818 printf("warning: ECC configured %dMB but actual size is %dMB\n", 819 CONFIG_ASPEED_ECC_SIZE, 820 info->info.size / SDRAM_SIZE_1MB); 821 conf_size = info->info.size; 822 } else if (conf_size == 0) { 823 conf_size = info->info.size; 824 } 825 826 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 827 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 828 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 829 writel(reg, ®s->config); 830 831 writel(0, ®s->test_init_val); 832 writel(0x80000001, ®s->test_addr); 833 writel(0x221, ®s->ecc_test_ctrl); 834 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 835 ; 836 writel(0, ®s->ecc_test_ctrl); 837 writel(BIT(31), ®s->intr_ctrl); 838 writel(0, ®s->intr_ctrl); 839 } 840 #endif 841 842 static int ast2600_sdrammc_probe(struct udevice *dev) 843 { 844 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 845 struct ast2600_sdrammc_regs *regs = priv->regs; 846 struct udevice *clk_dev; 847 int ret; 848 volatile uint32_t reg; 849 850 /* find SCU base address from clock device */ 851 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 852 &clk_dev); 853 if (ret) { 854 debug("clock device not defined\n"); 855 return ret; 856 } 857 858 priv->scu = devfdt_get_addr_ptr(clk_dev); 859 if (IS_ERR(priv->scu)) { 860 debug("%s(): can't get SCU\n", __func__); 861 return PTR_ERR(priv->scu); 862 } 863 864 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 865 printf("already initialized, "); 866 ast2600_sdrammc_calc_size(priv); 867 ast2600_sdrammc_update_size(priv); 868 return 0; 869 } 870 871 #ifdef AST2600_SDRAMMC_MANUAL_CLK 872 reg = readl(priv->scu + AST_SCU_MPLL); 873 reg &= ~(BIT(24) | GENMASK(22, 0)); 874 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 875 writel(reg, priv->scu + AST_SCU_MPLL); 876 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 877 udelay(100); 878 reg &= ~(BIT(25) | BIT(23)); 879 writel(reg, priv->scu + AST_SCU_MPLL); 880 while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))); 881 #else 882 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 883 if (ret) { 884 debug("DDR:No CLK\n"); 885 return ret; 886 } 887 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 888 #endif 889 890 #if 0 891 /* FIXME: enable the following code if reset-driver is ready */ 892 struct reset_ctl reset_ctl; 893 ret = reset_get_by_index(dev, 0, &reset_ctl); 894 if (ret) { 895 debug("%s(): Failed to get reset signal\n", __func__); 896 return ret; 897 } 898 899 ret = reset_assert(&reset_ctl); 900 if (ret) { 901 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 902 return ret; 903 } 904 #endif 905 906 ast2600_sdrammc_unlock(priv); 907 ast2600_sdrammc_common_init(regs); 908 L_ast2600_sdramphy_train: 909 ast2600_sdrammc_init_ddr4(priv); 910 911 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 912 ast2600_sdrammc_search_read_window(priv); 913 #else 914 /* make sure DDR-PHY is ready before access */ 915 do { 916 reg = readl(priv->phy_status) & BIT(1); 917 } while(reg == 0); 918 #endif 919 920 if (0 != ast2600_sdramphy_check_status(priv)) { 921 printf("DDR4 PHY training fail, retrain\n"); 922 goto L_ast2600_sdramphy_train; 923 } 924 925 ast2600_sdrammc_calc_size(priv); 926 927 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 928 if (0 != ast2600_sdrammc_test(priv)) { 929 printf("%s: DDR4 init fail\n", __func__); 930 return -EINVAL; 931 } 932 #endif 933 934 #ifdef CONFIG_ASPEED_ECC 935 ast2600_sdrammc_ecc_enable(priv); 936 #endif 937 938 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 939 priv->scu + AST_SCU_HANDSHAKE); 940 941 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 942 ast2600_sdrammc_lock(priv); 943 return 0; 944 } 945 946 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 947 { 948 struct dram_info *priv = dev_get_priv(dev); 949 950 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 951 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 952 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 953 954 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 955 "clock-frequency", 0); 956 if (!priv->clock_rate) { 957 debug("DDR Clock Rate not defined\n"); 958 return -EINVAL; 959 } 960 961 return 0; 962 } 963 964 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 965 { 966 struct dram_info *priv = dev_get_priv(dev); 967 968 *info = priv->info; 969 970 return 0; 971 } 972 973 static struct ram_ops ast2600_sdrammc_ops = { 974 .get_info = ast2600_sdrammc_get_info, 975 }; 976 977 static const struct udevice_id ast2600_sdrammc_ids[] = { 978 { .compatible = "aspeed,ast2600-sdrammc" }, 979 { } 980 }; 981 982 U_BOOT_DRIVER(sdrammc_ast2600) = { 983 .name = "aspeed_ast2600_sdrammc", 984 .id = UCLASS_RAM, 985 .of_match = ast2600_sdrammc_ids, 986 .ops = &ast2600_sdrammc_ops, 987 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 988 .probe = ast2600_sdrammc_probe, 989 .priv_auto_alloc_size = sizeof(struct dram_info), 990 }; 991