1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 45 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 46 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 47 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 48 #define SCU_HANDSHAKE_MASK \ 49 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 50 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 51 52 /* bit-field of AST_SCU_MPLL */ 53 #define SCU_MPLL_RESET BIT(25) 54 #define SCU_MPLL_BYPASS BIT(24) 55 #define SCU_MPLL_TURN_OFF BIT(23) 56 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 57 58 #define SCU_MPLL_FREQ_400M 0x0008405F 59 #define SCU_MPLL_EXT_400M 0x0000002F 60 //#define SCU_MPLL_FREQ_400M 0x0038007F 61 //#define SCU_MPLL_EXT_400M 0x0000003F 62 #define SCU_MPLL_FREQ_333M 0x00488299 63 #define SCU_MPLL_EXT_333M 0x0000014C 64 #define SCU_MPLL_FREQ_200M 0x0078007F 65 #define SCU_MPLL_EXT_200M 0x0000003F 66 #define SCU_MPLL_FREQ_100M 0x0078003F 67 #define SCU_MPLL_EXT_100M 0x0000001F 68 /* MPLL configuration */ 69 #if defined(CONFIG_ASPEED_DDR4_1600) 70 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 71 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 72 #elif defined(CONFIG_ASPEED_DDR4_1333) 73 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 74 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 75 #elif defined(CONFIG_ASPEED_DDR4_800) 76 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 77 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 78 #elif defined(CONFIG_ASPEED_DDR4_400) 79 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 80 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 81 #else 82 #error "undefined DDR4 target rate\n" 83 #endif 84 85 /* AC timing and SDRAM mode registers */ 86 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 87 /* mode register settings for FPGA are fixed */ 88 #define DDR4_MR01_MODE 0x03010100 89 #define DDR4_MR23_MODE 0x00000000 90 #define DDR4_MR45_MODE 0x04C00000 91 #define DDR4_MR6_MODE 0x00000050 92 #define DDR4_TRFC_FPGA 0x17263434 93 94 /* FPGA need for an additional initialization procedure: search read window */ 95 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 96 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 97 #define SEARCH_RDWIN_PTRN_0 0x12345678 98 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 99 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 100 #else 101 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 102 #define DDR4_MR01_MODE 0x03010510 103 #define DDR4_MR23_MODE 0x00000000 104 #define DDR4_MR45_MODE 0x04000000 105 #define DDR4_MR6_MODE 0x00000400 106 #define DDR4_TRFC_1600 0x467299f1 107 #define DDR4_TRFC_1333 0x3a5f80c9 108 #define DDR4_TRFC_800 0x23394c78 109 #define DDR4_TRFC_400 0x111c263c 110 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 111 defined(CONFIG_ASPEED_PALLADIUM)" */ 112 113 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 114 #define DDR4_TRFC DDR4_TRFC_FPGA 115 #else 116 /* real chip setting */ 117 #if defined(CONFIG_ASPEED_DDR4_1600) 118 #define DDR4_TRFC DDR4_TRFC_1600 119 #define DDR4_PHY_TRAIN_TRFC 0xc30 120 #elif defined(CONFIG_ASPEED_DDR4_1333) 121 #define DDR4_TRFC DDR4_TRFC_1333 122 #define DDR4_PHY_TRAIN_TRFC 0xa25 123 #elif defined(CONFIG_ASPEED_DDR4_800) 124 #define DDR4_TRFC DDR4_TRFC_800 125 #define DDR4_PHY_TRAIN_TRFC 0x618 126 #elif defined(CONFIG_ASPEED_DDR4_400) 127 #define DDR4_TRFC DDR4_TRFC_400 128 #define DDR4_PHY_TRAIN_TRFC 0x30c 129 #else 130 #error "undefined tRFC setting" 131 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 132 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 133 defined(CONFIG_ASPEED_PALLADIUM)" */ 134 135 /* supported SDRAM size */ 136 #define SDRAM_SIZE_1KB (1024U) 137 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 138 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 139 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 140 141 142 DECLARE_GLOBAL_DATA_PTR; 143 144 /* 145 * Bandwidth configuration parameters for different SDRAM requests. 146 * These are hardcoded settings taken from Aspeed SDK. 147 */ 148 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 149 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 150 0x00000140 }; 151 152 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 153 0x88888888 }; 154 #else 155 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 156 0x00001240 }; 157 158 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 159 0x44444444 }; 160 #endif 161 162 struct dram_info { 163 struct ram_info info; 164 struct clk ddr_clk; 165 struct ast2600_sdrammc_regs *regs; 166 void __iomem *scu; 167 struct ast2600_ddr_phy *phy; 168 void __iomem *phy_setting; 169 void __iomem *phy_status; 170 ulong clock_rate; 171 }; 172 173 static void ast2600_sdramphy_kick_training(struct dram_info *info) 174 { 175 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 176 struct ast2600_sdrammc_regs *regs = info->regs; 177 u32 volatile data; 178 179 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 180 udelay(5); 181 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 182 udelay(1000); 183 184 while (1) { 185 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 186 if (~data) { 187 break; 188 } 189 } 190 191 #if 0 192 while (1) { 193 data = readl(0x1e6e0400) & BIT(1); 194 if (data) { 195 break; 196 } 197 } 198 #endif 199 #endif 200 } 201 202 /** 203 * @brief load DDR-PHY configurations table to the PHY registers 204 * @param[in] p_tbl - pointer to the configuration table 205 * @param[in] info - pointer to the DRAM info struct 206 * 207 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 208 * system: one is in the SDRAM MC (memory controller) which is used in run 209 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 210 * training. 211 */ 212 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 213 { 214 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 215 u32 reg_base = (u32)info->phy_setting; 216 u32 addr = p_tbl[0]; 217 u32 data; 218 int i = 1; 219 220 writel(0, &info->regs->phy_ctrl[0]); 221 udelay(10); 222 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 223 224 /* load PHY configuration table into PHY-setting registers */ 225 while (1) { 226 if (addr < reg_base) { 227 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 228 break; 229 } 230 data = p_tbl[i++]; 231 232 if (data == DDR_PHY_TBL_END) { 233 break; 234 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 235 addr = p_tbl[i++]; 236 } else { 237 writel(data, addr); 238 addr += 4; 239 } 240 } 241 242 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 243 data |= DDR4_PHY_TRAIN_TRFC; 244 writel(data, info->phy_setting + 0x84); 245 #endif 246 } 247 248 static int ast2600_sdramphy_check_status(struct dram_info *info) 249 { 250 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 251 u32 value, tmp; 252 u32 reg_base = (u32)info->phy_status; 253 int need_retrain = 0; 254 255 debug("\nSDRAM PHY training report:\n"); 256 /* training status */ 257 value = readl(reg_base + 0x00); 258 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 259 if (value & BIT(3)) { 260 debug("\tinitial PVT calibration fail\n"); 261 } 262 if (value & BIT(5)) { 263 debug("\truntime calibration fail\n"); 264 } 265 266 /* PU & PD */ 267 value = readl(reg_base + 0x30); 268 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 269 debug(" PU = 0x%02x\n", value & 0xff); 270 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 271 272 /* read eye window */ 273 value = readl(reg_base + 0x68); 274 if (0 == (value & GENMASK(7, 0))) { 275 need_retrain = 1; 276 } 277 278 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 279 debug(" rising edge of read data eye training pass window\n"); 280 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 281 debug(" B0:%d%%\n", tmp); 282 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 283 debug(" B1:%d%%\n", tmp); 284 285 value = readl(reg_base + 0xC8); 286 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 287 debug(" falling edge of read data eye training pass window\n"); 288 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 289 debug(" B0:%d%%\n", tmp); 290 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 291 debug(" B1:%d%%\n", tmp); 292 293 /* write eye window */ 294 value = readl(reg_base + 0x7c); 295 if (0 == (value & GENMASK(7, 0))) { 296 need_retrain = 1; 297 } 298 299 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 300 debug(" rising edge of write data eye training pass window\n"); 301 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 302 debug(" B0:%d%%\n", tmp); 303 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 304 debug(" B1:%d%%\n", tmp); 305 306 /* read Vref (PHY side) training result */ 307 value = readl(reg_base + 0x88); 308 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 309 310 /* write Vref (DRAM side) training result */ 311 value = readl(reg_base + 0x90); 312 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 313 314 /* gate train */ 315 value = readl(reg_base + 0x50); 316 if ((0 == (value & GENMASK(15, 0))) || 317 (0 == (value & GENMASK(31, 16)))) { 318 need_retrain = 1; 319 } 320 #if 0 321 if (((value >> 24) & 0xff) < 3) 322 need_retrain = 1; 323 else 324 need_retrain = 0; 325 #endif 326 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 327 #if 0 328 debug(" gate training pass window\n"); 329 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 330 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 331 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 332 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 333 #endif 334 335 return need_retrain; 336 #else 337 return 0; 338 #endif 339 } 340 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 341 #define MC_TEST_PATTERN_N 8 342 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 343 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 344 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 345 }; 346 347 #define TIMEOUT_DRAM 5000000 348 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 349 { 350 unsigned int data; 351 unsigned int timeout = 0; 352 struct ast2600_sdrammc_regs *regs = info->regs; 353 354 writel(0, ®s->ecc_test_ctrl); 355 if (mode == 0) 356 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 357 else 358 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 359 360 do { 361 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 362 363 if (data & BIT(13)) 364 return 0; 365 366 if (++timeout > TIMEOUT_DRAM) { 367 printf("Timeout!!\n"); 368 writel(0, ®s->ecc_test_ctrl); 369 370 return 0; 371 } 372 } while (!data); 373 374 writel(0, ®s->ecc_test_ctrl); 375 376 return 1; 377 } 378 379 int ast2600_sdrammc_cbr_test(struct dram_info *info) 380 { 381 struct ast2600_sdrammc_regs *regs = info->regs; 382 u32 i; 383 384 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 385 386 /* single */ 387 for (i = 0; i < 8; i++) { 388 if (!ast2600_sdrammc_dg_test(info, i, 0)) 389 return (0); 390 } 391 392 /* burst */ 393 for (i = 0; i < 8; i++) { 394 if (!ast2600_sdrammc_dg_test(info, i, i)) 395 return (0); 396 } 397 398 return(1); 399 } 400 401 static int ast2600_sdrammc_test(struct dram_info *info) 402 { 403 struct ast2600_sdrammc_regs *regs = info->regs; 404 405 u32 pass_cnt = 0; 406 u32 fail_cnt = 0; 407 u32 target_cnt = 2; 408 u32 test_cnt = 0; 409 u32 pattern; 410 u32 i = 0; 411 bool finish = false; 412 413 debug("sdram mc test:\n"); 414 while (finish == false) { 415 pattern = as2600_sdrammc_test_pattern[i++]; 416 i = i % MC_TEST_PATTERN_N; 417 debug(" pattern = %08X : ", pattern); 418 writel(pattern, ®s->test_init_val); 419 420 if (!ast2600_sdrammc_cbr_test(info)) { 421 debug("fail\n"); 422 fail_cnt++; 423 } else { 424 debug("pass\n"); 425 pass_cnt++; 426 } 427 428 if (++test_cnt == target_cnt) { 429 finish = true; 430 } 431 } 432 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 433 target_cnt); 434 return fail_cnt; 435 } 436 #endif 437 /** 438 * scu500[14:13] 439 * 2b'00: VGA memory size = 16MB 440 * 2b'01: VGA memory size = 16MB 441 * 2b'10: VGA memory size = 32MB 442 * 2b'11: VGA memory size = 64MB 443 * 444 * mcr04[3:2] 445 * 2b'00: VGA memory size = 8MB 446 * 2b'01: VGA memory size = 16MB 447 * 2b'10: VGA memory size = 32MB 448 * 2b'11: VGA memory size = 64MB 449 */ 450 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 451 { 452 u32 vga_hwconf; 453 size_t vga_mem_size_base = 8 * 1024 * 1024; 454 455 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 456 SCU_HWSTRAP_VGAMEM_MASK) >> 457 SCU_HWSTRAP_VGAMEM_SHIFT; 458 459 if (vga_hwconf == 0) { 460 vga_hwconf = 1; 461 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 462 info->scu + AST_SCU_HW_STRAP); 463 } 464 465 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 466 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 467 SDRAM_CONF_VGA_SIZE_MASK)); 468 469 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 470 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 471 return 0; 472 473 return vga_mem_size_base << vga_hwconf; 474 } 475 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 476 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 477 { 478 u32 data; 479 u32 scu_base = (u32)info->scu; 480 481 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 482 483 do { 484 data = readl(scu_base + AST_SCU_FPGA_STATUS); 485 } while (!(data & 0x100)); 486 487 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 488 } 489 490 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 491 { 492 u32 pll, pll_min, pll_max, dat1, offset; 493 u32 win = 0x03, gwin = 0, gwinsize = 0; 494 u32 phy_setting = (u32)info->phy_setting; 495 496 #ifdef CONFIG_ASPEED_PALLADIUM 497 writel(0xc, phy_setting + 0x0000); 498 return 1; 499 #endif 500 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 501 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 502 503 while (gwin == 0) { 504 while (!(win & 0x80)) { 505 debug("Window = 0x%X\n", win); 506 writel(win, phy_setting + 0x0000); 507 508 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 509 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 510 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 511 ast2600_sdrammc_fpga_set_pll(info); 512 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 513 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 514 } 515 516 pll_min = 0xfff; 517 pll_max = 0x0; 518 pll = 0; 519 while (pll_max > 0 || pll < 256) { 520 ast2600_sdrammc_fpga_set_pll(info); 521 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 522 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 523 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 524 if (pll_min > pll) 525 pll_min = pll; 526 527 if (pll_max < pll) 528 pll_max = pll; 529 530 debug("%3d_(%3d:%3d)\n", pll, pll_min, 531 pll_max); 532 } else if (pll_max > 0) { 533 pll_min = pll_max - pll_min; 534 if (gwinsize < pll_min) { 535 gwin = win; 536 gwinsize = pll_min; 537 } 538 break; 539 } 540 pll += 1; 541 } 542 543 if (gwin != 0 && pll_max == 0) 544 break; 545 546 win = win << 1; 547 } 548 if (gwin == 0) 549 win = 0x7; 550 } 551 debug("Set PLL Read Gating Window = %x\n", gwin); 552 writel(gwin, phy_setting + 0x0000); 553 554 debug("PLL Read Window training\n"); 555 pll_min = 0xfff; 556 pll_max = 0x0; 557 558 debug("Search Window Start\n"); 559 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 560 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 561 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 562 ast2600_sdrammc_fpga_set_pll(info); 563 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 564 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 565 } 566 567 debug("Search Window Margin\n"); 568 pll = 0; 569 while (pll_max > 0 || pll < 256) { 570 ast2600_sdrammc_fpga_set_pll(info); 571 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 572 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 573 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 574 if (pll_min > pll) 575 pll_min = pll; 576 577 if (pll_max < pll) 578 pll_max = pll; 579 580 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 581 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 582 break; 583 } else if (pll_max > 0) { 584 pll_min = 0xfff; 585 pll_max = 0x0; 586 } 587 pll += 1; 588 } 589 if (pll_min < pll_max) { 590 debug("PLL Read window = %d\n", (pll_max - pll_min)); 591 offset = (pll_max - pll_min) >> 1; 592 pll_min = 0xfff; 593 pll = 0; 594 while (pll < (pll_min + offset)) { 595 ast2600_sdrammc_fpga_set_pll(info); 596 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 597 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 598 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 599 if (pll_min > pll) { 600 pll_min = pll; 601 } 602 debug("%d\n", pll); 603 } else { 604 pll_min = 0xfff; 605 pll_max = 0x0; 606 } 607 pll += 1; 608 } 609 return (1); 610 } else { 611 debug("PLL Read window training fail\n"); 612 return 0; 613 } 614 } 615 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 616 defined(CONFIG_ASPEED_PALLADIUM)" */ 617 618 /* 619 * Find out RAM size and save it in dram_info 620 * 621 * The procedure is taken from Aspeed SDK 622 */ 623 static void ast2600_sdrammc_calc_size(struct dram_info *info) 624 { 625 /* The controller supports 256/512/1024/2048 MB ram */ 626 size_t ram_size = SDRAM_MIN_SIZE; 627 const int write_test_offset = 0x100000; 628 u32 test_pattern = 0xdeadbeef; 629 u32 cap_param = SDRAM_CONF_CAP_2048M; 630 u32 refresh_timing_param = DDR4_TRFC; 631 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 632 633 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 634 ram_size >>= 1) { 635 writel(test_pattern, write_addr_base + (ram_size >> 1)); 636 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 637 } 638 639 /* One last write to overwrite all wrapped values */ 640 writel(test_pattern, write_addr_base); 641 642 /* Reset the pattern and see which value was really written */ 643 test_pattern = 0xdeadbeef; 644 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 645 ram_size >>= 1) { 646 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 647 break; 648 649 --cap_param; 650 refresh_timing_param >>= 8; 651 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 652 } 653 654 clrsetbits_le32(&info->regs->ac_timing[1], 655 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 656 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 657 << SDRAM_AC_TRFC_SHIFT)); 658 659 info->info.base = CONFIG_SYS_SDRAM_BASE; 660 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 661 662 clrsetbits_le32( 663 &info->regs->config, SDRAM_CONF_CAP_MASK, 664 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 665 } 666 667 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 668 { 669 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 670 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 671 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 672 (0x1 << MCR34_ODT_EXT_SHIFT); 673 674 /* init SDRAM-PHY only on real chip */ 675 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 676 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 677 &info->regs->power_ctrl); 678 udelay(5); 679 ast2600_sdramphy_kick_training(info); 680 udelay(500); 681 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 682 683 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 684 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 685 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 686 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 687 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 688 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 689 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 690 &info->regs->mode_setting_control); 691 692 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 693 694 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 695 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 696 &info->regs->refresh_timing); 697 #else 698 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 699 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 700 &info->regs->refresh_timing); 701 #endif 702 703 /* wait self-refresh idle */ 704 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 705 ; 706 707 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 708 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 709 SDRAM_REFRESH_ZQCS_EN | 710 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 711 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 712 &info->regs->refresh_timing); 713 #else 714 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 715 SDRAM_REFRESH_ZQCS_EN | 716 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 717 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 718 &info->regs->refresh_timing); 719 #endif 720 721 writel(power_ctrl, &info->regs->power_ctrl); 722 udelay(500); 723 724 #if defined(CONFIG_FPGA_ASPEED) 725 /* toggle Vref training */ 726 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 727 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 728 &info->regs->mode_setting_control); 729 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 730 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 731 &info->regs->mode_setting_control); 732 #endif 733 return 0; 734 } 735 736 static void ast2600_sdrammc_unlock(struct dram_info *info) 737 { 738 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 739 while (!readl(&info->regs->protection_key)) 740 ; 741 } 742 743 static void ast2600_sdrammc_lock(struct dram_info *info) 744 { 745 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 746 while (readl(&info->regs->protection_key)) 747 ; 748 } 749 750 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 751 { 752 int i; 753 754 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 755 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 756 /* [6:0] : Group 1 request queued number = 16 757 * [14:8] : Group 2 request queued number = 16 758 * [20:16] : R/W max-grant count for RQ output arbitration = 16 759 */ 760 writel(0x101010, ®s->arbitration_ctrl); 761 /* Request Queued Limitation for REQ8/9 USB1/2 */ 762 writel(0x0FFF3CEF, ®s->req_limit_mask); 763 764 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 765 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 766 767 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 768 769 /* FIXME: the sample code does NOT match the datasheet */ 770 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 771 772 writel(0, ®s->ecc_test_ctrl); 773 writel(0x80000001, ®s->test_addr); 774 writel(0, ®s->test_fail_dq_bit); 775 writel(0, ®s->test_init_val); 776 777 writel(0xFFFFFFFF, ®s->req_input_ctrl); 778 writel(0x300, ®s->req_high_pri_ctrl); 779 780 udelay(600); 781 782 #ifdef CONFIG_ASPEED_DDR4_DUALX8 783 writel(0xa037, ®s->config); 784 #else 785 writel(0xa017, ®s->config); 786 #endif 787 788 /* load controller setting */ 789 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 790 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 791 792 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 793 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 794 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 795 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 796 } 797 /* 798 * Update size info according to the ECC HW setting 799 * 800 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 801 * don't need to calculate the ECC size again but read from MCR04 and derive the 802 * size from its value. 803 */ 804 static void ast2600_sdrammc_update_size(struct dram_info *info) 805 { 806 struct ast2600_sdrammc_regs *regs = info->regs; 807 size_t hw_size; 808 size_t ram_size = SDRAM_MAX_SIZE; 809 u32 cap_param; 810 811 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 812 switch (cap_param) 813 { 814 case SDRAM_CONF_CAP_2048M: 815 ram_size = 2048 * SDRAM_SIZE_1MB; 816 break; 817 case SDRAM_CONF_CAP_1024M: 818 ram_size = 1024 * SDRAM_SIZE_1MB; 819 break; 820 case SDRAM_CONF_CAP_512M: 821 ram_size = 512 * SDRAM_SIZE_1MB; 822 break; 823 case SDRAM_CONF_CAP_256M: 824 ram_size = 256 * SDRAM_SIZE_1MB; 825 break; 826 } 827 828 info->info.base = CONFIG_SYS_SDRAM_BASE; 829 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 830 831 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 832 return; 833 834 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 835 hw_size += (1 << 20); 836 837 info->info.size = hw_size; 838 } 839 #ifdef CONFIG_ASPEED_ECC 840 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 841 { 842 struct ast2600_sdrammc_regs *regs = info->regs; 843 size_t conf_size; 844 u32 reg; 845 846 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 847 if (conf_size > info->info.size) { 848 printf("warning: ECC configured %dMB but actual size is %dMB\n", 849 CONFIG_ASPEED_ECC_SIZE, 850 info->info.size / SDRAM_SIZE_1MB); 851 conf_size = info->info.size; 852 } else if (conf_size == 0) { 853 conf_size = info->info.size; 854 } 855 856 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 857 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 858 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 859 writel(reg, ®s->config); 860 861 writel(0, ®s->test_init_val); 862 writel(0x80000001, ®s->test_addr); 863 writel(0x221, ®s->ecc_test_ctrl); 864 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 865 ; 866 writel(0, ®s->ecc_test_ctrl); 867 writel(BIT(31), ®s->intr_ctrl); 868 writel(0, ®s->intr_ctrl); 869 } 870 #endif 871 872 static int ast2600_sdrammc_probe(struct udevice *dev) 873 { 874 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 875 struct ast2600_sdrammc_regs *regs = priv->regs; 876 struct udevice *clk_dev; 877 int ret; 878 volatile uint32_t reg; 879 880 /* find SCU base address from clock device */ 881 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 882 &clk_dev); 883 if (ret) { 884 debug("clock device not defined\n"); 885 return ret; 886 } 887 888 priv->scu = devfdt_get_addr_ptr(clk_dev); 889 if (IS_ERR(priv->scu)) { 890 debug("%s(): can't get SCU\n", __func__); 891 return PTR_ERR(priv->scu); 892 } 893 894 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 895 printf("already initialized, "); 896 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 897 ast2600_sdrammc_update_size(priv); 898 return 0; 899 } 900 901 #ifdef AST2600_SDRAMMC_MANUAL_CLK 902 reg = readl(priv->scu + AST_SCU_MPLL); 903 reg &= ~(BIT(24) | GENMASK(22, 0)); 904 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 905 writel(reg, priv->scu + AST_SCU_MPLL); 906 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 907 udelay(100); 908 reg &= ~(BIT(25) | BIT(23)); 909 writel(reg, priv->scu + AST_SCU_MPLL); 910 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 911 ; 912 #else 913 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 914 if (ret) { 915 debug("DDR:No CLK\n"); 916 return ret; 917 } 918 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 919 #endif 920 921 #if 0 922 /* FIXME: enable the following code if reset-driver is ready */ 923 struct reset_ctl reset_ctl; 924 ret = reset_get_by_index(dev, 0, &reset_ctl); 925 if (ret) { 926 debug("%s(): Failed to get reset signal\n", __func__); 927 return ret; 928 } 929 930 ret = reset_assert(&reset_ctl); 931 if (ret) { 932 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 933 return ret; 934 } 935 #endif 936 937 ast2600_sdrammc_unlock(priv); 938 ast2600_sdrammc_common_init(regs); 939 L_ast2600_sdramphy_train: 940 ast2600_sdrammc_init_ddr4(priv); 941 942 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 943 ast2600_sdrammc_search_read_window(priv); 944 #else 945 /* make sure DDR-PHY is ready before access */ 946 do { 947 reg = readl(priv->phy_status) & BIT(1); 948 } while (reg == 0); 949 #endif 950 951 if (0 != ast2600_sdramphy_check_status(priv)) { 952 printf("DDR4 PHY training fail, retrain\n"); 953 goto L_ast2600_sdramphy_train; 954 } 955 956 ast2600_sdrammc_calc_size(priv); 957 958 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 959 if (0 != ast2600_sdrammc_test(priv)) { 960 printf("%s: DDR4 init fail\n", __func__); 961 return -EINVAL; 962 } 963 #endif 964 965 #ifdef CONFIG_ASPEED_ECC 966 ast2600_sdrammc_ecc_enable(priv); 967 #endif 968 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 969 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 970 ast2600_sdrammc_lock(priv); 971 return 0; 972 } 973 974 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 975 { 976 struct dram_info *priv = dev_get_priv(dev); 977 978 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 979 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 980 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 981 982 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 983 "clock-frequency", 0); 984 if (!priv->clock_rate) { 985 debug("DDR Clock Rate not defined\n"); 986 return -EINVAL; 987 } 988 989 return 0; 990 } 991 992 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 993 { 994 struct dram_info *priv = dev_get_priv(dev); 995 996 *info = priv->info; 997 998 return 0; 999 } 1000 1001 static struct ram_ops ast2600_sdrammc_ops = { 1002 .get_info = ast2600_sdrammc_get_info, 1003 }; 1004 1005 static const struct udevice_id ast2600_sdrammc_ids[] = { 1006 { .compatible = "aspeed,ast2600-sdrammc" }, 1007 { } 1008 }; 1009 1010 U_BOOT_DRIVER(sdrammc_ast2600) = { 1011 .name = "aspeed_ast2600_sdrammc", 1012 .id = UCLASS_RAM, 1013 .of_match = ast2600_sdrammc_ids, 1014 .ops = &ast2600_sdrammc_ops, 1015 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1016 .probe = ast2600_sdrammc_probe, 1017 .priv_auto_alloc_size = sizeof(struct dram_info), 1018 }; 1019