1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2600.h> 17 #include <asm/arch/sdram_ast2600.h> 18 #include <linux/err.h> 19 #include <linux/kernel.h> 20 #include <dt-bindings/clock/ast2600-clock.h> 21 #include "sdram_phy_ast2600.h" 22 23 /* in order to speed up DRAM init time, write pre-defined values to registers 24 * directly */ 25 #define AST2600_SDRAMMC_MANUAL_CLK 26 27 #ifdef CONFIG_FPGA_ASPEED 28 /* mode register settings for FPGA are fixed */ 29 #define DDR4_MR01_MODE 0x03010100 30 #define DDR4_MR23_MODE 0x00000000 31 #define DDR4_MR45_MODE 0x04C00000 32 #define DDR4_MR6_MODE 0x00000050 33 #define DDR4_TRFC_FPGA 0x17263434 34 35 /* FPGA need for an additional initialization procedure: search read window */ 36 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 37 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 38 #define SEARCH_RDWIN_PTRN_0 0x12345678 39 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 40 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 41 #else 42 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 43 #define DDR4_MR01_MODE 0x03010510 44 #define DDR4_MR23_MODE 0x00000000 45 #define DDR4_MR45_MODE 0x04000000 46 #define DDR4_MR6_MODE 0x00000400 47 #define DDR4_TRFC_1600 0x467299f1 48 #define DDR4_TRFC_800 0x23394c78 49 #endif /* end of "#ifdef CONFIG_FPGA_ASPEED" */ 50 51 #define SDRAM_SIZE_1KB (1024U) 52 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 53 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 54 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 55 56 /* register offset */ 57 #define AST_SCU_FPGA_STATUS 0x004 58 #define AST_SCU_HANDSHAKE 0x100 59 #define AST_SCU_MPLL 0x220 60 #define AST_SCU_FPGA_PLL 0x400 61 #define AST_SCU_HW_STRAP 0x500 62 63 /* bit-field of AST_SCU_HW_STRAP */ 64 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 65 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 66 #define SCU_HWSTRAP_DDR3 (1 << 25) 67 68 69 /* bit-field of AST_SCU_HANDSHAKE */ 70 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 71 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 72 73 74 /* bit-field of AST_SCU_MPLL */ 75 #define SCU_MPLL_FREQ_MASK 0x007FFFFF /* bit[22:0] */ 76 #define SCU_MPLL_FREQ_400M 0x0008405F /* 0x0038007F */ 77 #define SCU_MPLL_FREQ_200M 0x0078007F 78 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 79 80 #if defined(CONFIG_FPGA_ASPEED) 81 #define DDR4_TRFC DDR4_TRFC_FPGA 82 #else 83 /* real chip setting */ 84 #if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M) 85 #define DDR4_TRFC DDR4_TRFC_1600 86 #elif (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_200M) 87 #define DDR4_TRFC DDR4_TRFC_800 88 #else 89 #error "undefined tRFC setting" 90 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 91 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED)" */ 92 93 #define SCU_MPLL_TURN_OFF BIT(23) 94 #define SCU_MPLL_BYPASS BIT(24) 95 #define SCU_MPLL_RESET BIT(25) 96 97 DECLARE_GLOBAL_DATA_PTR; 98 99 /* 100 * Bandwidth configuration parameters for different SDRAM requests. 101 * These are hardcoded settings taken from Aspeed SDK. 102 */ 103 #ifdef CONFIG_FPGA_ASPEED 104 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 105 0x00000140}; 106 107 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 108 0x88888888}; 109 #else 110 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 111 0x00001240}; 112 113 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 114 0x44444444}; 115 #endif 116 117 struct dram_info { 118 struct ram_info info; 119 struct clk ddr_clk; 120 struct ast2600_sdrammc_regs *regs; 121 void __iomem *scu; 122 struct ast2600_ddr_phy *phy; 123 void __iomem *phy_setting; 124 void __iomem *phy_status; 125 ulong clock_rate; 126 }; 127 128 static void ast2600_sdramphy_kick_training(struct dram_info *info) 129 { 130 #ifndef CONFIG_FPGA_ASPEED 131 struct ast2600_sdrammc_regs *regs = info->regs; 132 u32 mask = SDRAM_PHYCTRL0_INIT | SDRAM_PHYCTRL0_PLL_LOCKED; 133 u32 data; 134 135 writel(0, ®s->phy_ctrl[0]); 136 udelay(2); 137 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 138 139 /* wait for (PLL_LOCKED == 1) and (INIT == 0) */ 140 do { 141 data = readl(®s->phy_ctrl[0]) & mask; 142 } while (SDRAM_PHYCTRL0_PLL_LOCKED != data); 143 #endif 144 } 145 146 /** 147 * @brief load DDR-PHY configurations table to the PHY registers 148 * @param[in] p_tbl - pointer to the configuration table 149 * @param[in] info - pointer to the DRAM info struct 150 * 151 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 152 * system: one is in the SDRAM MC (memory controller) which is used in run 153 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 154 * training. To make these two configurations align, we overwrite the DDR-PHY 155 * setting by the MC setting before DDR-PHY training. 156 */ 157 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 158 { 159 #ifndef CONFIG_FPGA_ASPEED 160 u32 reg_base = (u32)info->phy_setting; 161 u32 addr = p_tbl[0]; 162 u32 data; 163 int i = 1; 164 165 debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, 166 addr); 167 168 /* load PHY configuration table into PHY-setting registers */ 169 while (1) { 170 if (addr < reg_base) { 171 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 172 break; 173 } 174 data = p_tbl[i++]; 175 176 if (DDR_PHY_TBL_END == data) { 177 break; 178 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 179 addr = p_tbl[i++]; 180 } else { 181 writel(data, addr); 182 addr += 4; 183 } 184 } 185 186 printf("Overwrite DDR-PHY MRS by MCR config\n"); 187 /* MR0 and MR1 */ 188 data = readl(&info->regs->mr01_mode_setting); 189 data = 190 ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16); 191 writel(data, reg_base + 0x58); 192 debug("[%08x] 0x%08x\n", reg_base + 0x58, data); 193 194 /* MR2 and MR3 */ 195 data = readl(&info->regs->mr23_mode_setting); 196 writel(data, reg_base + 0x54); 197 debug("[%08x] 0x%08x\n", reg_base + 0x54, data); 198 199 /* MR4 and MR5 */ 200 data = readl(&info->regs->mr45_mode_setting); 201 writel(data, reg_base + 0x5c); 202 debug("[%08x] 0x%08x\n", reg_base + 0x5c, data); 203 204 /* MR6 */ 205 data = readl(&info->regs->mr6_mode_setting); 206 writel(data, reg_base + 0x60); 207 debug("[%08x] 0x%08x\n", reg_base + 0x60, data); 208 #endif 209 } 210 211 static void ast2600_sdramphy_show_status(struct dram_info *info) 212 { 213 #ifndef CONFIG_FPGA_ASPEED 214 u32 value; 215 u32 reg_base = (u32)info->phy_status; 216 217 debug("%s:reg base = 0x%08x\n", __func__, reg_base); 218 219 value = readl(reg_base + 0x00); 220 if (value & BIT(3)) { 221 debug("initial PVT calibration fail\n"); 222 } 223 if (value & BIT(5)) { 224 debug("runtime calibration fail\n"); 225 } 226 227 value = readl(reg_base + 0x30); 228 debug("IO PU = 0x%02x\n", value & 0xff); 229 debug("IO PD = 0x%02x\n", (value >> 16) & 0xff); 230 231 value = readl(reg_base + 0x88); 232 debug("PHY vref: 0x%02x_%02x\n", value & 0xff, (value >> 8) & 0xff); 233 value = readl(reg_base + 0x90); 234 debug("DDR vref: 0x%02x\n", value & 0x3f); 235 236 value = readl(reg_base + 0x40); 237 debug("MLB Gate training result: 0x%04x_%04x\n", value & 0xffff, 238 (value >> 16) & 0xffff); 239 value = readl(reg_base + 0x50); 240 debug("MLB Gate pass window: 0x%04x_%04x\n", value & 0xffff, 241 (value >> 16) & 0xffff); 242 value = readl(reg_base + 0x60); 243 debug("Rising edge Read Data Eye Training Result = 0x%x_%x\n", 244 value & 0xff, (value >> 8) & 0xff); 245 246 value = readl(reg_base + 0x68); 247 debug("Rising edge Read Data Eye Training Pass Window = 0x%x_%x\n", 248 value & 0xff, (value >> 8) & 0xff); 249 250 value = readl(reg_base + 0xC0); 251 debug("Falling edge Read Data Eye Training Result = 0x%x_%x\n", 252 value & 0xff, (value >> 8) & 0xff); 253 254 value = readl(reg_base + 0xC8); 255 debug("Falling edge Read Data Eye Training Pass Window = 0x%x_%x\n", 256 value & 0xff, (value >> 8) & 0xff); 257 258 value = readl(reg_base + 0x74); 259 debug("Write Data Eye fine Training Result = %X_%X\n", 260 value & 0xff, (value >> 8) & 0xff); 261 262 value = readl(reg_base + 0x7C); 263 debug("Write Data Eye Training Pass Window = 0x%x_%x\n", 264 value & 0xff, (value >> 8) & 0xff); 265 #endif 266 } 267 268 /** 269 * @brief SDRAM memory controller test mode with data-generation 270 * @param[in] - info - pointer to the current dram_info 271 * @param[in] - data_gen - data_gen index 272 * @param[in] - mode - 0:single, 1:burst 273 * @return - 0:success, others:fail 274 */ 275 static int ast2600_sdrammc_dg_test(struct dram_info *info, u32 data_gen, 276 u32 mode) 277 { 278 u32 data; 279 u32 mask; 280 struct ast2600_sdrammc_regs *regs = info->regs; 281 282 writel(0, ®s->ecc_test_ctrl); 283 data = (data_gen << SDRAM_TEST_GEN_MODE_SHIFT) | SDRAM_TEST_ERRSTOP | 284 SDRAM_TEST_EN; 285 if (mode) { 286 data |= 287 (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | SDRAM_TEST_MODE_RW); 288 } else { 289 data |= (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | 290 SDRAM_TEST_MODE_WO | SDRAM_TEST_TWO_MODES); 291 } 292 writel(data, ®s->ecc_test_ctrl); 293 294 mask = SDRAM_TEST_DONE | SDRAM_TEST_FAIL; 295 do { 296 data = readl(®s->ecc_test_ctrl) & mask; 297 if (data & SDRAM_TEST_FAIL) { 298 debug("%s %d fail\n", __func__, data_gen); 299 return 1; 300 } 301 } while (!data); 302 303 writel(0x00000000, ®s->ecc_test_ctrl); 304 return 0; 305 } 306 307 static int ast2600_sdrammc_cbr_test(struct dram_info *info, u32 pattern) 308 { 309 struct ast2600_sdrammc_regs *regs = info->regs; 310 int i; 311 int ret = 0; 312 313 writel((0xff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); 314 writel(pattern, ®s->test_init_val); 315 316 /* scan all data-generation mode */ 317 for (i = 0; i < 8; i++) { 318 if (0 == ast2600_sdrammc_dg_test(info, i, 0)) { 319 debug("sdrammc calibration test fail: single data " 320 "mode\n"); 321 ret = 1; 322 break; 323 } 324 } 325 326 for (i = 0; i < 8; i++) { 327 if (0 == ast2600_sdrammc_dg_test(info, i, 1)) { 328 debug( 329 "sdrammc calibration test fail: burst data mode\n"); 330 ret = 1; 331 break; 332 } 333 } 334 335 writel(0, ®s->ecc_test_ctrl); 336 return ret; 337 } 338 339 #define MC_TEST_PATTERN_N 8 340 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 341 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 342 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 343 344 static int ast2600_sdrammc_test(struct dram_info *info) 345 { 346 int i; 347 int ret; 348 349 for (i = 0; i < MC_TEST_PATTERN_N; i++) { 350 ret = ast2600_sdrammc_cbr_test(info, 351 as2600_sdrammc_test_pattern[i]); 352 if (ret) { 353 return ret; 354 } 355 debug("%s: pass %d\n", __func__, i); 356 } 357 358 return ret; 359 } 360 361 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 362 { 363 u32 vga_hwconf; 364 size_t vga_mem_size_base = 8 * 1024 * 1024; 365 366 vga_hwconf = readl(info->scu + AST_SCU_HW_STRAP) & 367 SCU_HWSTRAP_VGAMEM_MASK >> SCU_HWSTRAP_VGAMEM_SHIFT; 368 369 return vga_mem_size_base << vga_hwconf; 370 } 371 #ifdef CONFIG_FPGA_ASPEED 372 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 373 { 374 u32 data; 375 u32 scu_base = (u32)info->scu; 376 377 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 378 379 do { 380 data = readl(scu_base + AST_SCU_FPGA_STATUS); 381 } while (!(data & 0x100)); 382 383 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 384 } 385 386 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 387 { 388 u32 pll, pll_min, pll_max, dat1, offset; 389 u32 win = 0x03, gwin = 0, gwinsize = 0; 390 u32 phy_setting = (u32)info->phy_setting; 391 392 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 393 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 394 395 while (gwin == 0) { 396 while (!(win & 0x80)) { 397 debug("Window = 0x%X\n", win); 398 writel(win, phy_setting + 0x0000); 399 400 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 401 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 402 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 403 ast2600_sdrammc_fpga_set_pll(info); 404 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 405 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 406 } 407 408 pll_min = 0xfff; 409 pll_max = 0x0; 410 pll = 0; 411 while (pll_max > 0 || pll < 256) { 412 ast2600_sdrammc_fpga_set_pll(info); 413 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 414 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 415 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 416 if (pll_min > pll) { 417 pll_min = pll; 418 } 419 if (pll_max < pll) { 420 pll_max = pll; 421 } 422 debug("%3d_(%3d:%3d)\n", pll, pll_min, 423 pll_max); 424 } else if (pll_max > 0) { 425 pll_min = pll_max - pll_min; 426 if (gwinsize < pll_min) { 427 gwin = win; 428 gwinsize = pll_min; 429 } 430 break; 431 } 432 pll += 1; 433 } 434 435 if (gwin != 0 && pll_max == 0) { 436 break; 437 } 438 win = win << 1; 439 } 440 if (gwin == 0) { 441 win = 0x7; 442 } 443 } 444 debug("Set PLL Read Gating Window = %x\n", gwin); 445 writel(gwin, phy_setting + 0x0000); 446 447 debug("PLL Read Window training\n"); 448 pll_min = 0xfff; 449 pll_max = 0x0; 450 451 debug("Search Window Start\n"); 452 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 453 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 454 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 455 ast2600_sdrammc_fpga_set_pll(info); 456 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 457 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 458 } 459 460 debug("Search Window Margin\n"); 461 pll = 0; 462 while (pll_max > 0 || pll < 256) { 463 ast2600_sdrammc_fpga_set_pll(info); 464 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 465 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 466 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 467 if (pll_min > pll) { 468 pll_min = pll; 469 } 470 if (pll_max < pll) { 471 pll_max = pll; 472 } 473 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 474 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 475 break; 476 } else if (pll_max > 0) { 477 pll_min = 0xfff; 478 pll_max = 0x0; 479 } 480 pll += 1; 481 } 482 if (pll_min < pll_max) { 483 debug("PLL Read window = %d\n", (pll_max - pll_min)); 484 offset = (pll_max - pll_min) >> 1; 485 pll_min = 0xfff; 486 pll = 0; 487 while (pll < (pll_min + offset)) { 488 ast2600_sdrammc_fpga_set_pll(info); 489 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 490 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 491 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 492 if (pll_min > pll) { 493 pll_min = pll; 494 } 495 debug("%d\n", pll); 496 } else { 497 pll_min = 0xfff; 498 pll_max = 0x0; 499 } 500 pll += 1; 501 } 502 return (1); 503 } else { 504 debug("PLL Read window training fail\n"); 505 return (0); 506 } 507 } 508 #endif /* end of "#ifdef CONFIG_FPGA_ASPEED" */ 509 510 /* 511 * Find out RAM size and save it in dram_info 512 * 513 * The procedure is taken from Aspeed SDK 514 */ 515 static void ast2600_sdrammc_calc_size(struct dram_info *info) 516 { 517 /* The controller supports 256/512/1024/2048 MB ram */ 518 size_t ram_size = SDRAM_MIN_SIZE; 519 const int write_test_offset = 0x100000; 520 u32 test_pattern = 0xdeadbeef; 521 u32 cap_param = SDRAM_CONF_CAP_2048M; 522 u32 refresh_timing_param = DDR4_TRFC; 523 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 524 525 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 526 ram_size >>= 1) { 527 writel(test_pattern, write_addr_base + (ram_size >> 1)); 528 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 529 } 530 531 /* One last write to overwrite all wrapped values */ 532 writel(test_pattern, write_addr_base); 533 534 /* Reset the pattern and see which value was really written */ 535 test_pattern = 0xdeadbeef; 536 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 537 ram_size >>= 1) { 538 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 539 break; 540 541 --cap_param; 542 refresh_timing_param >>= 8; 543 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 544 } 545 546 clrsetbits_le32(&info->regs->ac_timing[1], 547 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 548 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 549 << SDRAM_AC_TRFC_SHIFT)); 550 551 info->info.base = CONFIG_SYS_SDRAM_BASE; 552 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 553 clrsetbits_le32(&info->regs->config, 554 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), 555 ((cap_param & SDRAM_CONF_CAP_MASK) 556 << SDRAM_CONF_CAP_SHIFT)); 557 } 558 559 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 560 { 561 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 562 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 563 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 564 (0x1 << MCR34_ODT_EXT_SHIFT); 565 566 #ifdef CONFIG_DUALX8_RAM 567 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8); 568 #else 569 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4); 570 #endif 571 572 /* init SDRAM-PHY only on real chip */ 573 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 574 ast2600_sdramphy_kick_training(info); 575 576 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 577 &info->regs->power_ctrl); 578 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 579 580 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 581 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 582 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 583 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 584 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 585 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 586 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 587 &info->regs->mode_setting_control); 588 589 #ifdef CONFIG_FPGA_ASPEED 590 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 591 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 592 &info->regs->refresh_timing); 593 #else 594 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 595 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 596 &info->regs->refresh_timing); 597 #endif 598 599 /* wait self-refresh idle */ 600 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 601 ; 602 603 #ifdef CONFIG_FPGA_ASPEED 604 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 605 SDRAM_REFRESH_ZQCS_EN | 606 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 607 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 608 &info->regs->refresh_timing); 609 #else 610 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 611 SDRAM_REFRESH_ZQCS_EN | 612 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 613 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 614 &info->regs->refresh_timing); 615 #endif 616 617 writel(power_ctrl, &info->regs->power_ctrl); 618 619 #ifdef CONFIG_FPGA_ASPEED 620 /* toggle Vref training */ 621 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 622 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 623 &info->regs->mode_setting_control); 624 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 625 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 626 &info->regs->mode_setting_control); 627 #endif 628 return 0; 629 } 630 631 static void ast2600_sdrammc_unlock(struct dram_info *info) 632 { 633 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 634 while (!readl(&info->regs->protection_key)) 635 ; 636 } 637 638 static void ast2600_sdrammc_lock(struct dram_info *info) 639 { 640 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 641 while (readl(&info->regs->protection_key)) 642 ; 643 } 644 645 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 646 { 647 int i; 648 649 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 650 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 651 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 652 ®s->arbitration_ctrl); 653 writel(0xFFFFFFFF, ®s->req_limit_mask); 654 655 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 656 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 657 658 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 659 660 /* FIXME: the sample code does NOT match the datasheet */ 661 writel(0x7FFFFFF, ®s->ecc_range_ctrl); 662 663 writel(0, ®s->ecc_test_ctrl); 664 writel(0, ®s->test_addr); 665 writel(0, ®s->test_fail_dq_bit); 666 writel(0, ®s->test_init_val); 667 668 writel(0xFFFFFFFF, ®s->req_input_ctrl); 669 writel(0, ®s->req_high_pri_ctrl); 670 671 #ifdef CONFIG_FPGA_ASPEED 672 //writel(0xFF, 0x1e6e0100); 673 #endif 674 udelay(500); 675 676 /* set capacity to the max size */ 677 clrsetbits_le32(®s->config, SDRAM_CONF_CAP_MASK, 678 SDRAM_CONF_CAP_2048M); 679 680 /* load controller setting */ 681 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 682 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 683 684 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 685 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 686 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 687 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 688 } 689 690 static int ast2600_sdrammc_probe(struct udevice *dev) 691 { 692 struct reset_ctl reset_ctl; 693 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 694 struct ast2600_sdrammc_regs *regs = priv->regs; 695 struct udevice *clk_dev; 696 int ret; 697 uint32_t reg; 698 699 /* find SCU base address from clock device */ 700 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 701 &clk_dev); 702 if (ret) { 703 debug("clock device not defined\n"); 704 return ret; 705 } 706 707 priv->scu = devfdt_get_addr_ptr(clk_dev); 708 if (IS_ERR(priv->scu)) { 709 debug("%s(): can't get SCU\n", __func__); 710 return PTR_ERR(priv->scu); 711 } 712 713 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 714 debug("%s(): DDR SDRAM had been initialized\n", __func__); 715 ast2600_sdrammc_calc_size(priv); 716 return 0; 717 } 718 719 #ifdef AST2600_SDRAMMC_MANUAL_CLK 720 reg = readl(priv->scu + AST_SCU_MPLL); 721 reg |= (SCU_MPLL_RESET | SCU_MPLL_TURN_OFF); 722 writel(reg, priv->scu + AST_SCU_MPLL); 723 reg &= ~(SCU_MPLL_RESET | SCU_MPLL_TURN_OFF| SCU_MPLL_FREQ_MASK); 724 reg |= SCU_MPLL_FREQ_CFG; 725 writel(reg, priv->scu + AST_SCU_MPLL); 726 #else 727 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 728 if (ret) { 729 debug("DDR:No CLK\n"); 730 return ret; 731 } 732 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 733 #endif 734 735 #if 0 736 /* FIXME: enable the following code if reset-driver is ready */ 737 ret = reset_get_by_index(dev, 0, &reset_ctl); 738 if (ret) { 739 debug("%s(): Failed to get reset signal\n", __func__); 740 return ret; 741 } 742 743 ret = reset_assert(&reset_ctl); 744 if (ret) { 745 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 746 return ret; 747 } 748 #endif 749 750 ast2600_sdrammc_unlock(priv); 751 ast2600_sdrammc_common_init(regs); 752 753 if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) { 754 debug("Unsupported SDRAM type: DDR3\n"); 755 return -EINVAL; 756 } else { 757 ast2600_sdrammc_init_ddr4(priv); 758 } 759 760 #ifdef CONFIG_FPGA_ASPEED 761 ast2600_sdrammc_search_read_window(priv); 762 #endif 763 764 ast2600_sdramphy_show_status(priv); 765 ast2600_sdrammc_calc_size(priv); 766 #if 0 767 ast2600_sdrammc_test(priv); 768 #endif 769 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 770 priv->scu + AST_SCU_HANDSHAKE); 771 772 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 773 ast2600_sdrammc_lock(priv); 774 return 0; 775 } 776 777 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 778 { 779 struct dram_info *priv = dev_get_priv(dev); 780 int ret; 781 782 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 783 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 784 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 785 786 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 787 "clock-frequency", 0); 788 if (!priv->clock_rate) { 789 debug("DDR Clock Rate not defined\n"); 790 return -EINVAL; 791 } 792 793 return 0; 794 } 795 796 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 797 { 798 struct dram_info *priv = dev_get_priv(dev); 799 800 *info = priv->info; 801 802 return 0; 803 } 804 805 static struct ram_ops ast2600_sdrammc_ops = { 806 .get_info = ast2600_sdrammc_get_info, 807 }; 808 809 static const struct udevice_id ast2600_sdrammc_ids[] = { 810 { .compatible = "aspeed,ast2600-sdrammc" }, 811 { } 812 }; 813 814 U_BOOT_DRIVER(sdrammc_ast2600) = { 815 .name = "aspeed_ast2600_sdrammc", 816 .id = UCLASS_RAM, 817 .of_match = ast2600_sdrammc_ids, 818 .ops = &ast2600_sdrammc_ops, 819 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 820 .probe = ast2600_sdrammc_probe, 821 .priv_auto_alloc_size = sizeof(struct dram_info), 822 }; 823