1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include <linux/bitfield.h> 21 #include <linux/bitops.h> 22 #include "sdram_phy_ast2600.h" 23 24 /* in order to speed up DRAM init time, write pre-defined values to registers 25 * directly */ 26 #define AST2600_SDRAMMC_MANUAL_CLK 27 28 /* register offset */ 29 #define AST_SCU_FPGA_STATUS 0x004 30 #define AST_SCU_HANDSHAKE 0x100 31 #define AST_SCU_MPLL 0x220 32 #define AST_SCU_MPLL_EXT 0x224 33 #define AST_SCU_FPGA_PLL 0x400 34 #define AST_SCU_HW_STRAP 0x500 35 #define AST_SCU_EFUSE_DATA 0x594 36 37 38 /* bit-field of AST_SCU_HW_STRAP */ 39 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 40 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 41 42 /* bit-field of AST_SCU_EFUSE_DATA */ 43 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 44 45 /* bit-field of AST_SCU_HANDSHAKE */ 46 #define SCU_SDRAM_SUPPORT_IKVM_HIGH_RES BIT(0) 47 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 48 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 49 #define SCU_P2A_BRIDGE_DISABLE BIT(12) 50 #define SCU_HANDSHAKE_MASK \ 51 (SCU_SDRAM_INIT_READY_MASK | SCU_SDRAM_INIT_BY_SOC_MASK | \ 52 SCU_P2A_BRIDGE_DISABLE | SCU_SDRAM_SUPPORT_IKVM_HIGH_RES) 53 54 /* bit-field of AST_SCU_MPLL */ 55 #define SCU_MPLL_RESET BIT(25) 56 #define SCU_MPLL_BYPASS BIT(24) 57 #define SCU_MPLL_TURN_OFF BIT(23) 58 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 59 60 #define SCU_MPLL_FREQ_400M 0x0008405F 61 #define SCU_MPLL_EXT_400M 0x0000002F 62 //#define SCU_MPLL_FREQ_400M 0x0038007F 63 //#define SCU_MPLL_EXT_400M 0x0000003F 64 #define SCU_MPLL_FREQ_333M 0x00488299 65 #define SCU_MPLL_EXT_333M 0x0000014C 66 #define SCU_MPLL_FREQ_200M 0x0078007F 67 #define SCU_MPLL_EXT_200M 0x0000003F 68 #define SCU_MPLL_FREQ_100M 0x0078003F 69 #define SCU_MPLL_EXT_100M 0x0000001F 70 /* MPLL configuration */ 71 #if defined(CONFIG_ASPEED_DDR4_1600) 72 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 73 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 74 #elif defined(CONFIG_ASPEED_DDR4_1333) 75 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 76 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 77 #elif defined(CONFIG_ASPEED_DDR4_800) 78 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 79 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 80 #elif defined(CONFIG_ASPEED_DDR4_400) 81 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 82 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 83 #else 84 #error "undefined DDR4 target rate\n" 85 #endif 86 87 /** 88 * MR01[26:24] - ODT configuration (DRAM side) 89 * b'001 : 60 ohm 90 * b'101 : 48 ohm 91 * b'011 : 40 ohm (default) 92 */ 93 #if defined(CONFIG_ASPEED_DDR4_DRAM_ODT60) 94 #define MR01_DRAM_ODT (0x1 << 24) 95 #elif defined(CONFIG_ASPEED_DDR4_DRAM_ODT48) 96 #define MR01_DRAM_ODT (0x5 << 24) 97 #else 98 #define MR01_DRAM_ODT (0x3 << 24) 99 #endif 100 101 /* AC timing and SDRAM mode registers */ 102 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 103 /* mode register settings for FPGA are fixed */ 104 #define DDR4_MR01_MODE (MR01_DRAM_ODT | 0x00010100) 105 #define DDR4_MR23_MODE 0x00000000 106 #define DDR4_MR45_MODE 0x04C00000 107 #define DDR4_MR6_MODE 0x00000050 108 #define DDR4_TRFC_FPGA 0x17263434 109 #define DDR4_TRFI 0x5d 110 111 /* FPGA need for an additional initialization procedure: search read window */ 112 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 113 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 114 #define SEARCH_RDWIN_PTRN_0 0x12345678 115 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 116 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 117 #else 118 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 119 #define DDR4_MR01_MODE ((MR1_VAL << 16) | MR0_VAL) 120 #define DDR4_MR23_MODE ((MR3_VAL << 16) | MR2_VAL) 121 #define DDR4_MR45_MODE ((MR5_VAL << 16) | MR4_VAL) 122 #define DDR4_MR6_MODE MR6_VAL 123 124 #define DDR4_TRFC_1600 0x467299f1 125 #define DDR4_TRFC_1333 0x3a5f80c9 126 #define DDR4_TRFC_800 0x23394c78 127 #define DDR4_TRFC_400 0x111c263c 128 /* 129 * tRFI calculation 130 * DDR4 spec. : 131 * tRFI = 7.8 us if temperature is Less/equal than 85 degree celsius 132 * tRFI = 3.9 us if temperature is greater than 85 degree celsius 133 * 134 * tRFI in MCR0C = floor(tRFI * 12.5M) - margin 135 * normal temp. -> floor(7.8 * 12.5) - 2 = 0x5f 136 * high temp. -> floor(3.9 * 12.5) - 1 = 0x2f 137 */ 138 #ifdef CONFIG_ASPEED_HI_TEMP_TRFI 139 #define DDR4_TRFI 0x2f /* High temperature tRFI */ 140 #else 141 #define DDR4_TRFI 0x5f /* Normal temperature tRFI */ 142 #endif /* end of "#ifdef CONFIG_ASPEED_HI_TEMP_TRFI" */ 143 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 144 defined(CONFIG_ASPEED_PALLADIUM)" */ 145 146 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 147 #define DDR4_TRFC DDR4_TRFC_FPGA 148 #else 149 /* real chip setting */ 150 #if defined(CONFIG_ASPEED_DDR4_1600) 151 #define DDR4_TRFC DDR4_TRFC_1600 152 #define DDR4_PHY_TRAIN_TRFC 0xc30 153 #elif defined(CONFIG_ASPEED_DDR4_1333) 154 #define DDR4_TRFC DDR4_TRFC_1333 155 #define DDR4_PHY_TRAIN_TRFC 0xa25 156 #elif defined(CONFIG_ASPEED_DDR4_800) 157 #define DDR4_TRFC DDR4_TRFC_800 158 #define DDR4_PHY_TRAIN_TRFC 0x618 159 #elif defined(CONFIG_ASPEED_DDR4_400) 160 #define DDR4_TRFC DDR4_TRFC_400 161 #define DDR4_PHY_TRAIN_TRFC 0x30c 162 #else 163 #error "undefined tRFC setting" 164 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 165 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 166 defined(CONFIG_ASPEED_PALLADIUM)" */ 167 168 /* supported SDRAM size */ 169 #define SDRAM_SIZE_1KB (1024U) 170 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 171 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 172 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 173 174 175 DECLARE_GLOBAL_DATA_PTR; 176 177 /* 178 * Bandwidth configuration parameters for different SDRAM requests. 179 * These are hardcoded settings taken from Aspeed SDK. 180 */ 181 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 182 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 183 0x00000140 }; 184 185 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 186 0x88888888 }; 187 #else 188 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 189 0x00001240 }; 190 191 static const u32 ddr_max_grant_params[4] = { 0x44484488, 0xee4444ee, 0x44444444, 192 0x44444444 }; 193 #endif 194 195 struct dram_info { 196 struct ram_info info; 197 struct clk ddr_clk; 198 struct ast2600_sdrammc_regs *regs; 199 void __iomem *scu; 200 struct ast2600_ddr_phy *phy; 201 void __iomem *phy_setting; 202 void __iomem *phy_status; 203 ulong clock_rate; 204 }; 205 206 static void ast2600_sdramphy_kick_training(struct dram_info *info) 207 { 208 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 209 struct ast2600_sdrammc_regs *regs = info->regs; 210 u32 volatile data; 211 212 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 213 udelay(5); 214 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 215 udelay(1000); 216 217 while (1) { 218 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 219 if (~data) { 220 break; 221 } 222 } 223 224 #if 0 225 while (1) { 226 data = readl(0x1e6e0400) & BIT(1); 227 if (data) { 228 break; 229 } 230 } 231 #endif 232 #endif 233 } 234 235 /** 236 * @brief load DDR-PHY configurations table to the PHY registers 237 * @param[in] p_tbl - pointer to the configuration table 238 * @param[in] info - pointer to the DRAM info struct 239 * 240 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 241 * system: one is in the SDRAM MC (memory controller) which is used in run 242 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 243 * training. 244 */ 245 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 246 { 247 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 248 u32 reg_base = (u32)info->phy_setting; 249 u32 addr = p_tbl[0]; 250 u32 data; 251 int i = 1; 252 253 writel(0, &info->regs->phy_ctrl[0]); 254 udelay(10); 255 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 256 257 /* load PHY configuration table into PHY-setting registers */ 258 while (1) { 259 if (addr < reg_base) { 260 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 261 break; 262 } 263 data = p_tbl[i++]; 264 265 if (data == DDR_PHY_TBL_END) { 266 break; 267 } else if (data == DDR_PHY_TBL_CHG_ADDR) { 268 addr = p_tbl[i++]; 269 } else { 270 writel(data, addr); 271 addr += 4; 272 } 273 } 274 275 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 276 data |= DDR4_PHY_TRAIN_TRFC; 277 writel(data, info->phy_setting + 0x84); 278 #endif 279 } 280 281 static int ast2600_sdramphy_check_status(struct dram_info *info) 282 { 283 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 284 u32 value, tmp; 285 u32 reg_base = (u32)info->phy_status; 286 int need_retrain = 0; 287 288 debug("\nSDRAM PHY training report:\n"); 289 /* training status */ 290 value = readl(reg_base + 0x00); 291 debug("\nrO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 292 if (value & BIT(3)) 293 debug("\tinitial PVT calibration fail\n"); 294 295 if (value & BIT(5)) 296 debug("\truntime calibration fail\n"); 297 298 /* PU & PD */ 299 value = readl(reg_base + 0x30); 300 debug("\nrO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 301 debug(" PU = 0x%02lx\n", FIELD_GET(GENMASK(7, 0), value)); 302 debug(" PD = 0x%02lx\n", FIELD_GET(GENMASK(23, 16), value)); 303 304 /* read eye window */ 305 value = readl(reg_base + 0x68); 306 if (FIELD_GET(GENMASK(7, 0), value) == 0) 307 need_retrain = 1; 308 309 debug("\nrO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 310 debug(" rising edge of read data eye training pass window\n"); 311 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 312 debug(" B0:%d%%\n", tmp); 313 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 314 debug(" B1:%d%%\n", tmp); 315 316 value = readl(reg_base + 0xC8); 317 debug("\nrO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 318 debug(" falling edge of read data eye training pass window\n"); 319 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 320 debug(" B0:%d%%\n", tmp); 321 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 322 debug(" B1:%d%%\n", tmp); 323 324 /* write eye window */ 325 value = readl(reg_base + 0x7c); 326 if (FIELD_GET(GENMASK(7, 0), value) == 0) 327 need_retrain = 1; 328 329 debug("\nrO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 330 debug(" write data eye training pass window\n"); 331 tmp = FIELD_GET(GENMASK(7, 0), value) * 100 / 255; 332 debug(" B0:%d%%\n", tmp); 333 tmp = FIELD_GET(GENMASK(15, 8), value) * 100 / 255; 334 debug(" B1:%d%%\n", tmp); 335 336 /* read Vref (PHY side) training result */ 337 value = readl(reg_base + 0x88); 338 debug("\nrO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 339 debug(" Read VrefDQ training result\n"); 340 tmp = FIELD_GET(GENMASK(7, 0), value) * 10000 / 128; 341 debug(" B0:%d.%d%%\n", tmp / 100, tmp % 100); 342 tmp = FIELD_GET(GENMASK(15, 8), value) * 10000 / 128; 343 debug(" B1:%d.%d%%\n", tmp / 100, tmp % 100); 344 345 /* write Vref (DRAM side) training result */ 346 value = readl(reg_base + 0x90); 347 debug("\nrO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 348 tmp = readl(info->phy_setting + 0x60) & BIT(6); 349 if (tmp) { 350 value = 4500 + 65 * value; 351 debug(" Write Vref training result: %d.%d%% (range 2)\n", 352 value / 100, value % 100); 353 } else { 354 value = 6000 + 65 * value; 355 debug(" Write Vref training result: %d.%d%% (range 1)\n", 356 value / 100, value % 100); 357 } 358 359 /* gate train */ 360 value = readl(reg_base + 0x50); 361 debug("\nrO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 362 if ((FIELD_GET(GENMASK(15, 0), value) == 0) || 363 (FIELD_GET(GENMASK(31, 16), value) == 0)) 364 need_retrain = 1; 365 366 debug(" gate training pass window\n"); 367 debug(" module 0: 0x%04lx\n", FIELD_GET(GENMASK(15, 0), value)); 368 debug(" module 1: 0x%04lx\n", FIELD_GET(GENMASK(31, 16), value)); 369 370 return need_retrain; 371 #else 372 return 0; 373 #endif 374 } 375 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 376 #define MC_TEST_PATTERN_N 8 377 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 378 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 379 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 380 }; 381 382 #define TIMEOUT_DRAM 5000000 383 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 384 { 385 unsigned int data; 386 unsigned int timeout = 0; 387 struct ast2600_sdrammc_regs *regs = info->regs; 388 389 writel(0, ®s->ecc_test_ctrl); 390 if (mode == 0) 391 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 392 else 393 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 394 395 do { 396 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 397 398 if (data & BIT(13)) 399 return 0; 400 401 if (++timeout > TIMEOUT_DRAM) { 402 printf("Timeout!!\n"); 403 writel(0, ®s->ecc_test_ctrl); 404 405 return 0; 406 } 407 } while (!data); 408 409 writel(0, ®s->ecc_test_ctrl); 410 411 return 1; 412 } 413 414 int ast2600_sdrammc_cbr_test(struct dram_info *info) 415 { 416 struct ast2600_sdrammc_regs *regs = info->regs; 417 u32 i; 418 419 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 420 421 /* single */ 422 for (i = 0; i < 8; i++) { 423 if (!ast2600_sdrammc_dg_test(info, i, 0)) 424 return (0); 425 } 426 427 /* burst */ 428 for (i = 0; i < 8; i++) { 429 if (!ast2600_sdrammc_dg_test(info, i, i)) 430 return (0); 431 } 432 433 return(1); 434 } 435 436 static int ast2600_sdrammc_test(struct dram_info *info) 437 { 438 struct ast2600_sdrammc_regs *regs = info->regs; 439 440 u32 pass_cnt = 0; 441 u32 fail_cnt = 0; 442 u32 target_cnt = 2; 443 u32 test_cnt = 0; 444 u32 pattern; 445 u32 i = 0; 446 bool finish = false; 447 448 debug("sdram mc test:\n"); 449 while (finish == false) { 450 pattern = as2600_sdrammc_test_pattern[i++]; 451 i = i % MC_TEST_PATTERN_N; 452 debug(" pattern = %08x : ", pattern); 453 writel(pattern, ®s->test_init_val); 454 455 if (!ast2600_sdrammc_cbr_test(info)) { 456 debug("fail\n"); 457 fail_cnt++; 458 } else { 459 debug("pass\n"); 460 pass_cnt++; 461 } 462 463 if (++test_cnt == target_cnt) { 464 finish = true; 465 } 466 } 467 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 468 target_cnt); 469 return fail_cnt; 470 } 471 #endif 472 /** 473 * scu500[14:13] 474 * 2b'00: VGA memory size = 16MB 475 * 2b'01: VGA memory size = 16MB 476 * 2b'10: VGA memory size = 32MB 477 * 2b'11: VGA memory size = 64MB 478 * 479 * mcr04[3:2] 480 * 2b'00: VGA memory size = 8MB 481 * 2b'01: VGA memory size = 16MB 482 * 2b'10: VGA memory size = 32MB 483 * 2b'11: VGA memory size = 64MB 484 */ 485 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 486 { 487 u32 vga_hwconf; 488 size_t vga_mem_size_base = 8 * 1024 * 1024; 489 490 vga_hwconf = (readl(info->scu + AST_SCU_HW_STRAP) & 491 SCU_HWSTRAP_VGAMEM_MASK) >> 492 SCU_HWSTRAP_VGAMEM_SHIFT; 493 494 if (vga_hwconf == 0) { 495 vga_hwconf = 1; 496 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 497 info->scu + AST_SCU_HW_STRAP); 498 } 499 500 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 501 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 502 SDRAM_CONF_VGA_SIZE_MASK)); 503 504 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 505 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 506 return 0; 507 508 return vga_mem_size_base << vga_hwconf; 509 } 510 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 511 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 512 { 513 u32 data; 514 u32 scu_base = (u32)info->scu; 515 516 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 517 518 do { 519 data = readl(scu_base + AST_SCU_FPGA_STATUS); 520 } while (!(data & 0x100)); 521 522 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 523 } 524 525 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 526 { 527 u32 pll, pll_min, pll_max, dat1, offset; 528 u32 win = 0x03, gwin = 0, gwinsize = 0; 529 u32 phy_setting = (u32)info->phy_setting; 530 531 #ifdef CONFIG_ASPEED_PALLADIUM 532 writel(0xc, phy_setting + 0x0000); 533 return 1; 534 #endif 535 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 536 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 537 538 while (gwin == 0) { 539 while (!(win & 0x80)) { 540 debug("Window = 0x%X\n", win); 541 writel(win, phy_setting + 0x0000); 542 543 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 544 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 545 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 546 ast2600_sdrammc_fpga_set_pll(info); 547 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 548 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 549 } 550 551 pll_min = 0xfff; 552 pll_max = 0x0; 553 pll = 0; 554 while (pll_max > 0 || pll < 256) { 555 ast2600_sdrammc_fpga_set_pll(info); 556 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 557 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 558 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 559 if (pll_min > pll) 560 pll_min = pll; 561 562 if (pll_max < pll) 563 pll_max = pll; 564 565 debug("%3d_(%3d:%3d)\n", pll, pll_min, 566 pll_max); 567 } else if (pll_max > 0) { 568 pll_min = pll_max - pll_min; 569 if (gwinsize < pll_min) { 570 gwin = win; 571 gwinsize = pll_min; 572 } 573 break; 574 } 575 pll += 1; 576 } 577 578 if (gwin != 0 && pll_max == 0) 579 break; 580 581 win = win << 1; 582 } 583 if (gwin == 0) 584 win = 0x7; 585 } 586 debug("Set PLL Read Gating Window = %x\n", gwin); 587 writel(gwin, phy_setting + 0x0000); 588 589 debug("PLL Read Window training\n"); 590 pll_min = 0xfff; 591 pll_max = 0x0; 592 593 debug("Search Window Start\n"); 594 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 595 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 596 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 597 ast2600_sdrammc_fpga_set_pll(info); 598 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 599 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 600 } 601 602 debug("Search Window Margin\n"); 603 pll = 0; 604 while (pll_max > 0 || pll < 256) { 605 ast2600_sdrammc_fpga_set_pll(info); 606 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 607 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 608 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 609 if (pll_min > pll) 610 pll_min = pll; 611 612 if (pll_max < pll) 613 pll_max = pll; 614 615 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 616 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 617 break; 618 } else if (pll_max > 0) { 619 pll_min = 0xfff; 620 pll_max = 0x0; 621 } 622 pll += 1; 623 } 624 if (pll_min < pll_max) { 625 debug("PLL Read window = %d\n", (pll_max - pll_min)); 626 offset = (pll_max - pll_min) >> 1; 627 pll_min = 0xfff; 628 pll = 0; 629 while (pll < (pll_min + offset)) { 630 ast2600_sdrammc_fpga_set_pll(info); 631 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 632 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 633 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 634 if (pll_min > pll) { 635 pll_min = pll; 636 } 637 debug("%d\n", pll); 638 } else { 639 pll_min = 0xfff; 640 pll_max = 0x0; 641 } 642 pll += 1; 643 } 644 return (1); 645 } else { 646 debug("PLL Read window training fail\n"); 647 return 0; 648 } 649 } 650 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 651 defined(CONFIG_ASPEED_PALLADIUM)" */ 652 653 /* 654 * Find out RAM size and save it in dram_info 655 * 656 * The procedure is taken from Aspeed SDK 657 */ 658 static void ast2600_sdrammc_calc_size(struct dram_info *info) 659 { 660 /* The controller supports 256/512/1024/2048 MB ram */ 661 size_t ram_size = SDRAM_MIN_SIZE; 662 const int write_test_offset = 0x100000; 663 u32 test_pattern = 0xdeadbeef; 664 u32 cap_param = SDRAM_CONF_CAP_2048M; 665 u32 refresh_timing_param = DDR4_TRFC; 666 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 667 668 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 669 ram_size >>= 1) { 670 writel(test_pattern, write_addr_base + (ram_size >> 1)); 671 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 672 } 673 674 /* One last write to overwrite all wrapped values */ 675 writel(test_pattern, write_addr_base); 676 677 /* Reset the pattern and see which value was really written */ 678 test_pattern = 0xdeadbeef; 679 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 680 ram_size >>= 1) { 681 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 682 break; 683 684 --cap_param; 685 refresh_timing_param >>= 8; 686 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 687 } 688 689 clrsetbits_le32(&info->regs->ac_timing[1], 690 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 691 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 692 << SDRAM_AC_TRFC_SHIFT)); 693 694 info->info.base = CONFIG_SYS_SDRAM_BASE; 695 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 696 697 clrsetbits_le32( 698 &info->regs->config, SDRAM_CONF_CAP_MASK, 699 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 700 } 701 702 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 703 { 704 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 705 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 706 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 707 (0x1 << MCR34_ODT_EXT_SHIFT); 708 709 /* init SDRAM-PHY only on real chip */ 710 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 711 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 712 &info->regs->power_ctrl); 713 udelay(5); 714 ast2600_sdramphy_kick_training(info); 715 udelay(500); 716 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 717 718 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 719 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 720 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 721 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 722 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 723 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 724 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 725 &info->regs->mode_setting_control); 726 727 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 728 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT), 729 &info->regs->refresh_timing); 730 731 /* wait self-refresh idle */ 732 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 733 ; 734 735 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 736 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 737 SDRAM_REFRESH_ZQCS_EN | 738 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 739 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 740 &info->regs->refresh_timing); 741 #else 742 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 743 SDRAM_REFRESH_ZQCS_EN | 744 (DDR4_TRFI << SDRAM_REFRESH_PERIOD_SHIFT) | 745 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 746 &info->regs->refresh_timing); 747 #endif 748 749 writel(power_ctrl, &info->regs->power_ctrl); 750 udelay(500); 751 752 #if defined(CONFIG_FPGA_ASPEED) 753 /* toggle Vref training */ 754 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 755 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 756 &info->regs->mode_setting_control); 757 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 758 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 759 &info->regs->mode_setting_control); 760 #endif 761 return 0; 762 } 763 764 static void ast2600_sdrammc_unlock(struct dram_info *info) 765 { 766 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 767 while (!readl(&info->regs->protection_key)) 768 ; 769 } 770 771 static void ast2600_sdrammc_lock(struct dram_info *info) 772 { 773 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 774 while (readl(&info->regs->protection_key)) 775 ; 776 } 777 778 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 779 { 780 int i; 781 782 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 783 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 784 /* [6:0] : Group 1 request queued number = 16 785 * [14:8] : Group 2 request queued number = 16 786 * [20:16] : R/W max-grant count for RQ output arbitration = 16 787 */ 788 writel(0x101010, ®s->arbitration_ctrl); 789 /* Request Queued Limitation for REQ8/9 USB1/2 */ 790 writel(0x0FFF3CEF, ®s->req_limit_mask); 791 792 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 793 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 794 795 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 796 797 /* FIXME: the sample code does NOT match the datasheet */ 798 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 799 800 writel(0, ®s->ecc_test_ctrl); 801 writel(0x80000001, ®s->test_addr); 802 writel(0, ®s->test_fail_dq_bit); 803 writel(0, ®s->test_init_val); 804 805 writel(0xFFFFFFFF, ®s->req_input_ctrl); 806 writel(0x300, ®s->req_high_pri_ctrl); 807 808 udelay(600); 809 810 #ifdef CONFIG_ASPEED_DDR4_DUALX8 811 writel(0xa037, ®s->config); 812 #else 813 writel(0xa017, ®s->config); 814 #endif 815 816 /* load controller setting */ 817 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 818 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 819 820 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 821 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 822 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 823 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 824 } 825 /* 826 * Update size info according to the ECC HW setting 827 * 828 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 829 * don't need to calculate the ECC size again but read from MCR04 and derive the 830 * size from its value. 831 */ 832 static void ast2600_sdrammc_update_size(struct dram_info *info) 833 { 834 struct ast2600_sdrammc_regs *regs = info->regs; 835 size_t hw_size; 836 size_t ram_size = SDRAM_MAX_SIZE; 837 u32 cap_param; 838 839 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 840 switch (cap_param) 841 { 842 case SDRAM_CONF_CAP_2048M: 843 ram_size = 2048 * SDRAM_SIZE_1MB; 844 break; 845 case SDRAM_CONF_CAP_1024M: 846 ram_size = 1024 * SDRAM_SIZE_1MB; 847 break; 848 case SDRAM_CONF_CAP_512M: 849 ram_size = 512 * SDRAM_SIZE_1MB; 850 break; 851 case SDRAM_CONF_CAP_256M: 852 ram_size = 256 * SDRAM_SIZE_1MB; 853 break; 854 } 855 856 info->info.base = CONFIG_SYS_SDRAM_BASE; 857 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 858 859 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 860 return; 861 862 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 863 hw_size += (1 << 20); 864 865 info->info.size = hw_size; 866 } 867 #ifdef CONFIG_ASPEED_ECC 868 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 869 { 870 struct ast2600_sdrammc_regs *regs = info->regs; 871 size_t conf_size; 872 u32 reg; 873 874 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 875 if (conf_size > info->info.size) { 876 printf("warning: ECC configured %dMB but actual size is %dMB\n", 877 CONFIG_ASPEED_ECC_SIZE, 878 info->info.size / SDRAM_SIZE_1MB); 879 conf_size = info->info.size; 880 } else if (conf_size == 0) { 881 conf_size = info->info.size; 882 } 883 884 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 885 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 886 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 887 writel(reg, ®s->config); 888 889 writel(0, ®s->test_init_val); 890 writel(0x80000001, ®s->test_addr); 891 writel(0x221, ®s->ecc_test_ctrl); 892 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 893 ; 894 writel(0, ®s->ecc_test_ctrl); 895 writel(BIT(31), ®s->intr_ctrl); 896 writel(0, ®s->intr_ctrl); 897 } 898 #endif 899 900 static int ast2600_sdrammc_probe(struct udevice *dev) 901 { 902 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 903 struct ast2600_sdrammc_regs *regs = priv->regs; 904 struct udevice *clk_dev; 905 int ret; 906 volatile uint32_t reg; 907 908 /* find SCU base address from clock device */ 909 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 910 &clk_dev); 911 if (ret) { 912 debug("clock device not defined\n"); 913 return ret; 914 } 915 916 priv->scu = devfdt_get_addr_ptr(clk_dev); 917 if (IS_ERR(priv->scu)) { 918 debug("%s(): can't get SCU\n", __func__); 919 return PTR_ERR(priv->scu); 920 } 921 922 reg = readl(priv->scu + AST_SCU_HANDSHAKE); 923 if (reg & SCU_SDRAM_INIT_READY_MASK) { 924 printf("already initialized, "); 925 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 926 ast2600_sdrammc_update_size(priv); 927 return 0; 928 } 929 930 #ifdef AST2600_SDRAMMC_MANUAL_CLK 931 reg = readl(priv->scu + AST_SCU_MPLL); 932 reg &= ~(BIT(24) | GENMASK(22, 0)); 933 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 934 writel(reg, priv->scu + AST_SCU_MPLL); 935 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 936 udelay(100); 937 reg &= ~(BIT(25) | BIT(23)); 938 writel(reg, priv->scu + AST_SCU_MPLL); 939 while (0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))) 940 ; 941 #else 942 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 943 if (ret) { 944 debug("DDR:No CLK\n"); 945 return ret; 946 } 947 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 948 #endif 949 950 #if 0 951 /* FIXME: enable the following code if reset-driver is ready */ 952 struct reset_ctl reset_ctl; 953 ret = reset_get_by_index(dev, 0, &reset_ctl); 954 if (ret) { 955 debug("%s(): Failed to get reset signal\n", __func__); 956 return ret; 957 } 958 959 ret = reset_assert(&reset_ctl); 960 if (ret) { 961 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 962 return ret; 963 } 964 #endif 965 966 ast2600_sdrammc_unlock(priv); 967 ast2600_sdrammc_common_init(regs); 968 L_ast2600_sdramphy_train: 969 ast2600_sdrammc_init_ddr4(priv); 970 971 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 972 ast2600_sdrammc_search_read_window(priv); 973 #else 974 /* make sure DDR-PHY is ready before access */ 975 do { 976 reg = readl(priv->phy_status) & BIT(1); 977 } while (reg == 0); 978 #endif 979 980 ret = ast2600_sdramphy_check_status(priv); 981 if (ret) { 982 printf("DDR4 PHY training fail, retrain\n"); 983 goto L_ast2600_sdramphy_train; 984 } 985 986 ast2600_sdrammc_calc_size(priv); 987 988 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 989 ret = ast2600_sdrammc_test(priv); 990 if (ret) { 991 printf("%s: DDR4 init fail\n", __func__); 992 return -EINVAL; 993 } 994 #endif 995 996 #ifdef CONFIG_ASPEED_ECC 997 ast2600_sdrammc_ecc_enable(priv); 998 #endif 999 setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK); 1000 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 1001 ast2600_sdrammc_lock(priv); 1002 return 0; 1003 } 1004 1005 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 1006 { 1007 struct dram_info *priv = dev_get_priv(dev); 1008 1009 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 1010 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 1011 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 1012 1013 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 1014 "clock-frequency", 0); 1015 if (!priv->clock_rate) { 1016 debug("DDR Clock Rate not defined\n"); 1017 return -EINVAL; 1018 } 1019 1020 return 0; 1021 } 1022 1023 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 1024 { 1025 struct dram_info *priv = dev_get_priv(dev); 1026 1027 *info = priv->info; 1028 1029 return 0; 1030 } 1031 1032 static struct ram_ops ast2600_sdrammc_ops = { 1033 .get_info = ast2600_sdrammc_get_info, 1034 }; 1035 1036 static const struct udevice_id ast2600_sdrammc_ids[] = { 1037 { .compatible = "aspeed,ast2600-sdrammc" }, 1038 { } 1039 }; 1040 1041 U_BOOT_DRIVER(sdrammc_ast2600) = { 1042 .name = "aspeed_ast2600_sdrammc", 1043 .id = UCLASS_RAM, 1044 .of_match = ast2600_sdrammc_ids, 1045 .ops = &ast2600_sdrammc_ops, 1046 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1047 .probe = ast2600_sdrammc_probe, 1048 .priv_auto_alloc_size = sizeof(struct dram_info), 1049 }; 1050