1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2500.h> 17 #include <asm/arch/sdram_ast2500.h> 18 #include <asm/arch/wdt.h> 19 #include <linux/err.h> 20 #include <linux/kernel.h> 21 #include <dt-bindings/clock/ast2500-clock.h> 22 23 /* in order to speed up DRAM init time, write pre-defined values to registers 24 * directly */ 25 #define AST2500_SDRAMMC_MANUAL_CLK 26 27 /* bit-field of m_pll_param */ 28 #define SCU_MPLL_FREQ_MASK (SCU_MPLL_DENUM_MASK | SCU_MPLL_NUM_MASK | SCU_MPLL_POST_MASK) 29 #define SCU_MPLL_FREQ_400M 0x93002400 30 #define SCU_MPLL_FREQ_360M 0x930023A0 31 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_360M 32 33 #define SCU_MPLL_TURN_OFF BIT(19) 34 #define SCU_MPLL_BYPASS BIT(20) 35 #define SCU_MPLL_RESET BIT(21) 36 37 /* These configuration parameters are taken from Aspeed SDK */ 38 #define DDR4_MR46_MODE 0x08000000 39 #define DDR4_MR5_MODE 0x400 40 #define DDR4_MR13_MODE 0x101 41 #define DDR4_MR02_MODE 0x410 42 #define DDR4_TRFC 0x45457188 43 44 #define PHY_CFG_SIZE 15 45 46 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000}; 47 static const struct { 48 u32 index[PHY_CFG_SIZE]; 49 u32 value[PHY_CFG_SIZE]; 50 } ddr4_phy_config = { 51 .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50}, 52 .value = { 53 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24, 54 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607, 55 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e, 56 }, 57 }; 58 59 #define SDRAM_MAX_SIZE (1024 * 1024 * 1024) 60 #define SDRAM_MIN_SIZE (128 * 1024 * 1024) 61 62 DECLARE_GLOBAL_DATA_PTR; 63 64 /* 65 * Bandwidth configuration parameters for different SDRAM requests. 66 * These are hardcoded settings taken from Aspeed SDK. 67 */ 68 static const u32 ddr_max_grant_params[4] = { 69 0x88448844, 0x24422288, 0x22222222, 0x22222222 70 }; 71 72 /* 73 * These registers are not documented by Aspeed at all. 74 * All writes and reads are taken pretty much as is from SDK. 75 */ 76 struct ast2500_ddr_phy { 77 u32 phy[117]; 78 }; 79 80 struct dram_info { 81 struct ram_info info; 82 struct clk ddr_clk; 83 struct ast2500_sdrammc_regs *regs; 84 struct ast2500_scu *scu; 85 struct ast2500_ddr_phy *phy; 86 ulong clock_rate; 87 }; 88 89 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) 90 { 91 writel(0, &phy->phy[2]); 92 writel(0, &phy->phy[6]); 93 writel(0, &phy->phy[8]); 94 writel(0, &phy->phy[10]); 95 writel(0, &phy->phy[12]); 96 writel(0, &phy->phy[42]); 97 writel(0, &phy->phy[44]); 98 99 writel(0x86000000, &phy->phy[16]); 100 writel(0x00008600, &phy->phy[17]); 101 writel(0x80000000, &phy->phy[18]); 102 writel(0x80808080, &phy->phy[19]); 103 104 return 0; 105 } 106 107 static void ast2500_ddr_phy_init_process(struct dram_info *info) 108 { 109 struct ast2500_sdrammc_regs *regs = info->regs; 110 111 writel(0, ®s->phy_ctrl[0]); 112 writel(0x4040, &info->phy->phy[51]); 113 114 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 115 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) 116 ; 117 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE, 118 ®s->phy_ctrl[0]); 119 } 120 121 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) 122 { 123 writel(0, &info->regs->phy_ctrl[0]); 124 writel((vref << 8) | 0x6, &info->phy->phy[48]); 125 ast2500_ddr_phy_init_process(info); 126 } 127 128 static int ast2500_ddr_cbr_test(struct dram_info *info) 129 { 130 struct ast2500_sdrammc_regs *regs = info->regs; 131 int i; 132 const u32 test_params = SDRAM_TEST_EN 133 | SDRAM_TEST_ERRSTOP 134 | SDRAM_TEST_TWO_MODES; 135 int ret = 0; 136 137 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) | 138 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); 139 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); 140 writel(0xff00ff00, ®s->test_init_val); 141 writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) | 142 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); 143 144 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 145 ; 146 147 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 148 ret = -EIO; 149 } else { 150 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) { 151 writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params, 152 ®s->ecc_test_ctrl); 153 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 154 ; 155 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 156 ret = -EIO; 157 break; 158 } 159 } 160 } 161 162 writel(0, ®s->refresh_timing); 163 writel(0, ®s->ecc_test_ctrl); 164 165 return ret; 166 } 167 168 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) 169 { 170 int i; 171 int vref_min = 0xff; 172 int vref_max = 0; 173 int range_size = 0; 174 175 for (i = 1; i < 0x40; ++i) { 176 int res; 177 178 ast2500_sdrammc_set_vref(info, i); 179 res = ast2500_ddr_cbr_test(info); 180 if (res < 0) { 181 if (range_size > 0) 182 break; 183 } else { 184 ++range_size; 185 vref_min = min(vref_min, i); 186 vref_max = max(vref_max, i); 187 } 188 } 189 190 /* Pick average setting */ 191 ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2); 192 193 return 0; 194 } 195 196 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) 197 { 198 size_t vga_mem_size_base = 8 * 1024 * 1024; 199 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) 200 >> SCU_HWSTRAP_VGAMEM_SHIFT; 201 202 return vga_mem_size_base << vga_hwconf; 203 } 204 205 /* 206 * Find out RAM size and save it in dram_info 207 * 208 * The procedure is taken from Aspeed SDK 209 */ 210 static void ast2500_sdrammc_calc_size(struct dram_info *info) 211 { 212 /* The controller supports 128/256/512/1024 MB ram */ 213 size_t ram_size = SDRAM_MIN_SIZE; 214 const int write_test_offset = 0x100000; 215 u32 test_pattern = 0xdeadbeef; 216 u32 cap_param = SDRAM_CONF_CAP_1024M; 217 u32 refresh_timing_param = DDR4_TRFC; 218 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 219 220 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 221 ram_size >>= 1) { 222 writel(test_pattern, write_addr_base + (ram_size >> 1)); 223 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 224 } 225 226 /* One last write to overwrite all wrapped values */ 227 writel(test_pattern, write_addr_base); 228 229 /* Reset the pattern and see which value was really written */ 230 test_pattern = 0xdeadbeef; 231 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 232 ram_size >>= 1) { 233 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 234 break; 235 236 --cap_param; 237 refresh_timing_param >>= 8; 238 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 239 } 240 241 clrsetbits_le32(&info->regs->ac_timing[1], 242 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 243 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 244 << SDRAM_AC_TRFC_SHIFT)); 245 246 info->info.base = CONFIG_SYS_SDRAM_BASE; 247 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); 248 clrsetbits_le32(&info->regs->config, 249 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), 250 ((cap_param & SDRAM_CONF_CAP_MASK) 251 << SDRAM_CONF_CAP_SHIFT)); 252 } 253 254 static int ast2500_sdrammc_init_ddr4(struct dram_info *info) 255 { 256 int i; 257 const u32 power_control = SDRAM_PCR_CKE_EN 258 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT) 259 | (2 << SDRAM_PCR_TCKE_PW_SHIFT) 260 | SDRAM_PCR_RESETN_DIS 261 | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN; 262 const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT) 263 #ifdef CONFIG_DUALX8_RAM 264 | SDRAM_CONF_DUALX8 265 #endif 266 | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4; 267 int ret; 268 269 writel(conf, &info->regs->config); 270 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 271 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); 272 273 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); 274 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); 275 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); 276 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); 277 278 for (i = 0; i < PHY_CFG_SIZE; ++i) { 279 writel(ddr4_phy_config.value[i], 280 &info->phy->phy[ddr4_phy_config.index[i]]); 281 } 282 283 writel(power_control, &info->regs->power_control); 284 285 ast2500_ddr_phy_init_process(info); 286 287 ret = ast2500_sdrammc_ddr4_calibrate_vref(info); 288 if (ret < 0) { 289 debug("Vref calibration failed!\n"); 290 return ret; 291 } 292 293 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) 294 | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT), 295 &info->regs->refresh_timing); 296 297 setbits_le32(&info->regs->power_control, 298 SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON); 299 300 ast2500_sdrammc_calc_size(info); 301 302 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); 303 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) 304 ; 305 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); 306 307 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); 308 309 /* Enable all requests except video & display */ 310 writel(SDRAM_REQ_USB20_EHCI1 311 | SDRAM_REQ_USB20_EHCI2 312 | SDRAM_REQ_CPU 313 | SDRAM_REQ_AHB2 314 | SDRAM_REQ_AHB 315 | SDRAM_REQ_MAC0 316 | SDRAM_REQ_MAC1 317 | SDRAM_REQ_PCIE 318 | SDRAM_REQ_XDMA 319 | SDRAM_REQ_ENCRYPTION 320 | SDRAM_REQ_VIDEO_FLAG 321 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE 322 | SDRAM_REQ_2D_RW 323 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); 324 325 return 0; 326 } 327 328 static void ast2500_sdrammc_unlock(struct dram_info *info) 329 { 330 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 331 while (!readl(&info->regs->protection_key)) 332 ; 333 } 334 335 static void ast2500_sdrammc_lock(struct dram_info *info) 336 { 337 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 338 while (readl(&info->regs->protection_key)) 339 ; 340 } 341 342 static int ast2500_sdrammc_probe(struct udevice *dev) 343 { 344 struct reset_ctl reset_ctl; 345 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 346 struct ast2500_sdrammc_regs *regs = priv->regs; 347 struct udevice *clk_dev; 348 int i; 349 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 350 uint32_t reg; 351 352 if (ret) { 353 debug("DDR:No CLK\n"); 354 return ret; 355 } 356 357 /* find the SCU base address from the aspeed clock device */ 358 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 359 &clk_dev); 360 if (ret) { 361 debug("clock device not defined\n"); 362 return ret; 363 } 364 priv->scu = devfdt_get_addr_ptr(clk_dev); 365 366 if (IS_ERR(priv->scu)) { 367 debug("%s(): can't get SCU\n", __func__); 368 return PTR_ERR(priv->scu); 369 } 370 371 if (readl(&priv->scu->vga_handshake[0]) & (0x1 << 6)) { 372 printf("%s(): DDR SDRAM had been initialized\n", __func__); 373 ast2500_sdrammc_calc_size(priv); 374 return 0; 375 } 376 377 #ifdef AST2500_SDRAMMC_MANUAL_CLK 378 reg = readl(&priv->scu->m_pll_param); 379 reg |= (SCU_MPLL_RESET | SCU_MPLL_TURN_OFF); 380 writel(reg, &priv->scu->m_pll_param); 381 reg &= ~(SCU_MPLL_RESET | SCU_MPLL_TURN_OFF| SCU_MPLL_FREQ_MASK); 382 reg |= SCU_MPLL_FREQ_CFG; 383 writel(reg, &priv->scu->m_pll_param); 384 #else 385 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 386 #endif 387 388 #if 0 389 ret = reset_get_by_index(dev, 0, &reset_ctl); 390 if (ret) { 391 debug("%s(): Failed to get reset signal\n", __func__); 392 return ret; 393 } 394 395 ret = reset_assert(&reset_ctl); 396 if (ret) { 397 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 398 return ret; 399 } 400 #endif 401 ast2500_sdrammc_unlock(priv); 402 403 writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS, 404 ®s->power_control); 405 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 406 407 /* Mask all requests except CPU and AHB during PHY init */ 408 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); 409 410 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 411 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 412 413 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 414 415 ast2500_sdrammc_init_phy(priv->phy); 416 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { 417 ast2500_sdrammc_init_ddr4(priv); 418 } else { 419 debug("Unsupported DRAM3\n"); 420 return -EINVAL; 421 } 422 423 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 424 ast2500_sdrammc_lock(priv); 425 426 return 0; 427 } 428 429 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev) 430 { 431 struct dram_info *priv = dev_get_priv(dev); 432 int ret; 433 434 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 435 priv->phy = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 436 437 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 438 "clock-frequency", 0); 439 if (!priv->clock_rate) { 440 debug("DDR Clock Rate not defined\n"); 441 return -EINVAL; 442 } 443 444 return 0; 445 } 446 447 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 448 { 449 struct dram_info *priv = dev_get_priv(dev); 450 451 *info = priv->info; 452 453 return 0; 454 } 455 456 static struct ram_ops ast2500_sdrammc_ops = { 457 .get_info = ast2500_sdrammc_get_info, 458 }; 459 460 static const struct udevice_id ast2500_sdrammc_ids[] = { 461 { .compatible = "aspeed,ast2500-sdrammc" }, 462 { } 463 }; 464 465 U_BOOT_DRIVER(sdrammc_ast2500) = { 466 .name = "aspeed_ast2500_sdrammc", 467 .id = UCLASS_RAM, 468 .of_match = ast2500_sdrammc_ids, 469 .ops = &ast2500_sdrammc_ops, 470 .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata, 471 .probe = ast2500_sdrammc_probe, 472 .priv_auto_alloc_size = sizeof(struct dram_info), 473 }; 474