1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2500.h> 17 #include <asm/arch/sdram_ast2500.h> 18 #include <linux/err.h> 19 #include <linux/kernel.h> 20 #include <dt-bindings/clock/ast2500-clock.h> 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2500_SDRAMMC_MANUAL_CLK 25 26 /* bit-field of m_pll_param */ 27 #define SCU_MPLL_FREQ_MASK (SCU_MPLL_DENUM_MASK | SCU_MPLL_NUM_MASK | SCU_MPLL_POST_MASK) 28 #define SCU_MPLL_FREQ_400M 0x93002400 29 #define SCU_MPLL_FREQ_360M 0x930023A0 30 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_360M 31 32 #define SCU_MPLL_TURN_OFF BIT(19) 33 #define SCU_MPLL_BYPASS BIT(20) 34 #define SCU_MPLL_RESET BIT(21) 35 36 /* These configuration parameters are taken from Aspeed SDK */ 37 #define DDR4_MR46_MODE 0x08000000 38 #define DDR4_MR5_MODE 0x400 39 #define DDR4_MR13_MODE 0x101 40 #define DDR4_MR02_MODE 0x410 41 #define DDR4_TRFC 0x45457188 42 43 #define PHY_CFG_SIZE 15 44 45 static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000}; 46 static const struct { 47 u32 index[PHY_CFG_SIZE]; 48 u32 value[PHY_CFG_SIZE]; 49 } ddr4_phy_config = { 50 .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50}, 51 .value = { 52 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24, 53 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607, 54 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e, 55 }, 56 }; 57 58 #define SDRAM_MAX_SIZE (1024 * 1024 * 1024) 59 #define SDRAM_MIN_SIZE (128 * 1024 * 1024) 60 61 DECLARE_GLOBAL_DATA_PTR; 62 63 /* 64 * Bandwidth configuration parameters for different SDRAM requests. 65 * These are hardcoded settings taken from Aspeed SDK. 66 */ 67 static const u32 ddr_max_grant_params[4] = { 68 0x88448844, 0x24422288, 0x22222222, 0x22222222 69 }; 70 71 /* 72 * These registers are not documented by Aspeed at all. 73 * All writes and reads are taken pretty much as is from SDK. 74 */ 75 struct ast2500_ddr_phy { 76 u32 phy[117]; 77 }; 78 79 struct dram_info { 80 struct ram_info info; 81 struct clk ddr_clk; 82 struct ast2500_sdrammc_regs *regs; 83 struct ast2500_scu *scu; 84 struct ast2500_ddr_phy *phy; 85 ulong clock_rate; 86 }; 87 88 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) 89 { 90 writel(0, &phy->phy[2]); 91 writel(0, &phy->phy[6]); 92 writel(0, &phy->phy[8]); 93 writel(0, &phy->phy[10]); 94 writel(0, &phy->phy[12]); 95 writel(0, &phy->phy[42]); 96 writel(0, &phy->phy[44]); 97 98 writel(0x86000000, &phy->phy[16]); 99 writel(0x00008600, &phy->phy[17]); 100 writel(0x80000000, &phy->phy[18]); 101 writel(0x80808080, &phy->phy[19]); 102 103 return 0; 104 } 105 106 static void ast2500_ddr_phy_init_process(struct dram_info *info) 107 { 108 struct ast2500_sdrammc_regs *regs = info->regs; 109 110 writel(0, ®s->phy_ctrl[0]); 111 writel(0x4040, &info->phy->phy[51]); 112 113 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 114 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) 115 ; 116 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE, 117 ®s->phy_ctrl[0]); 118 } 119 120 static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) 121 { 122 writel(0, &info->regs->phy_ctrl[0]); 123 writel((vref << 8) | 0x6, &info->phy->phy[48]); 124 ast2500_ddr_phy_init_process(info); 125 } 126 127 static int ast2500_ddr_cbr_test(struct dram_info *info) 128 { 129 struct ast2500_sdrammc_regs *regs = info->regs; 130 int i; 131 const u32 test_params = SDRAM_TEST_EN 132 | SDRAM_TEST_ERRSTOP 133 | SDRAM_TEST_TWO_MODES; 134 int ret = 0; 135 136 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) | 137 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); 138 writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); 139 writel(0xff00ff00, ®s->test_init_val); 140 writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) | 141 SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); 142 143 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 144 ; 145 146 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 147 ret = -EIO; 148 } else { 149 for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) { 150 writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params, 151 ®s->ecc_test_ctrl); 152 while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) 153 ; 154 if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { 155 ret = -EIO; 156 break; 157 } 158 } 159 } 160 161 writel(0, ®s->refresh_timing); 162 writel(0, ®s->ecc_test_ctrl); 163 164 return ret; 165 } 166 167 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) 168 { 169 int i; 170 int vref_min = 0xff; 171 int vref_max = 0; 172 int range_size = 0; 173 174 for (i = 1; i < 0x40; ++i) { 175 int res; 176 177 ast2500_sdrammc_set_vref(info, i); 178 res = ast2500_ddr_cbr_test(info); 179 if (res < 0) { 180 if (range_size > 0) 181 break; 182 } else { 183 ++range_size; 184 vref_min = min(vref_min, i); 185 vref_max = max(vref_max, i); 186 } 187 } 188 189 /* Pick average setting */ 190 ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2); 191 192 return 0; 193 } 194 195 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) 196 { 197 size_t vga_mem_size_base = 8 * 1024 * 1024; 198 u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) 199 >> SCU_HWSTRAP_VGAMEM_SHIFT; 200 201 return vga_mem_size_base << vga_hwconf; 202 } 203 204 /* 205 * Find out RAM size and save it in dram_info 206 * 207 * The procedure is taken from Aspeed SDK 208 */ 209 static void ast2500_sdrammc_calc_size(struct dram_info *info) 210 { 211 /* The controller supports 128/256/512/1024 MB ram */ 212 size_t ram_size = SDRAM_MIN_SIZE; 213 const int write_test_offset = 0x100000; 214 u32 test_pattern = 0xdeadbeef; 215 u32 cap_param = SDRAM_CONF_CAP_1024M; 216 u32 refresh_timing_param = DDR4_TRFC; 217 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 218 219 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 220 ram_size >>= 1) { 221 writel(test_pattern, write_addr_base + (ram_size >> 1)); 222 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 223 } 224 225 /* One last write to overwrite all wrapped values */ 226 writel(test_pattern, write_addr_base); 227 228 /* Reset the pattern and see which value was really written */ 229 test_pattern = 0xdeadbeef; 230 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 231 ram_size >>= 1) { 232 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 233 break; 234 235 --cap_param; 236 refresh_timing_param >>= 8; 237 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 238 } 239 240 clrsetbits_le32(&info->regs->ac_timing[1], 241 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 242 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 243 << SDRAM_AC_TRFC_SHIFT)); 244 245 info->info.base = CONFIG_SYS_SDRAM_BASE; 246 info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); 247 clrsetbits_le32(&info->regs->config, 248 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), 249 ((cap_param & SDRAM_CONF_CAP_MASK) 250 << SDRAM_CONF_CAP_SHIFT)); 251 } 252 253 static int ast2500_sdrammc_init_ddr4(struct dram_info *info) 254 { 255 int i; 256 const u32 power_control = SDRAM_PCR_CKE_EN 257 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT) 258 | (2 << SDRAM_PCR_TCKE_PW_SHIFT) 259 | SDRAM_PCR_RESETN_DIS 260 | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN; 261 const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT) 262 #ifdef CONFIG_DUALX8_RAM 263 | SDRAM_CONF_DUALX8 264 #endif 265 | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4; 266 int ret; 267 268 writel(conf, &info->regs->config); 269 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 270 writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); 271 272 writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); 273 writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); 274 writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); 275 writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); 276 277 for (i = 0; i < PHY_CFG_SIZE; ++i) { 278 writel(ddr4_phy_config.value[i], 279 &info->phy->phy[ddr4_phy_config.index[i]]); 280 } 281 282 writel(power_control, &info->regs->power_control); 283 284 ast2500_ddr_phy_init_process(info); 285 286 ret = ast2500_sdrammc_ddr4_calibrate_vref(info); 287 if (ret < 0) { 288 debug("Vref calibration failed!\n"); 289 return ret; 290 } 291 292 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) 293 | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT), 294 &info->regs->refresh_timing); 295 296 setbits_le32(&info->regs->power_control, 297 SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON); 298 299 ast2500_sdrammc_calc_size(info); 300 301 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); 302 while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) 303 ; 304 setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); 305 306 writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); 307 308 /* Enable all requests except video & display */ 309 writel(SDRAM_REQ_USB20_EHCI1 310 | SDRAM_REQ_USB20_EHCI2 311 | SDRAM_REQ_CPU 312 | SDRAM_REQ_AHB2 313 | SDRAM_REQ_AHB 314 | SDRAM_REQ_MAC0 315 | SDRAM_REQ_MAC1 316 | SDRAM_REQ_PCIE 317 | SDRAM_REQ_XDMA 318 | SDRAM_REQ_ENCRYPTION 319 | SDRAM_REQ_VIDEO_FLAG 320 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE 321 | SDRAM_REQ_2D_RW 322 | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); 323 324 return 0; 325 } 326 327 static void ast2500_sdrammc_unlock(struct dram_info *info) 328 { 329 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 330 while (!readl(&info->regs->protection_key)) 331 ; 332 } 333 334 static void ast2500_sdrammc_lock(struct dram_info *info) 335 { 336 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 337 while (readl(&info->regs->protection_key)) 338 ; 339 } 340 341 static int ast2500_sdrammc_probe(struct udevice *dev) 342 { 343 struct reset_ctl reset_ctl; 344 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 345 struct ast2500_sdrammc_regs *regs = priv->regs; 346 struct udevice *clk_dev; 347 int i; 348 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 349 uint32_t reg; 350 351 if (ret) { 352 debug("DDR:No CLK\n"); 353 return ret; 354 } 355 356 /* find the SCU base address from the aspeed clock device */ 357 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 358 &clk_dev); 359 if (ret) { 360 debug("clock device not defined\n"); 361 return ret; 362 } 363 priv->scu = devfdt_get_addr_ptr(clk_dev); 364 365 if (IS_ERR(priv->scu)) { 366 debug("%s(): can't get SCU\n", __func__); 367 return PTR_ERR(priv->scu); 368 } 369 370 if (readl(&priv->scu->vga_handshake[0]) & (0x1 << 6)) { 371 printf("%s(): DDR SDRAM had been initialized\n", __func__); 372 ast2500_sdrammc_calc_size(priv); 373 return 0; 374 } 375 376 #ifdef AST2500_SDRAMMC_MANUAL_CLK 377 reg = readl(&priv->scu->m_pll_param); 378 reg |= (SCU_MPLL_RESET | SCU_MPLL_TURN_OFF); 379 writel(reg, &priv->scu->m_pll_param); 380 reg &= ~(SCU_MPLL_RESET | SCU_MPLL_TURN_OFF| SCU_MPLL_FREQ_MASK); 381 reg |= SCU_MPLL_FREQ_CFG; 382 writel(reg, &priv->scu->m_pll_param); 383 #else 384 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 385 #endif 386 387 #if 0 388 ret = reset_get_by_index(dev, 0, &reset_ctl); 389 if (ret) { 390 debug("%s(): Failed to get reset signal\n", __func__); 391 return ret; 392 } 393 394 ret = reset_assert(&reset_ctl); 395 if (ret) { 396 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 397 return ret; 398 } 399 #endif 400 ast2500_sdrammc_unlock(priv); 401 402 writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS, 403 ®s->power_control); 404 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 405 406 /* Mask all requests except CPU and AHB during PHY init */ 407 writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); 408 409 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 410 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 411 412 setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 413 414 ast2500_sdrammc_init_phy(priv->phy); 415 if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { 416 ast2500_sdrammc_init_ddr4(priv); 417 } else { 418 debug("Unsupported DRAM3\n"); 419 return -EINVAL; 420 } 421 422 clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); 423 ast2500_sdrammc_lock(priv); 424 425 return 0; 426 } 427 428 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev) 429 { 430 struct dram_info *priv = dev_get_priv(dev); 431 int ret; 432 433 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 434 priv->phy = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 435 436 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 437 "clock-frequency", 0); 438 if (!priv->clock_rate) { 439 debug("DDR Clock Rate not defined\n"); 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 447 { 448 struct dram_info *priv = dev_get_priv(dev); 449 450 *info = priv->info; 451 452 return 0; 453 } 454 455 static struct ram_ops ast2500_sdrammc_ops = { 456 .get_info = ast2500_sdrammc_get_info, 457 }; 458 459 static const struct udevice_id ast2500_sdrammc_ids[] = { 460 { .compatible = "aspeed,ast2500-sdrammc" }, 461 { } 462 }; 463 464 U_BOOT_DRIVER(sdrammc_ast2500) = { 465 .name = "aspeed_ast2500_sdrammc", 466 .id = UCLASS_RAM, 467 .of_match = ast2500_sdrammc_ids, 468 .ops = &ast2500_sdrammc_ops, 469 .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata, 470 .probe = ast2500_sdrammc_probe, 471 .priv_auto_alloc_size = sizeof(struct dram_info), 472 }; 473