1if RAM || SPL_RAM 2 3if ASPEED_AST2600 4choice 5 prompt "DDR4 target data rate" 6 default ASPEED_DDR4_1600 7 8config ASPEED_DDR4_400 9 bool "DDR4 targets at 400Mbps" 10 depends on DM && OF_CONTROL && ARCH_ASPEED 11 help 12 select DDR4 target data rate at 400M 13 14config ASPEED_DDR4_800 15 bool "DDR4 targets at 800Mbps" 16 depends on DM && OF_CONTROL && ARCH_ASPEED 17 help 18 select DDR4 target data rate at 800M 19 20config ASPEED_DDR4_1333 21 bool "DDR4 targets at 1333Mbps" 22 depends on DM && OF_CONTROL && ARCH_ASPEED 23 help 24 select DDR4 target data rate at 1333M 25 26config ASPEED_DDR4_1600 27 bool "DDR4 targets at 1600Mbps" 28 depends on DM && OF_CONTROL && ARCH_ASPEED 29 help 30 select DDR4 target data rate at 1600M 31endchoice 32 33config ASPEED_DDR4_DUALX8 34 bool "dual X8 DDR4 die" 35 depends on DM && OF_CONTROL && ARCH_ASPEED 36 default n 37 help 38 select dual X8 DDR4 die 39 40config ASPEED_BYPASS_SELFTEST 41 bool "bypass self test during DRAM initialization" 42 default n 43 help 44 Say Y here to bypass DRAM self test to speed up the boot time 45endif 46 47config ASPEED_ECC 48 bool "aspeed SDRAM error correcting code" 49 depends on DM && OF_CONTROL && ARCH_ASPEED 50 default n 51 help 52 enable SDRAM ECC function 53 54choice 55 prompt "DDR4 PHY side ODT" 56 default ASPEED_DDR4_PHY_ODT80 57 58config ASPEED_DDR4_PHY_ODT80 59 bool "DDR4 PHY side ODT 80 ohm" 60 depends on DM && OF_CONTROL && ARCH_ASPEED 61 help 62 select DDR4 PHY side ODT 80 ohm 63 64config ASPEED_DDR4_PHY_ODT60 65 bool "DDR4 PHY side ODT 60 ohm" 66 depends on DM && OF_CONTROL && ARCH_ASPEED 67 help 68 select DDR4 PHY side ODT 60 ohm 69 70config ASPEED_DDR4_PHY_ODT48 71 bool "DDR4 PHY side ODT 48 ohm" 72 depends on DM && OF_CONTROL && ARCH_ASPEED 73 help 74 select DDR4 PHY side ODT 48 ohm 75 76config ASPEED_DDR4_PHY_ODT40 77 bool "DDR4 PHY side ODT 40 ohm" 78 depends on DM && OF_CONTROL && ARCH_ASPEED 79 help 80 select DDR4 PHY side ODT 40 ohm 81endchoice 82 83choice 84 prompt "DDR4 DRAM side ODT" 85 default ASPEED_DDR4_DRAM_ODT48 86 87config ASPEED_DDR4_DRAM_ODT80 88 bool "DDR4 DRAM side ODT 80 ohm" 89 depends on DM && OF_CONTROL && ARCH_ASPEED 90 help 91 select DDR4 DRAM side ODT 80 ohm 92 93config ASPEED_DDR4_DRAM_ODT60 94 bool "DDR4 DRAM side ODT 60 ohm" 95 depends on DM && OF_CONTROL && ARCH_ASPEED 96 help 97 select DDR4 DRAM side ODT 60 ohm 98 99config ASPEED_DDR4_DRAM_ODT48 100 bool "DDR4 DRAM side ODT 48 ohm" 101 depends on DM && OF_CONTROL && ARCH_ASPEED 102 help 103 select DDR4 DRAM side ODT 48 ohm 104 105config ASPEED_DDR4_DRAM_ODT40 106 bool "DDR4 DRAM side ODT 40 ohm" 107 depends on DM && OF_CONTROL && ARCH_ASPEED 108 help 109 select DDR4 DRAM side ODT 40 ohm 110endchoice 111 112choice 113 prompt "DDR4 DRAM output driver impedance" 114 default ASPEED_DDR4_DRAM_RON_34 115 116config ASPEED_DDR4_DRAM_RON_34 117 bool "DDR4 DRAM output driver impedance 34 ohm" 118 depends on DM && OF_CONTROL && ARCH_ASPEED 119 help 120 select DDR4 DRAM output driver impedance 34 ohm 121 122config ASPEED_DDR4_DRAM_RON_48 123 bool "DDR4 DRAM output driver impedance 48 ohm" 124 depends on DM && OF_CONTROL && ARCH_ASPEED 125 help 126 select DDR4 DRAM output driver impedance 48 ohm 127endchoice 128 129config ASPEED_DDR4_WR_DATA_EYE_TRAINING_RESULT_OFFSET 130 hex "DDR PHY write data eye training result offset" 131 default 0x10 132 help 133 The offset value applied to the DDR PHY write data eye training result 134 to fine-tune the write DQ/DQS alignment. Please don't change it if you 135 are not sure what is the best value in your system. 136endif 137