1if RAM || SPL_RAM 2 3if ASPEED_AST2600 4choice 5 prompt "DDR4 target data rate" 6 default ASPEED_DDR4_1600 7 8config ASPEED_DDR4_400 9 bool "DDR4 targets at 400Mbps" 10 depends on DM && OF_CONTROL && ARCH_ASPEED 11 help 12 select DDR4 target data rate at 400M 13 14config ASPEED_DDR4_800 15 bool "DDR4 targets at 800Mbps" 16 depends on DM && OF_CONTROL && ARCH_ASPEED 17 help 18 select DDR4 target data rate at 800M 19 20config ASPEED_DDR4_1333 21 bool "DDR4 targets at 1333Mbps" 22 depends on DM && OF_CONTROL && ARCH_ASPEED 23 help 24 select DDR4 target data rate at 1333M 25 26config ASPEED_DDR4_1600 27 bool "DDR4 targets at 1600Mbps" 28 depends on DM && OF_CONTROL && ARCH_ASPEED 29 help 30 select DDR4 target data rate at 1600M 31endchoice 32 33config ASPEED_DDR4_DUALX8 34 bool "dual X8 DDR4 die" 35 depends on DM && OF_CONTROL && ARCH_ASPEED 36 default n 37 help 38 select dual X8 DDR4 die 39 40config ASPEED_BYPASS_SELFTEST 41 bool "bypass self test during DRAM initialization" 42 default n 43 help 44 Say Y here to bypass DRAM self test to speed up the boot time 45endif 46 47choice 48 prompt "DDR4 PHY side ODT" 49 default ASPEED_DDR4_PHY_ODT80 50 51config ASPEED_DDR4_PHY_ODT80 52 bool "DDR4 PHY side ODT 80 ohm" 53 depends on DM && OF_CONTROL && ARCH_ASPEED 54 help 55 select DDR4 PHY side ODT 80 ohm 56 57config ASPEED_DDR4_PHY_ODT60 58 bool "DDR4 PHY side ODT 60 ohm" 59 depends on DM && OF_CONTROL && ARCH_ASPEED 60 help 61 select DDR4 PHY side ODT 60 ohm 62 63config ASPEED_DDR4_PHY_ODT48 64 bool "DDR4 PHY side ODT 48 ohm" 65 depends on DM && OF_CONTROL && ARCH_ASPEED 66 help 67 select DDR4 PHY side ODT 48 ohm 68 69config ASPEED_DDR4_PHY_ODT40 70 bool "DDR4 PHY side ODT 40 ohm" 71 depends on DM && OF_CONTROL && ARCH_ASPEED 72 help 73 select DDR4 PHY side ODT 40 ohm 74endchoice 75 76choice 77 prompt "DDR4 DRAM side ODT" 78 default ASPEED_DDR4_DRAM_ODT48 79 80config ASPEED_DDR4_DRAM_ODT80 81 bool "DDR4 DRAM side ODT 80 ohm" 82 depends on DM && OF_CONTROL && ARCH_ASPEED 83 help 84 select DDR4 DRAM side ODT 80 ohm 85 86config ASPEED_DDR4_DRAM_ODT60 87 bool "DDR4 DRAM side ODT 60 ohm" 88 depends on DM && OF_CONTROL && ARCH_ASPEED 89 help 90 select DDR4 DRAM side ODT 60 ohm 91 92config ASPEED_DDR4_DRAM_ODT48 93 bool "DDR4 DRAM side ODT 48 ohm" 94 depends on DM && OF_CONTROL && ARCH_ASPEED 95 help 96 select DDR4 DRAM side ODT 48 ohm 97 98config ASPEED_DDR4_DRAM_ODT40 99 bool "DDR4 DRAM side ODT 40 ohm" 100 depends on DM && OF_CONTROL && ARCH_ASPEED 101 help 102 select DDR4 DRAM side ODT 40 ohm 103endchoice 104 105choice 106 prompt "DDR4 DRAM output driver impedance" 107 default ASPEED_DDR4_DRAM_RON_34 108 109config ASPEED_DDR4_DRAM_RON_34 110 bool "DDR4 DRAM output driver impedance 34 ohm" 111 depends on DM && OF_CONTROL && ARCH_ASPEED 112 help 113 select DDR4 DRAM output driver impedance 34 ohm 114 115config ASPEED_DDR4_DRAM_RON_48 116 bool "DDR4 DRAM output driver impedance 48 ohm" 117 depends on DM && OF_CONTROL && ARCH_ASPEED 118 help 119 select DDR4 DRAM output driver impedance 48 ohm 120endchoice 121 122config ASPEED_DDR4_WR_DATA_EYE_TRAINING_RESULT_OFFSET 123 hex "DDR PHY write data eye training result offset" 124 default 0x10 125 help 126 The offset value applied to the DDR PHY write data eye training result 127 to fine-tune the write DQ/DQS alignment. Please don't change it if you 128 are not sure what is the best value in your system. 129endif 130