1if RAM || SPL_RAM 2 3if ASPEED_AST2600 4choice 5 prompt "DDR4 target data rate" 6 default ASPEED_DDR4_1600 7 8config ASPEED_DDR4_400 9 bool "DDR4 targets at 400Mbps" 10 depends on DM && OF_CONTROL && ARCH_ASPEED 11 help 12 select DDR4 target data rate at 400M 13 14config ASPEED_DDR4_800 15 bool "DDR4 targets at 800Mbps" 16 depends on DM && OF_CONTROL && ARCH_ASPEED 17 help 18 select DDR4 target data rate at 800M 19 20config ASPEED_DDR4_1333 21 bool "DDR4 targets at 1333Mbps" 22 depends on DM && OF_CONTROL && ARCH_ASPEED 23 help 24 select DDR4 target data rate at 1333M 25 26config ASPEED_DDR4_1600 27 bool "DDR4 targets at 1600Mbps" 28 depends on DM && OF_CONTROL && ARCH_ASPEED 29 help 30 select DDR4 target data rate at 1600M 31endchoice 32 33config ASPEED_DDR4_DUALX8 34 bool "dual X8 DDR4 die" 35 depends on DM && OF_CONTROL && ARCH_ASPEED 36 default n 37 help 38 select dual X8 DDR4 die 39 40config ASPEED_BYPASS_SELFTEST 41 bool "bypass self test during DRAM initialization" 42 default n 43 help 44 Say Y here to bypass DRAM self test to speed up the boot time 45 46choice 47 prompt "DDR4 PHY side ODT" 48 default ASPEED_DDR4_PHY_ODT80 49 50config ASPEED_DDR4_PHY_ODT80 51 bool "DDR4 PHY side ODT 80 ohm" 52 depends on DM && OF_CONTROL && ARCH_ASPEED 53 help 54 select DDR4 PHY side ODT 80 ohm 55 56config ASPEED_DDR4_PHY_ODT60 57 bool "DDR4 PHY side ODT 60 ohm" 58 depends on DM && OF_CONTROL && ARCH_ASPEED 59 help 60 select DDR4 PHY side ODT 60 ohm 61 62config ASPEED_DDR4_PHY_ODT48 63 bool "DDR4 PHY side ODT 48 ohm" 64 depends on DM && OF_CONTROL && ARCH_ASPEED 65 help 66 select DDR4 PHY side ODT 48 ohm 67 68config ASPEED_DDR4_PHY_ODT40 69 bool "DDR4 PHY side ODT 40 ohm" 70 depends on DM && OF_CONTROL && ARCH_ASPEED 71 help 72 select DDR4 PHY side ODT 40 ohm 73endchoice 74 75choice 76 prompt "DDR4 DRAM side ODT" 77 default ASPEED_DDR4_DRAM_ODT48 78 79config ASPEED_DDR4_DRAM_ODT80 80 bool "DDR4 DRAM side ODT 80 ohm" 81 depends on DM && OF_CONTROL && ARCH_ASPEED 82 help 83 select DDR4 DRAM side ODT 80 ohm 84 85config ASPEED_DDR4_DRAM_ODT60 86 bool "DDR4 DRAM side ODT 60 ohm" 87 depends on DM && OF_CONTROL && ARCH_ASPEED 88 help 89 select DDR4 DRAM side ODT 60 ohm 90 91config ASPEED_DDR4_DRAM_ODT48 92 bool "DDR4 DRAM side ODT 48 ohm" 93 depends on DM && OF_CONTROL && ARCH_ASPEED 94 help 95 select DDR4 DRAM side ODT 48 ohm 96 97config ASPEED_DDR4_DRAM_ODT40 98 bool "DDR4 DRAM side ODT 40 ohm" 99 depends on DM && OF_CONTROL && ARCH_ASPEED 100 help 101 select DDR4 DRAM side ODT 40 ohm 102endchoice 103 104choice 105 prompt "DDR4 DRAM output driver impedance" 106 default ASPEED_DDR4_DRAM_RON_34 107 108config ASPEED_DDR4_DRAM_RON_34 109 bool "DDR4 DRAM output driver impedance 34 ohm" 110 depends on DM && OF_CONTROL && ARCH_ASPEED 111 help 112 select DDR4 DRAM output driver impedance 34 ohm 113 114config ASPEED_DDR4_DRAM_RON_48 115 bool "DDR4 DRAM output driver impedance 48 ohm" 116 depends on DM && OF_CONTROL && ARCH_ASPEED 117 help 118 select DDR4 DRAM output driver impedance 48 ohm 119endchoice 120 121config ASPEED_DDR4_WR_DATA_EYE_TRAINING_RESULT_OFFSET 122 hex "DDR PHY write data eye training result offset" 123 default 0x10 124 help 125 The offset value applied to the DDR PHY write data eye training result 126 to fine-tune the write DQ/DQS alignment. Please don't change it if you 127 are not sure what is the best value in your system. 128endif 129 130endif 131