192a5848dSChia-Wei, Wangif RAM || SPL_RAM 292a5848dSChia-Wei, Wang 3c3d7eb06SDylan Hungif ASPEED_AST2600 479088fd5SDylan Hungchoice 579088fd5SDylan Hung prompt "DDR4 target data rate" 679088fd5SDylan Hung default ASPEED_DDR4_1600 779088fd5SDylan Hung 8489b054eSDylan Hungconfig ASPEED_DDR4_400 9489b054eSDylan Hung bool "DDR4 targets at 400Mbps" 10489b054eSDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 11489b054eSDylan Hung help 12489b054eSDylan Hung select DDR4 target data rate at 400M 13489b054eSDylan Hung 1479088fd5SDylan Hungconfig ASPEED_DDR4_800 1579088fd5SDylan Hung bool "DDR4 targets at 800Mbps" 1679088fd5SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 1779088fd5SDylan Hung help 1879088fd5SDylan Hung select DDR4 target data rate at 800M 1979088fd5SDylan Hung 20fd8b1ad3SDylan Hungconfig ASPEED_DDR4_1333 21fd8b1ad3SDylan Hung bool "DDR4 targets at 1333Mbps" 22fd8b1ad3SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 23fd8b1ad3SDylan Hung help 24fd8b1ad3SDylan Hung select DDR4 target data rate at 1333M 25fd8b1ad3SDylan Hung 2679088fd5SDylan Hungconfig ASPEED_DDR4_1600 2779088fd5SDylan Hung bool "DDR4 targets at 1600Mbps" 2879088fd5SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 2979088fd5SDylan Hung help 3079088fd5SDylan Hung select DDR4 target data rate at 1600M 3179088fd5SDylan Hungendchoice 3279088fd5SDylan Hung 3379088fd5SDylan Hungconfig ASPEED_DDR4_DUALX8 3479088fd5SDylan Hung bool "dual X8 DDR4 die" 3579088fd5SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 3679088fd5SDylan Hung default n 3779088fd5SDylan Hung help 3879088fd5SDylan Hung select dual X8 DDR4 die 39420e65f8SDylan Hung 4023156602SDylan Hungconfig ASPEED_BYPASS_SELFTEST 4123156602SDylan Hung bool "bypass self test during DRAM initialization" 4223156602SDylan Hung default n 4323156602SDylan Hung help 4423156602SDylan Hung Say Y here to bypass DRAM self test to speed up the boot time 45c3d7eb06SDylan Hungendif 4623156602SDylan Hung 47d6f57adbSDylan Hungconfig ASPEED_ECC 48d6f57adbSDylan Hung bool "aspeed SDRAM error correcting code" 49d6f57adbSDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 50ecb4ad9fSDylan Hung default n 51d6f57adbSDylan Hung help 52d6f57adbSDylan Hung enable SDRAM ECC function 530bef06a6SDylan Hung 54cbb11045SDylan Hungif ASPEED_ECC 55cbb11045SDylan Hungconfig ASPEED_ECC_SIZE 56cbb11045SDylan Hung int "ECC size: 0=driver auto-caluated" 570bef06a6SDylan Hung depends on ASPEED_ECC 58cbb11045SDylan Hung default 0 590bef06a6SDylan Hung help 60cbb11045SDylan Hung SDRAM size with the error correcting code enabled. The unit is 61cbb11045SDylan Hung in Megabytes. Noted that only the 8/9 of the configured size 62cbb11045SDylan Hung can be used by the system. The remaining 1/9 will be used by 63cbb11045SDylan Hung the ECC engine. If the size is set to 0, the sdram driver will 64cbb11045SDylan Hung calculate the SDRAM size and set the whole range be ECC enabled. 65cbb11045SDylan Hungendif 66b415f713SDylan Hung 67b415f713SDylan Hungchoice 68b415f713SDylan Hung prompt "DDR4 PHY side ODT" 69323f39fbSDylan Hung default ASPEED_DDR4_PHY_ODT80 70b415f713SDylan Hung 71dd3a6e11SDylan Hungconfig ASPEED_DDR4_PHY_ODT80 72dd3a6e11SDylan Hung bool "DDR4 PHY side ODT 80 ohm" 73dd3a6e11SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 74dd3a6e11SDylan Hung help 75dd3a6e11SDylan Hung select DDR4 PHY side ODT 80 ohm 76dd3a6e11SDylan Hung 77b415f713SDylan Hungconfig ASPEED_DDR4_PHY_ODT60 78b415f713SDylan Hung bool "DDR4 PHY side ODT 60 ohm" 79b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 80b415f713SDylan Hung help 81b415f713SDylan Hung select DDR4 PHY side ODT 60 ohm 82b415f713SDylan Hung 83b415f713SDylan Hungconfig ASPEED_DDR4_PHY_ODT48 84b415f713SDylan Hung bool "DDR4 PHY side ODT 48 ohm" 85b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 86b415f713SDylan Hung help 87b415f713SDylan Hung select DDR4 PHY side ODT 48 ohm 88b415f713SDylan Hung 89b415f713SDylan Hungconfig ASPEED_DDR4_PHY_ODT40 90b415f713SDylan Hung bool "DDR4 PHY side ODT 40 ohm" 91b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 92b415f713SDylan Hung help 93b415f713SDylan Hung select DDR4 PHY side ODT 40 ohm 94b415f713SDylan Hungendchoice 95b415f713SDylan Hung 96b415f713SDylan Hungchoice 97b415f713SDylan Hung prompt "DDR4 DRAM side ODT" 98323f39fbSDylan Hung default ASPEED_DDR4_DRAM_ODT48 99b415f713SDylan Hung 100b415f713SDylan Hungconfig ASPEED_DDR4_DRAM_ODT60 101b415f713SDylan Hung bool "DDR4 DRAM side ODT 60 ohm" 102b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 103b415f713SDylan Hung help 104b415f713SDylan Hung select DDR4 DRAM side ODT 60 ohm 105b415f713SDylan Hung 106b415f713SDylan Hungconfig ASPEED_DDR4_DRAM_ODT48 107b415f713SDylan Hung bool "DDR4 DRAM side ODT 48 ohm" 108b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 109b415f713SDylan Hung help 110b415f713SDylan Hung select DDR4 DRAM side ODT 48 ohm 111b415f713SDylan Hung 112b415f713SDylan Hungconfig ASPEED_DDR4_DRAM_ODT40 113b415f713SDylan Hung bool "DDR4 DRAM side ODT 40 ohm" 114b415f713SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 115b415f713SDylan Hung help 116b415f713SDylan Hung select DDR4 DRAM side ODT 40 ohm 117b415f713SDylan Hungendchoice 118cb2cc580SDylan Hung 119cb2cc580SDylan Hungchoice 120cb2cc580SDylan Hung prompt "DDR4 DRAM output driver impedance" 121cb2cc580SDylan Hung default ASPEED_DDR4_DRAM_RON_34 122cb2cc580SDylan Hung 123cb2cc580SDylan Hungconfig ASPEED_DDR4_DRAM_RON_34 124cb2cc580SDylan Hung bool "DDR4 DRAM output driver impedance 34 ohm" 125cb2cc580SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 126cb2cc580SDylan Hung help 127cb2cc580SDylan Hung select DDR4 DRAM output driver impedance 34 ohm 128cb2cc580SDylan Hung 129cb2cc580SDylan Hungconfig ASPEED_DDR4_DRAM_RON_48 130cb2cc580SDylan Hung bool "DDR4 DRAM output driver impedance 48 ohm" 131cb2cc580SDylan Hung depends on DM && OF_CONTROL && ARCH_ASPEED 132cb2cc580SDylan Hung help 133cb2cc580SDylan Hung select DDR4 DRAM output driver impedance 48 ohm 134cb2cc580SDylan Hungendchoice 135*16261a32SDylan Hung 136*16261a32SDylan Hungconfig ASPEED_DDR4_WR_DATA_EYE_TRAINING_RESULT_OFFSET 137*16261a32SDylan Hung hex "DDR PHY write data eye training result offset" 138*16261a32SDylan Hung default 0x10 139*16261a32SDylan Hung help 140*16261a32SDylan Hung The offset value applied to the DDR PHY write data eye training result 141*16261a32SDylan Hung to fine-tune the write DQ/DQS alignment. Please don't change it if you 142*16261a32SDylan Hung are not sure what is the best value in your system. 14392a5848dSChia-Wei, Wangendif 144