1 /* 2 * Copyright (C) 2005 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * 6 * Description: UCC ethernet driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #ifndef __UEC_PHY_H__ 17 #define __UEC_PHY_H__ 18 19 #define MII_end ((u32)-2) 20 #define MII_read ((u32)-1) 21 22 #define MIIMIND_BUSY 0x00000001 23 #define MIIMIND_NOTVALID 0x00000004 24 25 #define UGETH_AN_TIMEOUT 2000 26 27 /* 1000BT control (Marvell & BCM54xx at least) */ 28 #define MII_1000BASETCONTROL 0x09 29 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 30 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 31 32 /* 1000BT status */ 33 #define MII_1000BASETSTATUS 0x0a 34 #define LPA_1000FULL 0x0400 35 #define LPA_1000HALF 0x0200 36 37 /* Cicada Extended Control Register 1 */ 38 #define MII_CIS8201_EXT_CON1 0x17 39 #define MII_CIS8201_EXTCON1_INIT 0x0000 40 41 /* Cicada Interrupt Mask Register */ 42 #define MII_CIS8201_IMASK 0x19 43 #define MII_CIS8201_IMASK_IEN 0x8000 44 #define MII_CIS8201_IMASK_SPEED 0x4000 45 #define MII_CIS8201_IMASK_LINK 0x2000 46 #define MII_CIS8201_IMASK_DUPLEX 0x1000 47 #define MII_CIS8201_IMASK_MASK 0xf000 48 49 /* Cicada Interrupt Status Register */ 50 #define MII_CIS8201_ISTAT 0x1a 51 #define MII_CIS8201_ISTAT_STATUS 0x8000 52 #define MII_CIS8201_ISTAT_SPEED 0x4000 53 #define MII_CIS8201_ISTAT_LINK 0x2000 54 #define MII_CIS8201_ISTAT_DUPLEX 0x1000 55 56 /* Cicada Auxiliary Control/Status Register */ 57 #define MII_CIS8201_AUX_CONSTAT 0x1c 58 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004 59 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 60 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 61 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 62 #define MII_CIS8201_AUXCONSTAT_100 0x0008 63 64 /* 88E1011 PHY Status Register */ 65 #define MII_M1011_PHY_SPEC_STATUS 0x11 66 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 67 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 68 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 69 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 70 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 71 #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 72 73 #define MII_M1011_IEVENT 0x13 74 #define MII_M1011_IEVENT_CLEAR 0x0000 75 76 #define MII_M1011_IMASK 0x12 77 #define MII_M1011_IMASK_INIT 0x6400 78 #define MII_M1011_IMASK_CLEAR 0x0000 79 80 /* 88E1111 PHY Register */ 81 #define MII_M1111_PHY_EXT_CR 0x14 82 #define MII_M1111_RX_DELAY 0x80 83 #define MII_M1111_TX_DELAY 0x2 84 #define MII_M1111_PHY_EXT_SR 0x1b 85 #define MII_M1111_HWCFG_MODE_MASK 0xf 86 #define MII_M1111_HWCFG_MODE_RGMII 0xb 87 88 #define MII_DM9161_SCR 0x10 89 #define MII_DM9161_SCR_INIT 0x0610 90 #define MII_DM9161_SCR_RMII_INIT 0x0710 91 92 /* DM9161 Specified Configuration and Status Register */ 93 #define MII_DM9161_SCSR 0x11 94 #define MII_DM9161_SCSR_100F 0x8000 95 #define MII_DM9161_SCSR_100H 0x4000 96 #define MII_DM9161_SCSR_10F 0x2000 97 #define MII_DM9161_SCSR_10H 0x1000 98 99 /* DM9161 Interrupt Register */ 100 #define MII_DM9161_INTR 0x15 101 #define MII_DM9161_INTR_PEND 0x8000 102 #define MII_DM9161_INTR_DPLX_MASK 0x0800 103 #define MII_DM9161_INTR_SPD_MASK 0x0400 104 #define MII_DM9161_INTR_LINK_MASK 0x0200 105 #define MII_DM9161_INTR_MASK 0x0100 106 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010 107 #define MII_DM9161_INTR_SPD_CHANGE 0x0008 108 #define MII_DM9161_INTR_LINK_CHANGE 0x0004 109 #define MII_DM9161_INTR_INIT 0x0000 110 #define MII_DM9161_INTR_STOP \ 111 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ 112 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) 113 114 /* DM9161 10BT Configuration/Status */ 115 #define MII_DM9161_10BTCSR 0x12 116 #define MII_DM9161_10BTCSR_INIT 0x7800 117 118 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ 119 SUPPORTED_10baseT_Full | \ 120 SUPPORTED_100baseT_Half | \ 121 SUPPORTED_100baseT_Full | \ 122 SUPPORTED_Autoneg | \ 123 SUPPORTED_TP | \ 124 SUPPORTED_MII) 125 126 #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ 127 SUPPORTED_1000baseT_Half | \ 128 SUPPORTED_1000baseT_Full) 129 130 #define MII_READ_COMMAND 0x00000001 131 132 #define MII_INTERRUPT_DISABLED 0x0 133 #define MII_INTERRUPT_ENABLED 0x1 134 135 #define SPEED_10 10 136 #define SPEED_100 100 137 #define SPEED_1000 1000 138 139 /* Duplex, half or full. */ 140 #define DUPLEX_HALF 0x00 141 #define DUPLEX_FULL 0x01 142 143 /* Indicates what features are supported by the interface. */ 144 #define SUPPORTED_10baseT_Half (1 << 0) 145 #define SUPPORTED_10baseT_Full (1 << 1) 146 #define SUPPORTED_100baseT_Half (1 << 2) 147 #define SUPPORTED_100baseT_Full (1 << 3) 148 #define SUPPORTED_1000baseT_Half (1 << 4) 149 #define SUPPORTED_1000baseT_Full (1 << 5) 150 #define SUPPORTED_Autoneg (1 << 6) 151 #define SUPPORTED_TP (1 << 7) 152 #define SUPPORTED_AUI (1 << 8) 153 #define SUPPORTED_MII (1 << 9) 154 #define SUPPORTED_FIBRE (1 << 10) 155 #define SUPPORTED_BNC (1 << 11) 156 #define SUPPORTED_10000baseT_Full (1 << 12) 157 158 #define ADVERTISED_10baseT_Half (1 << 0) 159 #define ADVERTISED_10baseT_Full (1 << 1) 160 #define ADVERTISED_100baseT_Half (1 << 2) 161 #define ADVERTISED_100baseT_Full (1 << 3) 162 #define ADVERTISED_1000baseT_Half (1 << 4) 163 #define ADVERTISED_1000baseT_Full (1 << 5) 164 #define ADVERTISED_Autoneg (1 << 6) 165 #define ADVERTISED_TP (1 << 7) 166 #define ADVERTISED_AUI (1 << 8) 167 #define ADVERTISED_MII (1 << 9) 168 #define ADVERTISED_FIBRE (1 << 10) 169 #define ADVERTISED_BNC (1 << 11) 170 #define ADVERTISED_10000baseT_Full (1 << 12) 171 172 /* Advertisement control register. */ 173 #define ADVERTISE_SLCT 0x001f /* Selector bits */ 174 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 175 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 176 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 177 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 178 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 179 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 180 #define ADVERTISE_RESV 0x1c00 /* Unused... */ 181 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 182 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 183 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 184 185 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 186 ADVERTISE_CSMA) 187 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 188 ADVERTISE_100HALF | ADVERTISE_100FULL) 189 190 /* Taken from mii_if_info and sungem_phy.h */ 191 struct uec_mii_info { 192 /* Information about the PHY type */ 193 /* And management functions */ 194 struct phy_info *phyinfo; 195 196 struct eth_device *dev; 197 198 /* forced speed & duplex (no autoneg) 199 * partner speed & duplex & pause (autoneg) 200 */ 201 int speed; 202 int duplex; 203 int pause; 204 205 /* The most recently read link state */ 206 int link; 207 208 /* Enabled Interrupts */ 209 u32 interrupts; 210 211 u32 advertising; 212 int autoneg; 213 int mii_id; 214 215 /* private data pointer */ 216 /* For use by PHYs to maintain extra state */ 217 void *priv; 218 219 /* Provided by ethernet driver */ 220 int (*mdio_read) (struct eth_device * dev, int mii_id, int reg); 221 void (*mdio_write) (struct eth_device * dev, int mii_id, int reg, 222 int val); 223 }; 224 225 /* struct phy_info: a structure which defines attributes for a PHY 226 * 227 * id will contain a number which represents the PHY. During 228 * startup, the driver will poll the PHY to find out what its 229 * UID--as defined by registers 2 and 3--is. The 32-bit result 230 * gotten from the PHY will be ANDed with phy_id_mask to 231 * discard any bits which may change based on revision numbers 232 * unimportant to functionality 233 * 234 * There are 6 commands which take a ugeth_mii_info structure. 235 * Each PHY must declare config_aneg, and read_status. 236 */ 237 struct phy_info { 238 u32 phy_id; 239 char *name; 240 unsigned int phy_id_mask; 241 u32 features; 242 243 /* Called to initialize the PHY */ 244 int (*init) (struct uec_mii_info * mii_info); 245 246 /* Called to suspend the PHY for power */ 247 int (*suspend) (struct uec_mii_info * mii_info); 248 249 /* Reconfigures autonegotiation (or disables it) */ 250 int (*config_aneg) (struct uec_mii_info * mii_info); 251 252 /* Determines the negotiated speed and duplex */ 253 int (*read_status) (struct uec_mii_info * mii_info); 254 255 /* Clears any pending interrupts */ 256 int (*ack_interrupt) (struct uec_mii_info * mii_info); 257 258 /* Enables or disables interrupts */ 259 int (*config_intr) (struct uec_mii_info * mii_info); 260 261 /* Clears up any memory if needed */ 262 void (*close) (struct uec_mii_info * mii_info); 263 }; 264 265 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); 266 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, 267 int value); 268 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); 269 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); 270 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, 271 u32 interrupts); 272 #endif /* __UEC_PHY_H__ */ 273