1 /* 2 * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * 6 * Description: UCC ethernet driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #ifndef __UEC_PHY_H__ 13 #define __UEC_PHY_H__ 14 15 #define MII_end ((u32)-2) 16 #define MII_read ((u32)-1) 17 18 #define MIIMIND_BUSY 0x00000001 19 #define MIIMIND_NOTVALID 0x00000004 20 21 #define UGETH_AN_TIMEOUT 2000 22 23 /* Cicada Extended Control Register 1 */ 24 #define MII_CIS8201_EXT_CON1 0x17 25 #define MII_CIS8201_EXTCON1_INIT 0x0000 26 27 /* Cicada Interrupt Mask Register */ 28 #define MII_CIS8201_IMASK 0x19 29 #define MII_CIS8201_IMASK_IEN 0x8000 30 #define MII_CIS8201_IMASK_SPEED 0x4000 31 #define MII_CIS8201_IMASK_LINK 0x2000 32 #define MII_CIS8201_IMASK_DUPLEX 0x1000 33 #define MII_CIS8201_IMASK_MASK 0xf000 34 35 /* Cicada Interrupt Status Register */ 36 #define MII_CIS8201_ISTAT 0x1a 37 #define MII_CIS8201_ISTAT_STATUS 0x8000 38 #define MII_CIS8201_ISTAT_SPEED 0x4000 39 #define MII_CIS8201_ISTAT_LINK 0x2000 40 #define MII_CIS8201_ISTAT_DUPLEX 0x1000 41 42 /* Cicada Auxiliary Control/Status Register */ 43 #define MII_CIS8201_AUX_CONSTAT 0x1c 44 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004 45 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 46 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 47 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 48 #define MII_CIS8201_AUXCONSTAT_100 0x0008 49 50 /* 88E1011 PHY Status Register */ 51 #define MII_M1011_PHY_SPEC_STATUS 0x11 52 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 53 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 54 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 55 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 56 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 57 #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 58 59 #define MII_M1011_IEVENT 0x13 60 #define MII_M1011_IEVENT_CLEAR 0x0000 61 62 #define MII_M1011_IMASK 0x12 63 #define MII_M1011_IMASK_INIT 0x6400 64 #define MII_M1011_IMASK_CLEAR 0x0000 65 66 /* 88E1111 PHY Register */ 67 #define MII_M1111_PHY_EXT_CR 0x14 68 #define MII_M1111_RX_DELAY 0x80 69 #define MII_M1111_TX_DELAY 0x2 70 #define MII_M1111_PHY_EXT_SR 0x1b 71 #define MII_M1111_HWCFG_MODE_MASK 0xf 72 #define MII_M1111_HWCFG_MODE_RGMII 0xb 73 74 #define MII_DM9161_SCR 0x10 75 #define MII_DM9161_SCR_INIT 0x0610 76 #define MII_DM9161_SCR_RMII_INIT 0x0710 77 78 /* DM9161 Specified Configuration and Status Register */ 79 #define MII_DM9161_SCSR 0x11 80 #define MII_DM9161_SCSR_100F 0x8000 81 #define MII_DM9161_SCSR_100H 0x4000 82 #define MII_DM9161_SCSR_10F 0x2000 83 #define MII_DM9161_SCSR_10H 0x1000 84 85 /* DM9161 Interrupt Register */ 86 #define MII_DM9161_INTR 0x15 87 #define MII_DM9161_INTR_PEND 0x8000 88 #define MII_DM9161_INTR_DPLX_MASK 0x0800 89 #define MII_DM9161_INTR_SPD_MASK 0x0400 90 #define MII_DM9161_INTR_LINK_MASK 0x0200 91 #define MII_DM9161_INTR_MASK 0x0100 92 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010 93 #define MII_DM9161_INTR_SPD_CHANGE 0x0008 94 #define MII_DM9161_INTR_LINK_CHANGE 0x0004 95 #define MII_DM9161_INTR_INIT 0x0000 96 #define MII_DM9161_INTR_STOP \ 97 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ 98 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) 99 100 /* DM9161 10BT Configuration/Status */ 101 #define MII_DM9161_10BTCSR 0x12 102 #define MII_DM9161_10BTCSR_INIT 0x7800 103 104 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ 105 SUPPORTED_10baseT_Full | \ 106 SUPPORTED_100baseT_Half | \ 107 SUPPORTED_100baseT_Full | \ 108 SUPPORTED_Autoneg | \ 109 SUPPORTED_TP | \ 110 SUPPORTED_MII) 111 112 #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ 113 SUPPORTED_1000baseT_Half | \ 114 SUPPORTED_1000baseT_Full) 115 116 #define MII_READ_COMMAND 0x00000001 117 118 #define MII_INTERRUPT_DISABLED 0x0 119 #define MII_INTERRUPT_ENABLED 0x1 120 121 #define SPEED_10 10 122 #define SPEED_100 100 123 #define SPEED_1000 1000 124 125 /* Duplex, half or full. */ 126 #define DUPLEX_HALF 0x00 127 #define DUPLEX_FULL 0x01 128 129 /* Indicates what features are supported by the interface. */ 130 #define SUPPORTED_10baseT_Half (1 << 0) 131 #define SUPPORTED_10baseT_Full (1 << 1) 132 #define SUPPORTED_100baseT_Half (1 << 2) 133 #define SUPPORTED_100baseT_Full (1 << 3) 134 #define SUPPORTED_1000baseT_Half (1 << 4) 135 #define SUPPORTED_1000baseT_Full (1 << 5) 136 #define SUPPORTED_Autoneg (1 << 6) 137 #define SUPPORTED_TP (1 << 7) 138 #define SUPPORTED_AUI (1 << 8) 139 #define SUPPORTED_MII (1 << 9) 140 #define SUPPORTED_FIBRE (1 << 10) 141 #define SUPPORTED_BNC (1 << 11) 142 #define SUPPORTED_10000baseT_Full (1 << 12) 143 144 #define ADVERTISED_10baseT_Half (1 << 0) 145 #define ADVERTISED_10baseT_Full (1 << 1) 146 #define ADVERTISED_100baseT_Half (1 << 2) 147 #define ADVERTISED_100baseT_Full (1 << 3) 148 #define ADVERTISED_1000baseT_Half (1 << 4) 149 #define ADVERTISED_1000baseT_Full (1 << 5) 150 #define ADVERTISED_Autoneg (1 << 6) 151 #define ADVERTISED_TP (1 << 7) 152 #define ADVERTISED_AUI (1 << 8) 153 #define ADVERTISED_MII (1 << 9) 154 #define ADVERTISED_FIBRE (1 << 10) 155 #define ADVERTISED_BNC (1 << 11) 156 #define ADVERTISED_10000baseT_Full (1 << 12) 157 158 /* Taken from mii_if_info and sungem_phy.h */ 159 struct uec_mii_info { 160 /* Information about the PHY type */ 161 /* And management functions */ 162 struct phy_info *phyinfo; 163 164 struct eth_device *dev; 165 166 /* forced speed & duplex (no autoneg) 167 * partner speed & duplex & pause (autoneg) 168 */ 169 int speed; 170 int duplex; 171 int pause; 172 173 /* The most recently read link state */ 174 int link; 175 176 /* Enabled Interrupts */ 177 u32 interrupts; 178 179 u32 advertising; 180 int autoneg; 181 int mii_id; 182 183 /* private data pointer */ 184 /* For use by PHYs to maintain extra state */ 185 void *priv; 186 187 /* Provided by ethernet driver */ 188 int (*mdio_read) (struct eth_device * dev, int mii_id, int reg); 189 void (*mdio_write) (struct eth_device * dev, int mii_id, int reg, 190 int val); 191 }; 192 193 /* struct phy_info: a structure which defines attributes for a PHY 194 * 195 * id will contain a number which represents the PHY. During 196 * startup, the driver will poll the PHY to find out what its 197 * UID--as defined by registers 2 and 3--is. The 32-bit result 198 * gotten from the PHY will be ANDed with phy_id_mask to 199 * discard any bits which may change based on revision numbers 200 * unimportant to functionality 201 * 202 * There are 6 commands which take a ugeth_mii_info structure. 203 * Each PHY must declare config_aneg, and read_status. 204 */ 205 struct phy_info { 206 u32 phy_id; 207 char *name; 208 unsigned int phy_id_mask; 209 u32 features; 210 211 /* Called to initialize the PHY */ 212 int (*init) (struct uec_mii_info * mii_info); 213 214 /* Called to suspend the PHY for power */ 215 int (*suspend) (struct uec_mii_info * mii_info); 216 217 /* Reconfigures autonegotiation (or disables it) */ 218 int (*config_aneg) (struct uec_mii_info * mii_info); 219 220 /* Determines the negotiated speed and duplex */ 221 int (*read_status) (struct uec_mii_info * mii_info); 222 223 /* Clears any pending interrupts */ 224 int (*ack_interrupt) (struct uec_mii_info * mii_info); 225 226 /* Enables or disables interrupts */ 227 int (*config_intr) (struct uec_mii_info * mii_info); 228 229 /* Clears up any memory if needed */ 230 void (*close) (struct uec_mii_info * mii_info); 231 }; 232 233 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); 234 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, 235 int value); 236 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); 237 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); 238 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, 239 u32 interrupts); 240 #endif /* __UEC_PHY_H__ */ 241