xref: /openbmc/u-boot/drivers/qe/uec_phy.h (revision 1e52fea3)
1 /*
2  * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *
6  * Description: UCC ethernet driver -- PHY handling
7  *		Driver for UEC on QE
8  *		Based on 8260_io/fcc_enet.c
9  *
10  * This program is free software; you can redistribute	it and/or modify it
11  * under  the terms of	the GNU General	 Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  *
15  */
16 #ifndef __UEC_PHY_H__
17 #define __UEC_PHY_H__
18 
19 #define MII_end ((u32)-2)
20 #define MII_read ((u32)-1)
21 
22 #define MIIMIND_BUSY		0x00000001
23 #define MIIMIND_NOTVALID	0x00000004
24 
25 #define UGETH_AN_TIMEOUT	2000
26 
27 /* Cicada Extended Control Register 1 */
28 #define MII_CIS8201_EXT_CON1	    0x17
29 #define MII_CIS8201_EXTCON1_INIT    0x0000
30 
31 /* Cicada Interrupt Mask Register */
32 #define MII_CIS8201_IMASK	    0x19
33 #define MII_CIS8201_IMASK_IEN	    0x8000
34 #define MII_CIS8201_IMASK_SPEED	    0x4000
35 #define MII_CIS8201_IMASK_LINK	    0x2000
36 #define MII_CIS8201_IMASK_DUPLEX    0x1000
37 #define MII_CIS8201_IMASK_MASK	    0xf000
38 
39 /* Cicada Interrupt Status Register */
40 #define MII_CIS8201_ISTAT	    0x1a
41 #define MII_CIS8201_ISTAT_STATUS    0x8000
42 #define MII_CIS8201_ISTAT_SPEED	    0x4000
43 #define MII_CIS8201_ISTAT_LINK	    0x2000
44 #define MII_CIS8201_ISTAT_DUPLEX    0x1000
45 
46 /* Cicada Auxiliary Control/Status Register */
47 #define MII_CIS8201_AUX_CONSTAT	       0x1c
48 #define MII_CIS8201_AUXCONSTAT_INIT    0x0004
49 #define MII_CIS8201_AUXCONSTAT_DUPLEX  0x0020
50 #define MII_CIS8201_AUXCONSTAT_SPEED   0x0018
51 #define MII_CIS8201_AUXCONSTAT_GBIT    0x0010
52 #define MII_CIS8201_AUXCONSTAT_100     0x0008
53 
54 /* 88E1011 PHY Status Register */
55 #define MII_M1011_PHY_SPEC_STATUS		0x11
56 #define MII_M1011_PHY_SPEC_STATUS_1000		0x8000
57 #define MII_M1011_PHY_SPEC_STATUS_100		0x4000
58 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK	0xc000
59 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX	0x2000
60 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED	0x0800
61 #define MII_M1011_PHY_SPEC_STATUS_LINK		0x0400
62 
63 #define MII_M1011_IEVENT		0x13
64 #define MII_M1011_IEVENT_CLEAR		0x0000
65 
66 #define MII_M1011_IMASK			0x12
67 #define MII_M1011_IMASK_INIT		0x6400
68 #define MII_M1011_IMASK_CLEAR		0x0000
69 
70 /* 88E1111 PHY Register */
71 #define MII_M1111_PHY_EXT_CR            0x14
72 #define MII_M1111_RX_DELAY              0x80
73 #define MII_M1111_TX_DELAY              0x2
74 #define MII_M1111_PHY_EXT_SR            0x1b
75 #define MII_M1111_HWCFG_MODE_MASK       0xf
76 #define MII_M1111_HWCFG_MODE_RGMII      0xb
77 
78 #define MII_DM9161_SCR			0x10
79 #define MII_DM9161_SCR_INIT		0x0610
80 #define MII_DM9161_SCR_RMII_INIT	0x0710
81 
82 /* DM9161 Specified Configuration and Status Register */
83 #define MII_DM9161_SCSR			0x11
84 #define MII_DM9161_SCSR_100F		0x8000
85 #define MII_DM9161_SCSR_100H		0x4000
86 #define MII_DM9161_SCSR_10F		0x2000
87 #define MII_DM9161_SCSR_10H		0x1000
88 
89 /* DM9161 Interrupt Register */
90 #define MII_DM9161_INTR			0x15
91 #define MII_DM9161_INTR_PEND		0x8000
92 #define MII_DM9161_INTR_DPLX_MASK	0x0800
93 #define MII_DM9161_INTR_SPD_MASK	0x0400
94 #define MII_DM9161_INTR_LINK_MASK	0x0200
95 #define MII_DM9161_INTR_MASK		0x0100
96 #define MII_DM9161_INTR_DPLX_CHANGE	0x0010
97 #define MII_DM9161_INTR_SPD_CHANGE	0x0008
98 #define MII_DM9161_INTR_LINK_CHANGE	0x0004
99 #define MII_DM9161_INTR_INIT		0x0000
100 #define MII_DM9161_INTR_STOP	\
101 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
102  | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
103 
104 /* DM9161 10BT Configuration/Status */
105 #define MII_DM9161_10BTCSR		0x12
106 #define MII_DM9161_10BTCSR_INIT		0x7800
107 
108 #define MII_BASIC_FEATURES    (SUPPORTED_10baseT_Half | \
109 		 SUPPORTED_10baseT_Full | \
110 		 SUPPORTED_100baseT_Half | \
111 		 SUPPORTED_100baseT_Full | \
112 		 SUPPORTED_Autoneg | \
113 		 SUPPORTED_TP | \
114 		 SUPPORTED_MII)
115 
116 #define MII_GBIT_FEATURES    (MII_BASIC_FEATURES | \
117 		 SUPPORTED_1000baseT_Half | \
118 		 SUPPORTED_1000baseT_Full)
119 
120 #define MII_READ_COMMAND		0x00000001
121 
122 #define MII_INTERRUPT_DISABLED		0x0
123 #define MII_INTERRUPT_ENABLED		0x1
124 
125 #define SPEED_10    10
126 #define SPEED_100   100
127 #define SPEED_1000  1000
128 
129 /* Duplex, half or full. */
130 #define DUPLEX_HALF		0x00
131 #define DUPLEX_FULL		0x01
132 
133 /* Indicates what features are supported by the interface. */
134 #define SUPPORTED_10baseT_Half		(1 << 0)
135 #define SUPPORTED_10baseT_Full		(1 << 1)
136 #define SUPPORTED_100baseT_Half		(1 << 2)
137 #define SUPPORTED_100baseT_Full		(1 << 3)
138 #define SUPPORTED_1000baseT_Half	(1 << 4)
139 #define SUPPORTED_1000baseT_Full	(1 << 5)
140 #define SUPPORTED_Autoneg		(1 << 6)
141 #define SUPPORTED_TP			(1 << 7)
142 #define SUPPORTED_AUI			(1 << 8)
143 #define SUPPORTED_MII			(1 << 9)
144 #define SUPPORTED_FIBRE			(1 << 10)
145 #define SUPPORTED_BNC			(1 << 11)
146 #define SUPPORTED_10000baseT_Full	(1 << 12)
147 
148 #define ADVERTISED_10baseT_Half		(1 << 0)
149 #define ADVERTISED_10baseT_Full		(1 << 1)
150 #define ADVERTISED_100baseT_Half	(1 << 2)
151 #define ADVERTISED_100baseT_Full	(1 << 3)
152 #define ADVERTISED_1000baseT_Half	(1 << 4)
153 #define ADVERTISED_1000baseT_Full	(1 << 5)
154 #define ADVERTISED_Autoneg		(1 << 6)
155 #define ADVERTISED_TP			(1 << 7)
156 #define ADVERTISED_AUI			(1 << 8)
157 #define ADVERTISED_MII			(1 << 9)
158 #define ADVERTISED_FIBRE		(1 << 10)
159 #define ADVERTISED_BNC			(1 << 11)
160 #define ADVERTISED_10000baseT_Full	(1 << 12)
161 
162 /* Taken from mii_if_info and sungem_phy.h */
163 struct uec_mii_info {
164 	/* Information about the PHY type */
165 	/* And management functions */
166 	struct phy_info *phyinfo;
167 
168 	struct eth_device *dev;
169 
170 	/* forced speed & duplex (no autoneg)
171 	 * partner speed & duplex & pause (autoneg)
172 	 */
173 	int speed;
174 	int duplex;
175 	int pause;
176 
177 	/* The most recently read link state */
178 	int link;
179 
180 	/* Enabled Interrupts */
181 	u32 interrupts;
182 
183 	u32 advertising;
184 	int autoneg;
185 	int mii_id;
186 
187 	/* private data pointer */
188 	/* For use by PHYs to maintain extra state */
189 	void *priv;
190 
191 	/* Provided by ethernet driver */
192 	int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
193 	void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
194 			    int val);
195 };
196 
197 /* struct phy_info: a structure which defines attributes for a PHY
198  *
199  * id will contain a number which represents the PHY.  During
200  * startup, the driver will poll the PHY to find out what its
201  * UID--as defined by registers 2 and 3--is.  The 32-bit result
202  * gotten from the PHY will be ANDed with phy_id_mask to
203  * discard any bits which may change based on revision numbers
204  * unimportant to functionality
205  *
206  * There are 6 commands which take a ugeth_mii_info structure.
207  * Each PHY must declare config_aneg, and read_status.
208  */
209 struct phy_info {
210 	u32 phy_id;
211 	char *name;
212 	unsigned int phy_id_mask;
213 	u32 features;
214 
215 	/* Called to initialize the PHY */
216 	int (*init) (struct uec_mii_info * mii_info);
217 
218 	/* Called to suspend the PHY for power */
219 	int (*suspend) (struct uec_mii_info * mii_info);
220 
221 	/* Reconfigures autonegotiation (or disables it) */
222 	int (*config_aneg) (struct uec_mii_info * mii_info);
223 
224 	/* Determines the negotiated speed and duplex */
225 	int (*read_status) (struct uec_mii_info * mii_info);
226 
227 	/* Clears any pending interrupts */
228 	int (*ack_interrupt) (struct uec_mii_info * mii_info);
229 
230 	/* Enables or disables interrupts */
231 	int (*config_intr) (struct uec_mii_info * mii_info);
232 
233 	/* Clears up any memory if needed */
234 	void (*close) (struct uec_mii_info * mii_info);
235 };
236 
237 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
238 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
239 		    int value);
240 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
241 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
242 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
243 				  u32 interrupts);
244 #endif /* __UEC_PHY_H__ */
245