1 /* 2 * Copyright (C) 2005 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * 6 * Description: UCC ethernet driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #ifndef __UEC_PHY_H__ 17 #define __UEC_PHY_H__ 18 19 #define MII_end ((u32)-2) 20 #define MII_read ((u32)-1) 21 22 #define MIIMIND_BUSY 0x00000001 23 #define MIIMIND_NOTVALID 0x00000004 24 25 #define UGETH_AN_TIMEOUT 2000 26 27 /* 1000BT control (Marvell & BCM54xx at least) */ 28 #define MII_1000BASETCONTROL 0x09 29 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 30 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 31 32 /* Cicada Extended Control Register 1 */ 33 #define MII_CIS8201_EXT_CON1 0x17 34 #define MII_CIS8201_EXTCON1_INIT 0x0000 35 36 /* Cicada Interrupt Mask Register */ 37 #define MII_CIS8201_IMASK 0x19 38 #define MII_CIS8201_IMASK_IEN 0x8000 39 #define MII_CIS8201_IMASK_SPEED 0x4000 40 #define MII_CIS8201_IMASK_LINK 0x2000 41 #define MII_CIS8201_IMASK_DUPLEX 0x1000 42 #define MII_CIS8201_IMASK_MASK 0xf000 43 44 /* Cicada Interrupt Status Register */ 45 #define MII_CIS8201_ISTAT 0x1a 46 #define MII_CIS8201_ISTAT_STATUS 0x8000 47 #define MII_CIS8201_ISTAT_SPEED 0x4000 48 #define MII_CIS8201_ISTAT_LINK 0x2000 49 #define MII_CIS8201_ISTAT_DUPLEX 0x1000 50 51 /* Cicada Auxiliary Control/Status Register */ 52 #define MII_CIS8201_AUX_CONSTAT 0x1c 53 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004 54 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 55 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 56 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 57 #define MII_CIS8201_AUXCONSTAT_100 0x0008 58 59 /* 88E1011 PHY Status Register */ 60 #define MII_M1011_PHY_SPEC_STATUS 0x11 61 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 62 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 63 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 64 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 65 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 66 #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 67 68 #define MII_M1011_IEVENT 0x13 69 #define MII_M1011_IEVENT_CLEAR 0x0000 70 71 #define MII_M1011_IMASK 0x12 72 #define MII_M1011_IMASK_INIT 0x6400 73 #define MII_M1011_IMASK_CLEAR 0x0000 74 75 #define MII_DM9161_SCR 0x10 76 #define MII_DM9161_SCR_INIT 0x0610 77 #define MII_DM9161_SCR_RMII_INIT 0x0710 78 79 /* DM9161 Specified Configuration and Status Register */ 80 #define MII_DM9161_SCSR 0x11 81 #define MII_DM9161_SCSR_100F 0x8000 82 #define MII_DM9161_SCSR_100H 0x4000 83 #define MII_DM9161_SCSR_10F 0x2000 84 #define MII_DM9161_SCSR_10H 0x1000 85 86 /* DM9161 Interrupt Register */ 87 #define MII_DM9161_INTR 0x15 88 #define MII_DM9161_INTR_PEND 0x8000 89 #define MII_DM9161_INTR_DPLX_MASK 0x0800 90 #define MII_DM9161_INTR_SPD_MASK 0x0400 91 #define MII_DM9161_INTR_LINK_MASK 0x0200 92 #define MII_DM9161_INTR_MASK 0x0100 93 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010 94 #define MII_DM9161_INTR_SPD_CHANGE 0x0008 95 #define MII_DM9161_INTR_LINK_CHANGE 0x0004 96 #define MII_DM9161_INTR_INIT 0x0000 97 #define MII_DM9161_INTR_STOP \ 98 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ 99 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) 100 101 /* DM9161 10BT Configuration/Status */ 102 #define MII_DM9161_10BTCSR 0x12 103 #define MII_DM9161_10BTCSR_INIT 0x7800 104 105 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ 106 SUPPORTED_10baseT_Full | \ 107 SUPPORTED_100baseT_Half | \ 108 SUPPORTED_100baseT_Full | \ 109 SUPPORTED_Autoneg | \ 110 SUPPORTED_TP | \ 111 SUPPORTED_MII) 112 113 #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ 114 SUPPORTED_1000baseT_Half | \ 115 SUPPORTED_1000baseT_Full) 116 117 #define MII_READ_COMMAND 0x00000001 118 119 #define MII_INTERRUPT_DISABLED 0x0 120 #define MII_INTERRUPT_ENABLED 0x1 121 122 #define SPEED_10 10 123 #define SPEED_100 100 124 #define SPEED_1000 1000 125 126 /* Duplex, half or full. */ 127 #define DUPLEX_HALF 0x00 128 #define DUPLEX_FULL 0x01 129 130 /* Indicates what features are supported by the interface. */ 131 #define SUPPORTED_10baseT_Half (1 << 0) 132 #define SUPPORTED_10baseT_Full (1 << 1) 133 #define SUPPORTED_100baseT_Half (1 << 2) 134 #define SUPPORTED_100baseT_Full (1 << 3) 135 #define SUPPORTED_1000baseT_Half (1 << 4) 136 #define SUPPORTED_1000baseT_Full (1 << 5) 137 #define SUPPORTED_Autoneg (1 << 6) 138 #define SUPPORTED_TP (1 << 7) 139 #define SUPPORTED_AUI (1 << 8) 140 #define SUPPORTED_MII (1 << 9) 141 #define SUPPORTED_FIBRE (1 << 10) 142 #define SUPPORTED_BNC (1 << 11) 143 #define SUPPORTED_10000baseT_Full (1 << 12) 144 145 #define ADVERTISED_10baseT_Half (1 << 0) 146 #define ADVERTISED_10baseT_Full (1 << 1) 147 #define ADVERTISED_100baseT_Half (1 << 2) 148 #define ADVERTISED_100baseT_Full (1 << 3) 149 #define ADVERTISED_1000baseT_Half (1 << 4) 150 #define ADVERTISED_1000baseT_Full (1 << 5) 151 #define ADVERTISED_Autoneg (1 << 6) 152 #define ADVERTISED_TP (1 << 7) 153 #define ADVERTISED_AUI (1 << 8) 154 #define ADVERTISED_MII (1 << 9) 155 #define ADVERTISED_FIBRE (1 << 10) 156 #define ADVERTISED_BNC (1 << 11) 157 #define ADVERTISED_10000baseT_Full (1 << 12) 158 159 /* Advertisement control register. */ 160 #define ADVERTISE_SLCT 0x001f /* Selector bits */ 161 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 162 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 163 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 164 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 165 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 166 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 167 #define ADVERTISE_RESV 0x1c00 /* Unused... */ 168 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 169 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 170 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 171 172 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 173 ADVERTISE_CSMA) 174 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 175 ADVERTISE_100HALF | ADVERTISE_100FULL) 176 177 /* Taken from mii_if_info and sungem_phy.h */ 178 struct uec_mii_info { 179 /* Information about the PHY type */ 180 /* And management functions */ 181 struct phy_info *phyinfo; 182 183 struct eth_device *dev; 184 185 /* forced speed & duplex (no autoneg) 186 * partner speed & duplex & pause (autoneg) 187 */ 188 int speed; 189 int duplex; 190 int pause; 191 192 /* The most recently read link state */ 193 int link; 194 195 /* Enabled Interrupts */ 196 u32 interrupts; 197 198 u32 advertising; 199 int autoneg; 200 int mii_id; 201 202 /* private data pointer */ 203 /* For use by PHYs to maintain extra state */ 204 void *priv; 205 206 /* Provided by ethernet driver */ 207 int (*mdio_read) (struct eth_device * dev, int mii_id, int reg); 208 void (*mdio_write) (struct eth_device * dev, int mii_id, int reg, 209 int val); 210 }; 211 212 /* struct phy_info: a structure which defines attributes for a PHY 213 * 214 * id will contain a number which represents the PHY. During 215 * startup, the driver will poll the PHY to find out what its 216 * UID--as defined by registers 2 and 3--is. The 32-bit result 217 * gotten from the PHY will be ANDed with phy_id_mask to 218 * discard any bits which may change based on revision numbers 219 * unimportant to functionality 220 * 221 * There are 6 commands which take a ugeth_mii_info structure. 222 * Each PHY must declare config_aneg, and read_status. 223 */ 224 struct phy_info { 225 u32 phy_id; 226 char *name; 227 unsigned int phy_id_mask; 228 u32 features; 229 230 /* Called to initialize the PHY */ 231 int (*init) (struct uec_mii_info * mii_info); 232 233 /* Called to suspend the PHY for power */ 234 int (*suspend) (struct uec_mii_info * mii_info); 235 236 /* Reconfigures autonegotiation (or disables it) */ 237 int (*config_aneg) (struct uec_mii_info * mii_info); 238 239 /* Determines the negotiated speed and duplex */ 240 int (*read_status) (struct uec_mii_info * mii_info); 241 242 /* Clears any pending interrupts */ 243 int (*ack_interrupt) (struct uec_mii_info * mii_info); 244 245 /* Enables or disables interrupts */ 246 int (*config_intr) (struct uec_mii_info * mii_info); 247 248 /* Clears up any memory if needed */ 249 void (*close) (struct uec_mii_info * mii_info); 250 }; 251 252 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); 253 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, 254 int value); 255 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); 256 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); 257 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, 258 u32 interrupts); 259 #endif /* __UEC_PHY_H__ */ 260