1 /* 2 * Copyright (C) 2005 Freescale Semiconductor, Inc. 3 * 4 * Author: Shlomi Gridish 5 * 6 * Description: UCC GETH Driver -- PHY handling 7 * Driver for UEC on QE 8 * Based on 8260_io/fcc_enet.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include "common.h" 18 #include "net.h" 19 #include "malloc.h" 20 #include "asm/errno.h" 21 #include "asm/immap_qe.h" 22 #include "asm/io.h" 23 #include "qe.h" 24 #include "uccf.h" 25 #include "uec.h" 26 #include "uec_phy.h" 27 #include "miiphy.h" 28 29 #define ugphy_printk(format, arg...) \ 30 printf(format "\n", ## arg) 31 32 #define ugphy_dbg(format, arg...) \ 33 ugphy_printk(format , ## arg) 34 #define ugphy_err(format, arg...) \ 35 ugphy_printk(format , ## arg) 36 #define ugphy_info(format, arg...) \ 37 ugphy_printk(format , ## arg) 38 #define ugphy_warn(format, arg...) \ 39 ugphy_printk(format , ## arg) 40 41 #ifdef UEC_VERBOSE_DEBUG 42 #define ugphy_vdbg ugphy_dbg 43 #else 44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) 45 #endif /* UEC_VERBOSE_DEBUG */ 46 47 /*--------------------------------------------------------------------+ 48 * Fixed PHY (PHY-less) support for Ethernet Ports. 49 * 50 * Copied from cpu/ppc4xx/4xx_enet.c 51 *--------------------------------------------------------------------*/ 52 53 /* 54 * Some boards do not have a PHY for each ethernet port. These ports are known 55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate 56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) 57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned 58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network 59 * speed and duplex should be for the port. 60 * 61 * Example board header configuration file: 62 * #define CONFIG_FIXED_PHY 0xFFFFFFFF 63 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) 64 * 65 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 69 * 70 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ 71 * {name, speed, duplex}, 72 * 73 * #define CONFIG_SYS_FIXED_PHY_PORTS \ 74 * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \ 75 * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF) 76 */ 77 78 #ifndef CONFIG_FIXED_PHY 79 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ 80 #endif 81 82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS 83 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ 84 #endif 85 86 struct fixed_phy_port { 87 char name[NAMESIZE]; /* ethernet port name */ 88 unsigned int speed; /* specified speed 10,100 or 1000 */ 89 unsigned int duplex; /* specified duplex FULL or HALF */ 90 }; 91 92 static const struct fixed_phy_port fixed_phy_port[] = { 93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ 94 }; 95 96 static void config_genmii_advert (struct uec_mii_info *mii_info); 97 static void genmii_setup_forced (struct uec_mii_info *mii_info); 98 static void genmii_restart_aneg (struct uec_mii_info *mii_info); 99 static int gbit_config_aneg (struct uec_mii_info *mii_info); 100 static int genmii_config_aneg (struct uec_mii_info *mii_info); 101 static int genmii_update_link (struct uec_mii_info *mii_info); 102 static int genmii_read_status (struct uec_mii_info *mii_info); 103 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); 104 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); 105 106 /* Write value to the PHY for this device to the register at regnum, */ 107 /* waiting until the write is done before it returns. All PHY */ 108 /* configuration has to be done through the TSEC1 MIIM regs */ 109 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) 110 { 111 uec_private_t *ugeth = (uec_private_t *) dev->priv; 112 uec_mii_t *ug_regs; 113 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; 114 u32 tmp_reg; 115 116 ug_regs = ugeth->uec_mii_regs; 117 118 /* Stop the MII management read cycle */ 119 out_be32 (&ug_regs->miimcom, 0); 120 /* Setting up the MII Mangement Address Register */ 121 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; 122 out_be32 (&ug_regs->miimadd, tmp_reg); 123 124 /* Setting up the MII Mangement Control Register with the value */ 125 out_be32 (&ug_regs->miimcon, (u32) value); 126 sync(); 127 128 /* Wait till MII management write is complete */ 129 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY); 130 } 131 132 /* Reads from register regnum in the PHY for device dev, */ 133 /* returning the value. Clears miimcom first. All PHY */ 134 /* configuration has to be done through the TSEC1 MIIM regs */ 135 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) 136 { 137 uec_private_t *ugeth = (uec_private_t *) dev->priv; 138 uec_mii_t *ug_regs; 139 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; 140 u32 tmp_reg; 141 u16 value; 142 143 ug_regs = ugeth->uec_mii_regs; 144 145 /* Setting up the MII Mangement Address Register */ 146 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; 147 out_be32 (&ug_regs->miimadd, tmp_reg); 148 149 /* clear MII management command cycle */ 150 out_be32 (&ug_regs->miimcom, 0); 151 sync(); 152 153 /* Perform an MII management read cycle */ 154 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); 155 156 /* Wait till MII management write is complete */ 157 while ((in_be32 (&ug_regs->miimind)) & 158 (MIIMIND_NOT_VALID | MIIMIND_BUSY)); 159 160 /* Read MII management status */ 161 value = (u16) in_be32 (&ug_regs->miimstat); 162 if (value == 0xffff) 163 ugphy_vdbg 164 ("read wrong value : mii_id %d,mii_reg %d, base %08x", 165 mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); 166 167 return (value); 168 } 169 170 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info) 171 { 172 if (mii_info->phyinfo->ack_interrupt) 173 mii_info->phyinfo->ack_interrupt (mii_info); 174 } 175 176 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, 177 u32 interrupts) 178 { 179 mii_info->interrupts = interrupts; 180 if (mii_info->phyinfo->config_intr) 181 mii_info->phyinfo->config_intr (mii_info); 182 } 183 184 /* Writes MII_ADVERTISE with the appropriate values, after 185 * sanitizing advertise to make sure only supported features 186 * are advertised 187 */ 188 static void config_genmii_advert (struct uec_mii_info *mii_info) 189 { 190 u32 advertise; 191 u16 adv; 192 193 /* Only allow advertising what this PHY supports */ 194 mii_info->advertising &= mii_info->phyinfo->features; 195 advertise = mii_info->advertising; 196 197 /* Setup standard advertisement */ 198 adv = phy_read (mii_info, PHY_ANAR); 199 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 200 if (advertise & ADVERTISED_10baseT_Half) 201 adv |= ADVERTISE_10HALF; 202 if (advertise & ADVERTISED_10baseT_Full) 203 adv |= ADVERTISE_10FULL; 204 if (advertise & ADVERTISED_100baseT_Half) 205 adv |= ADVERTISE_100HALF; 206 if (advertise & ADVERTISED_100baseT_Full) 207 adv |= ADVERTISE_100FULL; 208 phy_write (mii_info, PHY_ANAR, adv); 209 } 210 211 static void genmii_setup_forced (struct uec_mii_info *mii_info) 212 { 213 u16 ctrl; 214 u32 features = mii_info->phyinfo->features; 215 216 ctrl = phy_read (mii_info, PHY_BMCR); 217 218 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | 219 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); 220 ctrl |= PHY_BMCR_RESET; 221 222 switch (mii_info->speed) { 223 case SPEED_1000: 224 if (features & (SUPPORTED_1000baseT_Half 225 | SUPPORTED_1000baseT_Full)) { 226 ctrl |= PHY_BMCR_1000_MBPS; 227 break; 228 } 229 mii_info->speed = SPEED_100; 230 case SPEED_100: 231 if (features & (SUPPORTED_100baseT_Half 232 | SUPPORTED_100baseT_Full)) { 233 ctrl |= PHY_BMCR_100_MBPS; 234 break; 235 } 236 mii_info->speed = SPEED_10; 237 case SPEED_10: 238 if (features & (SUPPORTED_10baseT_Half 239 | SUPPORTED_10baseT_Full)) 240 break; 241 default: /* Unsupported speed! */ 242 ugphy_err ("%s: Bad speed!", mii_info->dev->name); 243 break; 244 } 245 246 phy_write (mii_info, PHY_BMCR, ctrl); 247 } 248 249 /* Enable and Restart Autonegotiation */ 250 static void genmii_restart_aneg (struct uec_mii_info *mii_info) 251 { 252 u16 ctl; 253 254 ctl = phy_read (mii_info, PHY_BMCR); 255 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 256 phy_write (mii_info, PHY_BMCR, ctl); 257 } 258 259 static int gbit_config_aneg (struct uec_mii_info *mii_info) 260 { 261 u16 adv; 262 u32 advertise; 263 264 if (mii_info->autoneg) { 265 /* Configure the ADVERTISE register */ 266 config_genmii_advert (mii_info); 267 advertise = mii_info->advertising; 268 269 adv = phy_read (mii_info, MII_1000BASETCONTROL); 270 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | 271 MII_1000BASETCONTROL_HALFDUPLEXCAP); 272 if (advertise & SUPPORTED_1000baseT_Half) 273 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; 274 if (advertise & SUPPORTED_1000baseT_Full) 275 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; 276 phy_write (mii_info, MII_1000BASETCONTROL, adv); 277 278 /* Start/Restart aneg */ 279 genmii_restart_aneg (mii_info); 280 } else 281 genmii_setup_forced (mii_info); 282 283 return 0; 284 } 285 286 static int marvell_config_aneg (struct uec_mii_info *mii_info) 287 { 288 /* The Marvell PHY has an errata which requires 289 * that certain registers get written in order 290 * to restart autonegotiation */ 291 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); 292 293 phy_write (mii_info, 0x1d, 0x1f); 294 phy_write (mii_info, 0x1e, 0x200c); 295 phy_write (mii_info, 0x1d, 0x5); 296 phy_write (mii_info, 0x1e, 0); 297 phy_write (mii_info, 0x1e, 0x100); 298 299 gbit_config_aneg (mii_info); 300 301 return 0; 302 } 303 304 static int genmii_config_aneg (struct uec_mii_info *mii_info) 305 { 306 if (mii_info->autoneg) { 307 config_genmii_advert (mii_info); 308 genmii_restart_aneg (mii_info); 309 } else 310 genmii_setup_forced (mii_info); 311 312 return 0; 313 } 314 315 static int genmii_update_link (struct uec_mii_info *mii_info) 316 { 317 u16 status; 318 319 /* Status is read once to clear old link state */ 320 phy_read (mii_info, PHY_BMSR); 321 322 /* 323 * Wait if the link is up, and autonegotiation is in progress 324 * (ie - we're capable and it's not done) 325 */ 326 status = phy_read(mii_info, PHY_BMSR); 327 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE) 328 && !(status & PHY_BMSR_AUTN_COMP)) { 329 int i = 0; 330 331 while (!(status & PHY_BMSR_AUTN_COMP)) { 332 /* 333 * Timeout reached ? 334 */ 335 if (i > UGETH_AN_TIMEOUT) { 336 mii_info->link = 0; 337 return 0; 338 } 339 340 i++; 341 udelay(1000); /* 1 ms */ 342 status = phy_read(mii_info, PHY_BMSR); 343 } 344 mii_info->link = 1; 345 udelay(500000); /* another 500 ms (results in faster booting) */ 346 } else { 347 if (status & PHY_BMSR_LS) 348 mii_info->link = 1; 349 else 350 mii_info->link = 0; 351 } 352 353 return 0; 354 } 355 356 static int genmii_read_status (struct uec_mii_info *mii_info) 357 { 358 u16 status; 359 int err; 360 361 /* Update the link, but return if there 362 * was an error */ 363 err = genmii_update_link (mii_info); 364 if (err) 365 return err; 366 367 if (mii_info->autoneg) { 368 status = phy_read(mii_info, MII_1000BASETSTATUS); 369 370 if (status & (LPA_1000FULL | LPA_1000HALF)) { 371 mii_info->speed = SPEED_1000; 372 if (status & LPA_1000FULL) 373 mii_info->duplex = DUPLEX_FULL; 374 else 375 mii_info->duplex = DUPLEX_HALF; 376 } else { 377 status = phy_read(mii_info, PHY_ANLPAR); 378 379 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) 380 mii_info->duplex = DUPLEX_FULL; 381 else 382 mii_info->duplex = DUPLEX_HALF; 383 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) 384 mii_info->speed = SPEED_100; 385 else 386 mii_info->speed = SPEED_10; 387 } 388 mii_info->pause = 0; 389 } 390 /* On non-aneg, we assume what we put in BMCR is the speed, 391 * though magic-aneg shouldn't prevent this case from occurring 392 */ 393 394 return 0; 395 } 396 397 static int bcm_init(struct uec_mii_info *mii_info) 398 { 399 struct eth_device *edev = mii_info->dev; 400 uec_private_t *uec = edev->priv; 401 402 gbit_config_aneg(mii_info); 403 404 if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) { 405 u16 val; 406 int cnt = 50; 407 408 /* Wait for aneg to complete. */ 409 do 410 val = phy_read(mii_info, PHY_BMSR); 411 while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); 412 413 /* Set RDX clk delay. */ 414 phy_write(mii_info, 0x18, 0x7 | (7 << 12)); 415 416 val = phy_read(mii_info, 0x18); 417 /* Set RDX-RXC skew. */ 418 val |= (1 << 8); 419 val |= (7 | (7 << 12)); 420 /* Write bits 14:0. */ 421 val |= (1 << 15); 422 phy_write(mii_info, 0x18, val); 423 } 424 425 return 0; 426 } 427 428 static int marvell_init(struct uec_mii_info *mii_info) 429 { 430 struct eth_device *edev = mii_info->dev; 431 uec_private_t *uec = edev->priv; 432 433 if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) { 434 int temp; 435 436 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); 437 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 438 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); 439 440 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); 441 temp &= ~MII_M1111_HWCFG_MODE_MASK; 442 temp |= MII_M1111_HWCFG_MODE_RGMII; 443 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); 444 445 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); 446 } 447 448 return 0; 449 } 450 451 static int marvell_read_status (struct uec_mii_info *mii_info) 452 { 453 u16 status; 454 int err; 455 456 /* Update the link, but return if there 457 * was an error */ 458 err = genmii_update_link (mii_info); 459 if (err) 460 return err; 461 462 /* If the link is up, read the speed and duplex */ 463 /* If we aren't autonegotiating, assume speeds 464 * are as set */ 465 if (mii_info->autoneg && mii_info->link) { 466 int speed; 467 468 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS); 469 470 /* Get the duplexity */ 471 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) 472 mii_info->duplex = DUPLEX_FULL; 473 else 474 mii_info->duplex = DUPLEX_HALF; 475 476 /* Get the speed */ 477 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; 478 switch (speed) { 479 case MII_M1011_PHY_SPEC_STATUS_1000: 480 mii_info->speed = SPEED_1000; 481 break; 482 case MII_M1011_PHY_SPEC_STATUS_100: 483 mii_info->speed = SPEED_100; 484 break; 485 default: 486 mii_info->speed = SPEED_10; 487 break; 488 } 489 mii_info->pause = 0; 490 } 491 492 return 0; 493 } 494 495 static int marvell_ack_interrupt (struct uec_mii_info *mii_info) 496 { 497 /* Clear the interrupts by reading the reg */ 498 phy_read (mii_info, MII_M1011_IEVENT); 499 500 return 0; 501 } 502 503 static int marvell_config_intr (struct uec_mii_info *mii_info) 504 { 505 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 506 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 507 else 508 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 509 510 return 0; 511 } 512 513 static int dm9161_init (struct uec_mii_info *mii_info) 514 { 515 /* Reset the PHY */ 516 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | 517 PHY_BMCR_RESET); 518 /* PHY and MAC connect */ 519 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & 520 ~PHY_BMCR_ISO); 521 522 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); 523 524 config_genmii_advert (mii_info); 525 /* Start/restart aneg */ 526 genmii_config_aneg (mii_info); 527 528 return 0; 529 } 530 531 static int dm9161_config_aneg (struct uec_mii_info *mii_info) 532 { 533 return 0; 534 } 535 536 static int dm9161_read_status (struct uec_mii_info *mii_info) 537 { 538 u16 status; 539 int err; 540 541 /* Update the link, but return if there was an error */ 542 err = genmii_update_link (mii_info); 543 if (err) 544 return err; 545 /* If the link is up, read the speed and duplex 546 If we aren't autonegotiating assume speeds are as set */ 547 if (mii_info->autoneg && mii_info->link) { 548 status = phy_read (mii_info, MII_DM9161_SCSR); 549 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) 550 mii_info->speed = SPEED_100; 551 else 552 mii_info->speed = SPEED_10; 553 554 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) 555 mii_info->duplex = DUPLEX_FULL; 556 else 557 mii_info->duplex = DUPLEX_HALF; 558 } 559 560 return 0; 561 } 562 563 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info) 564 { 565 /* Clear the interrupt by reading the reg */ 566 phy_read (mii_info, MII_DM9161_INTR); 567 568 return 0; 569 } 570 571 static int dm9161_config_intr (struct uec_mii_info *mii_info) 572 { 573 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 574 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 575 else 576 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 577 578 return 0; 579 } 580 581 static void dm9161_close (struct uec_mii_info *mii_info) 582 { 583 } 584 585 static int fixed_phy_aneg (struct uec_mii_info *mii_info) 586 { 587 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */ 588 return 0; 589 } 590 591 static int fixed_phy_read_status (struct uec_mii_info *mii_info) 592 { 593 int i = 0; 594 595 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { 596 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name, 597 strlen(mii_info->dev->name)) == 0) { 598 mii_info->speed = fixed_phy_port[i].speed; 599 mii_info->duplex = fixed_phy_port[i].duplex; 600 mii_info->link = 1; /* Link is always UP */ 601 mii_info->pause = 0; 602 break; 603 } 604 } 605 return 0; 606 } 607 608 static int smsc_config_aneg (struct uec_mii_info *mii_info) 609 { 610 return 0; 611 } 612 613 static int smsc_read_status (struct uec_mii_info *mii_info) 614 { 615 u16 status; 616 int err; 617 618 /* Update the link, but return if there 619 * was an error */ 620 err = genmii_update_link (mii_info); 621 if (err) 622 return err; 623 624 /* If the link is up, read the speed and duplex */ 625 /* If we aren't autonegotiating, assume speeds 626 * are as set */ 627 if (mii_info->autoneg && mii_info->link) { 628 int val; 629 630 status = phy_read (mii_info, 0x1f); 631 val = (status & 0x1c) >> 2; 632 633 switch (val) { 634 case 1: 635 mii_info->duplex = DUPLEX_HALF; 636 mii_info->speed = SPEED_10; 637 break; 638 case 5: 639 mii_info->duplex = DUPLEX_FULL; 640 mii_info->speed = SPEED_10; 641 break; 642 case 2: 643 mii_info->duplex = DUPLEX_HALF; 644 mii_info->speed = SPEED_100; 645 break; 646 case 6: 647 mii_info->duplex = DUPLEX_FULL; 648 mii_info->speed = SPEED_100; 649 break; 650 } 651 mii_info->pause = 0; 652 } 653 654 return 0; 655 } 656 657 static struct phy_info phy_info_dm9161 = { 658 .phy_id = 0x0181b880, 659 .phy_id_mask = 0x0ffffff0, 660 .name = "Davicom DM9161E", 661 .init = dm9161_init, 662 .config_aneg = dm9161_config_aneg, 663 .read_status = dm9161_read_status, 664 .close = dm9161_close, 665 }; 666 667 static struct phy_info phy_info_dm9161a = { 668 .phy_id = 0x0181b8a0, 669 .phy_id_mask = 0x0ffffff0, 670 .name = "Davicom DM9161A", 671 .features = MII_BASIC_FEATURES, 672 .init = dm9161_init, 673 .config_aneg = dm9161_config_aneg, 674 .read_status = dm9161_read_status, 675 .ack_interrupt = dm9161_ack_interrupt, 676 .config_intr = dm9161_config_intr, 677 .close = dm9161_close, 678 }; 679 680 static struct phy_info phy_info_marvell = { 681 .phy_id = 0x01410c00, 682 .phy_id_mask = 0xffffff00, 683 .name = "Marvell 88E11x1", 684 .features = MII_GBIT_FEATURES, 685 .init = &marvell_init, 686 .config_aneg = &marvell_config_aneg, 687 .read_status = &marvell_read_status, 688 .ack_interrupt = &marvell_ack_interrupt, 689 .config_intr = &marvell_config_intr, 690 }; 691 692 static struct phy_info phy_info_bcm5481 = { 693 .phy_id = 0x0143bca0, 694 .phy_id_mask = 0xffffff0, 695 .name = "Broadcom 5481", 696 .features = MII_GBIT_FEATURES, 697 .read_status = genmii_read_status, 698 .init = bcm_init, 699 }; 700 701 static struct phy_info phy_info_fixedphy = { 702 .phy_id = CONFIG_FIXED_PHY, 703 .phy_id_mask = CONFIG_FIXED_PHY, 704 .name = "Fixed PHY", 705 .config_aneg = fixed_phy_aneg, 706 .read_status = fixed_phy_read_status, 707 }; 708 709 static struct phy_info phy_info_smsclan8700 = { 710 .phy_id = 0x0007c0c0, 711 .phy_id_mask = 0xfffffff0, 712 .name = "SMSC LAN8700", 713 .features = MII_BASIC_FEATURES, 714 .config_aneg = smsc_config_aneg, 715 .read_status = smsc_read_status, 716 }; 717 718 static struct phy_info phy_info_genmii = { 719 .phy_id = 0x00000000, 720 .phy_id_mask = 0x00000000, 721 .name = "Generic MII", 722 .features = MII_BASIC_FEATURES, 723 .config_aneg = genmii_config_aneg, 724 .read_status = genmii_read_status, 725 }; 726 727 static struct phy_info *phy_info[] = { 728 &phy_info_dm9161, 729 &phy_info_dm9161a, 730 &phy_info_marvell, 731 &phy_info_bcm5481, 732 &phy_info_smsclan8700, 733 &phy_info_fixedphy, 734 &phy_info_genmii, 735 NULL 736 }; 737 738 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum) 739 { 740 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum); 741 } 742 743 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) 744 { 745 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val); 746 } 747 748 /* Use the PHY ID registers to determine what type of PHY is attached 749 * to device dev. return a struct phy_info structure describing that PHY 750 */ 751 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) 752 { 753 u16 phy_reg; 754 u32 phy_ID; 755 int i; 756 struct phy_info *theInfo = NULL; 757 758 /* Grab the bits from PHYIR1, and put them in the upper half */ 759 phy_reg = phy_read (mii_info, PHY_PHYIDR1); 760 phy_ID = (phy_reg & 0xffff) << 16; 761 762 /* Grab the bits from PHYIR2, and put them in the lower half */ 763 phy_reg = phy_read (mii_info, PHY_PHYIDR2); 764 phy_ID |= (phy_reg & 0xffff); 765 766 /* loop through all the known PHY types, and find one that */ 767 /* matches the ID we read from the PHY. */ 768 for (i = 0; phy_info[i]; i++) 769 if (phy_info[i]->phy_id == 770 (phy_ID & phy_info[i]->phy_id_mask)) { 771 theInfo = phy_info[i]; 772 break; 773 } 774 775 /* This shouldn't happen, as we have generic PHY support */ 776 if (theInfo == NULL) { 777 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID); 778 return NULL; 779 } else { 780 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID); 781 } 782 783 return theInfo; 784 } 785 786 void marvell_phy_interface_mode (struct eth_device *dev, 787 enet_interface_e mode) 788 { 789 uec_private_t *uec = (uec_private_t *) dev->priv; 790 struct uec_mii_info *mii_info; 791 u16 status; 792 793 if (!uec->mii_info) { 794 printf ("%s: the PHY not initialized\n", __FUNCTION__); 795 return; 796 } 797 mii_info = uec->mii_info; 798 799 if (mode == ENET_100_RGMII) { 800 phy_write (mii_info, 0x00, 0x9140); 801 phy_write (mii_info, 0x1d, 0x001f); 802 phy_write (mii_info, 0x1e, 0x200c); 803 phy_write (mii_info, 0x1d, 0x0005); 804 phy_write (mii_info, 0x1e, 0x0000); 805 phy_write (mii_info, 0x1e, 0x0100); 806 phy_write (mii_info, 0x09, 0x0e00); 807 phy_write (mii_info, 0x04, 0x01e1); 808 phy_write (mii_info, 0x00, 0x9140); 809 phy_write (mii_info, 0x00, 0x1000); 810 udelay (100000); 811 phy_write (mii_info, 0x00, 0x2900); 812 phy_write (mii_info, 0x14, 0x0cd2); 813 phy_write (mii_info, 0x00, 0xa100); 814 phy_write (mii_info, 0x09, 0x0000); 815 phy_write (mii_info, 0x1b, 0x800b); 816 phy_write (mii_info, 0x04, 0x05e1); 817 phy_write (mii_info, 0x00, 0xa100); 818 phy_write (mii_info, 0x00, 0x2100); 819 udelay (1000000); 820 } else if (mode == ENET_10_RGMII) { 821 phy_write (mii_info, 0x14, 0x8e40); 822 phy_write (mii_info, 0x1b, 0x800b); 823 phy_write (mii_info, 0x14, 0x0c82); 824 phy_write (mii_info, 0x00, 0x8100); 825 udelay (1000000); 826 } 827 828 /* handle 88e1111 rev.B2 erratum 5.6 */ 829 if (mii_info->autoneg) { 830 status = phy_read (mii_info, PHY_BMCR); 831 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON); 832 } 833 /* now the B2 will correctly report autoneg completion status */ 834 } 835 836 void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode) 837 { 838 #ifdef CONFIG_PHY_MODE_NEED_CHANGE 839 marvell_phy_interface_mode (dev, mode); 840 #endif 841 } 842