xref: /openbmc/u-boot/drivers/qe/uec.h (revision b9b1bc8542db5f26453c45db843903dee7056244)
1 /*
2  * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  * based on source code of Shlomi Gridish
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __UEC_H__
24 #define __UEC_H__
25 
26 #include "qe.h"
27 #include "uccf.h"
28 #include <asm/fsl_enet.h>
29 
30 #define MAX_TX_THREADS				8
31 #define MAX_RX_THREADS				8
32 #define MAX_TX_QUEUES				8
33 #define MAX_RX_QUEUES				8
34 #define MAX_PREFETCHED_BDS			4
35 #define MAX_IPH_OFFSET_ENTRY			8
36 #define MAX_ENET_INIT_PARAM_ENTRIES_RX		9
37 #define MAX_ENET_INIT_PARAM_ENTRIES_TX		8
38 
39 /* UEC UPSMR (Protocol Specific Mode Register)
40  */
41 #define UPSMR_ECM	0x04000000 /* Enable CAM Miss               */
42 #define UPSMR_HSE	0x02000000 /* Hardware Statistics Enable    */
43 #define UPSMR_PRO	0x00400000 /* Promiscuous                   */
44 #define UPSMR_CAP	0x00200000 /* CAM polarity                  */
45 #define UPSMR_RSH	0x00100000 /* Receive Short Frames          */
46 #define UPSMR_RPM	0x00080000 /* Reduced Pin Mode interfaces   */
47 #define UPSMR_R10M	0x00040000 /* RGMII/RMII 10 Mode            */
48 #define UPSMR_RLPB	0x00020000 /* RMII Loopback Mode            */
49 #define UPSMR_TBIM	0x00010000 /* Ten-bit Interface Mode        */
50 #define UPSMR_RMM	0x00001000 /* RMII/RGMII Mode               */
51 #define UPSMR_CAM	0x00000400 /* CAM Address Matching          */
52 #define UPSMR_BRO	0x00000200 /* Broadcast Address             */
53 #define UPSMR_RES1	0x00002000 /* Reserved feild - must be 1    */
54 #define UPSMR_SGMM	0x00000020 /* SGMII mode    */
55 
56 #define UPSMR_INIT_VALUE	(UPSMR_HSE | UPSMR_RES1)
57 
58 /* UEC MACCFG1 (MAC Configuration 1 Register)
59  */
60 #define MACCFG1_FLOW_RX			0x00000020 /* Flow Control Rx */
61 #define MACCFG1_FLOW_TX			0x00000010 /* Flow Control Tx */
62 #define MACCFG1_ENABLE_SYNCHED_RX	0x00000008 /* Enable Rx Sync  */
63 #define MACCFG1_ENABLE_RX		0x00000004 /* Enable Rx       */
64 #define MACCFG1_ENABLE_SYNCHED_TX	0x00000002 /* Enable Tx Sync  */
65 #define MACCFG1_ENABLE_TX		0x00000001 /* Enable Tx       */
66 
67 #define MACCFG1_INIT_VALUE		(0)
68 
69 /* UEC MACCFG2 (MAC Configuration 2 Register)
70  */
71 #define MACCFG2_PREL				0x00007000
72 #define MACCFG2_PREL_SHIFT			(31 - 19)
73 #define MACCFG2_PREL_MASK			0x0000f000
74 #define MACCFG2_SRP				0x00000080
75 #define MACCFG2_STP				0x00000040
76 #define MACCFG2_RESERVED_1			0x00000020 /* must be set  */
77 #define MACCFG2_LC				0x00000010 /* Length Check */
78 #define MACCFG2_MPE				0x00000008
79 #define MACCFG2_FDX				0x00000001 /* Full Duplex  */
80 #define MACCFG2_FDX_MASK			0x00000001
81 #define MACCFG2_PAD_CRC				0x00000004
82 #define MACCFG2_CRC_EN				0x00000002
83 #define MACCFG2_PAD_AND_CRC_MODE_NONE		0x00000000
84 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY	0x00000002
85 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC	0x00000004
86 #define MACCFG2_INTERFACE_MODE_NIBBLE		0x00000100
87 #define MACCFG2_INTERFACE_MODE_BYTE		0x00000200
88 #define MACCFG2_INTERFACE_MODE_MASK		0x00000300
89 
90 #define MACCFG2_INIT_VALUE	(MACCFG2_PREL | MACCFG2_RESERVED_1 | \
91 				 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
92 
93 /* UEC Event Register
94 */
95 #define UCCE_MPD				0x80000000
96 #define UCCE_SCAR				0x40000000
97 #define UCCE_GRA				0x20000000
98 #define UCCE_CBPR				0x10000000
99 #define UCCE_BSY				0x08000000
100 #define UCCE_RXC				0x04000000
101 #define UCCE_TXC				0x02000000
102 #define UCCE_TXE				0x01000000
103 #define UCCE_TXB7				0x00800000
104 #define UCCE_TXB6				0x00400000
105 #define UCCE_TXB5				0x00200000
106 #define UCCE_TXB4				0x00100000
107 #define UCCE_TXB3				0x00080000
108 #define UCCE_TXB2				0x00040000
109 #define UCCE_TXB1				0x00020000
110 #define UCCE_TXB0				0x00010000
111 #define UCCE_RXB7				0x00008000
112 #define UCCE_RXB6				0x00004000
113 #define UCCE_RXB5				0x00002000
114 #define UCCE_RXB4				0x00001000
115 #define UCCE_RXB3				0x00000800
116 #define UCCE_RXB2				0x00000400
117 #define UCCE_RXB1				0x00000200
118 #define UCCE_RXB0				0x00000100
119 #define UCCE_RXF7				0x00000080
120 #define UCCE_RXF6				0x00000040
121 #define UCCE_RXF5				0x00000020
122 #define UCCE_RXF4				0x00000010
123 #define UCCE_RXF3				0x00000008
124 #define UCCE_RXF2				0x00000004
125 #define UCCE_RXF1				0x00000002
126 #define UCCE_RXF0				0x00000001
127 
128 #define UCCE_TXB	(UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
129 			 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
130 #define UCCE_RXB	(UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
131 			 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
132 #define UCCE_RXF	(UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
133 			 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
134 #define UCCE_OTHER	(UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
135 			 UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
136 
137 /* UEC TEMODR Register
138 */
139 #define TEMODER_SCHEDULER_ENABLE		0x2000
140 #define TEMODER_IP_CHECKSUM_GENERATE		0x0400
141 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1	0x0200
142 #define TEMODER_RMON_STATISTICS			0x0100
143 #define TEMODER_NUM_OF_QUEUES_SHIFT		(15-15)
144 
145 #define TEMODER_INIT_VALUE			0xc000
146 
147 /* UEC REMODR Register
148 */
149 #define REMODER_RX_RMON_STATISTICS_ENABLE	0x00001000
150 #define REMODER_RX_EXTENDED_FEATURES		0x80000000
151 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT	(31-9 )
152 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT	(31-10)
153 #define REMODER_RX_QOS_MODE_SHIFT		(31-15)
154 #define REMODER_RMON_STATISTICS			0x00001000
155 #define REMODER_RX_EXTENDED_FILTERING		0x00000800
156 #define REMODER_NUM_OF_QUEUES_SHIFT		(31-23)
157 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH	0x00000008
158 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH	0x00000004
159 #define REMODER_IP_CHECKSUM_CHECK		0x00000002
160 #define REMODER_IP_ADDRESS_ALIGNMENT		0x00000001
161 
162 #define REMODER_INIT_VALUE			0
163 
164 /* BMRx - Bus Mode Register */
165 #define BMR_GLB					0x20
166 #define BMR_BO_BE				0x10
167 #define BMR_DTB_SECONDARY_BUS			0x02
168 #define BMR_BDB_SECONDARY_BUS			0x01
169 
170 #define BMR_SHIFT				24
171 #define BMR_INIT_VALUE				(BMR_GLB | BMR_BO_BE)
172 
173 /* UEC UCCS (Ethernet Status Register)
174  */
175 #define UCCS_BPR				0x02
176 #define UCCS_PAU				0x02
177 #define UCCS_MPD				0x01
178 
179 /* UEC MIIMCFG (MII Management Configuration Register)
180  */
181 #define MIIMCFG_RESET_MANAGEMENT		0x80000000
182 #define MIIMCFG_NO_PREAMBLE			0x00000010
183 #define MIIMCFG_CLOCK_DIVIDE_SHIFT		(31 - 31)
184 #define MIIMCFG_CLOCK_DIVIDE_MASK		0x0000000f
185 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4	0x00000001
186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6	0x00000002
187 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8	0x00000003
188 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10	0x00000004
189 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14	0x00000005
190 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20	0x00000006
191 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28	0x00000007
192 
193 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE	\
194 	MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
195 
196 /* UEC MIIMCOM (MII Management Command Register)
197  */
198 #define MIIMCOM_SCAN_CYCLE			0x00000002 /* Scan cycle */
199 #define MIIMCOM_READ_CYCLE			0x00000001 /* Read cycle */
200 
201 /* UEC MIIMADD (MII Management Address Register)
202  */
203 #define MIIMADD_PHY_ADDRESS_SHIFT		(31 - 23)
204 #define MIIMADD_PHY_REGISTER_SHIFT		(31 - 31)
205 
206 /* UEC MIIMCON (MII Management Control Register)
207  */
208 #define MIIMCON_PHY_CONTROL_SHIFT		(31 - 31)
209 #define MIIMCON_PHY_STATUS_SHIFT		(31 - 31)
210 
211 /* UEC MIIMIND (MII Management Indicator Register)
212  */
213 #define MIIMIND_NOT_VALID			0x00000004
214 #define MIIMIND_SCAN				0x00000002
215 #define MIIMIND_BUSY				0x00000001
216 
217 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
218  */
219 #define UTBIPAR_PHY_ADDRESS_SHIFT		(31 - 31)
220 #define UTBIPAR_PHY_ADDRESS_MASK		0x0000001f
221 
222 /* UEC UESCR (Ethernet Statistics Control Register)
223  */
224 #define UESCR_AUTOZ				0x8000
225 #define UESCR_CLRCNT				0x4000
226 #define UESCR_MAXCOV_SHIFT			(15 -  7)
227 #define UESCR_SCOV_SHIFT			(15 - 15)
228 
229 /****** Tx data struct collection ******/
230 /* Tx thread data, each Tx thread has one this struct.
231 */
232 typedef struct uec_thread_data_tx {
233 	u8   res0[136];
234 } __attribute__ ((packed)) uec_thread_data_tx_t;
235 
236 /* Tx thread parameter, each Tx thread has one this struct.
237 */
238 typedef struct uec_thread_tx_pram {
239 	u8   res0[64];
240 } __attribute__ ((packed)) uec_thread_tx_pram_t;
241 
242 /* Send queue queue-descriptor, each Tx queue has one this QD
243 */
244 typedef struct uec_send_queue_qd {
245 	u32    bd_ring_base; /* pointer to BD ring base address */
246 	u8     res0[0x8];
247 	u32    last_bd_completed_address; /* last entry in BD ring */
248 	u8     res1[0x30];
249 } __attribute__ ((packed)) uec_send_queue_qd_t;
250 
251 /* Send queue memory region */
252 typedef struct uec_send_queue_mem_region {
253 	uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
254 } __attribute__ ((packed)) uec_send_queue_mem_region_t;
255 
256 /* Scheduler struct
257 */
258 typedef struct uec_scheduler {
259 	u16  cpucount0;        /* CPU packet counter */
260 	u16  cpucount1;        /* CPU packet counter */
261 	u16  cecount0;         /* QE  packet counter */
262 	u16  cecount1;         /* QE  packet counter */
263 	u16  cpucount2;        /* CPU packet counter */
264 	u16  cpucount3;        /* CPU packet counter */
265 	u16  cecount2;         /* QE  packet counter */
266 	u16  cecount3;         /* QE  packet counter */
267 	u16  cpucount4;        /* CPU packet counter */
268 	u16  cpucount5;        /* CPU packet counter */
269 	u16  cecount4;         /* QE  packet counter */
270 	u16  cecount5;         /* QE  packet counter */
271 	u16  cpucount6;        /* CPU packet counter */
272 	u16  cpucount7;        /* CPU packet counter */
273 	u16  cecount6;         /* QE  packet counter */
274 	u16  cecount7;         /* QE  packet counter */
275 	u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
276 	u32  rtsrshadow;       /* temporary variable handled by QE */
277 	u32  time;             /* temporary variable handled by QE */
278 	u32  ttl;              /* temporary variable handled by QE */
279 	u32  mblinterval;      /* max burst length interval        */
280 	u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
281 	u8   fracsiz;
282 	u8   res0[1];
283 	u8   strictpriorityq;  /* Strict Priority Mask register */
284 	u8   txasap;           /* Transmit ASAP register        */
285 	u8   extrabw;          /* Extra BandWidth register      */
286 	u8   oldwfqmask;       /* temporary variable handled by QE */
287 	u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
288 	u32  minw;             /* temporary variable handled by QE */
289 	u8   res1[0x70-0x64];
290 } __attribute__ ((packed)) uec_scheduler_t;
291 
292 /* Tx firmware counters
293 */
294 typedef struct uec_tx_firmware_statistics_pram {
295 	u32  sicoltx;            /* single collision */
296 	u32  mulcoltx;           /* multiple collision */
297 	u32  latecoltxfr;        /* late collision */
298 	u32  frabortduecol;      /* frames aborted due to tx collision */
299 	u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
300 	u32  carriersenseertx;   /* carrier sense error */
301 	u32  frtxok;             /* frames transmitted OK */
302 	u32  txfrexcessivedefer;
303 	u32  txpkts256;          /* total packets(including bad) 256~511 B */
304 	u32  txpkts512;          /* total packets(including bad) 512~1023B */
305 	u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
306 	u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
307 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
308 
309 /* Tx global parameter table
310 */
311 typedef struct uec_tx_global_pram {
312 	u16  temoder;
313 	u8   res0[0x38-0x02];
314 	u32  sqptr;
315 	u32  schedulerbasepointer;
316 	u32  txrmonbaseptr;
317 	u32  tstate;
318 	u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
319 	u32  vtagtable[0x8];
320 	u32  tqptr;
321 	u8   res2[0x80-0x74];
322 } __attribute__ ((packed)) uec_tx_global_pram_t;
323 
324 
325 /****** Rx data struct collection ******/
326 /* Rx thread data, each Rx thread has one this struct.
327 */
328 typedef struct uec_thread_data_rx {
329 	u8   res0[40];
330 } __attribute__ ((packed)) uec_thread_data_rx_t;
331 
332 /* Rx thread parameter, each Rx thread has one this struct.
333 */
334 typedef struct uec_thread_rx_pram {
335 	u8   res0[128];
336 } __attribute__ ((packed)) uec_thread_rx_pram_t;
337 
338 /* Rx firmware counters
339 */
340 typedef struct uec_rx_firmware_statistics_pram {
341 	u32   frrxfcser;         /* frames with crc error */
342 	u32   fraligner;         /* frames with alignment error */
343 	u32   inrangelenrxer;    /* in range length error */
344 	u32   outrangelenrxer;   /* out of range length error */
345 	u32   frtoolong;         /* frame too long */
346 	u32   runt;              /* runt */
347 	u32   verylongevent;     /* very long event */
348 	u32   symbolerror;       /* symbol error */
349 	u32   dropbsy;           /* drop because of BD not ready */
350 	u8    res0[0x8];
351 	u32   mismatchdrop;      /* drop because of MAC filtering */
352 	u32   underpkts;         /* total frames less than 64 octets */
353 	u32   pkts256;           /* total frames(including bad)256~511 B */
354 	u32   pkts512;           /* total frames(including bad)512~1023 B */
355 	u32   pkts1024;          /* total frames(including bad)1024~1518 B */
356 	u32   pktsjumbo;         /* total frames(including bad) >1024 B */
357 	u32   frlossinmacer;
358 	u32   pausefr;           /* pause frames */
359 	u8    res1[0x4];
360 	u32   removevlan;
361 	u32   replacevlan;
362 	u32   insertvlan;
363 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
364 
365 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
366 */
367 typedef struct uec_rx_interrupt_coalescing_entry {
368 	u32   maxvalue;
369 	u32   counter;
370 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
371 
372 typedef struct uec_rx_interrupt_coalescing_table {
373 	uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
374 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
375 
376 /* RxBD queue entry, each Rx queue has one this entry.
377 */
378 typedef struct uec_rx_bd_queues_entry {
379 	u32   bdbaseptr;         /* BD base pointer          */
380 	u32   bdptr;             /* BD pointer               */
381 	u32   externalbdbaseptr; /* external BD base pointer */
382 	u32   externalbdptr;     /* external BD pointer      */
383 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
384 
385 /* Rx global paramter table
386 */
387 typedef struct uec_rx_global_pram {
388 	u32  remoder;             /* ethernet mode reg. */
389 	u32  rqptr;               /* base pointer to the Rx Queues */
390 	u32  res0[0x1];
391 	u8   res1[0x20-0xC];
392 	u16  typeorlen;
393 	u8   res2[0x1];
394 	u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
395 	u32  rxrmonbaseptr;       /* Rx RMON statistics base */
396 	u8   res3[0x30-0x28];
397 	u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
398 	u8   res4[0x36-0x34];
399 	u8   rstate;
400 	u8   res5[0x46-0x37];
401 	u16  mrblr;               /* max receive buffer length reg. */
402 	u32  rbdqptr;             /* RxBD parameter table description */
403 	u16  mflr;                /* max frame length reg. */
404 	u16  minflr;              /* min frame length reg. */
405 	u16  maxd1;               /* max dma1 length reg. */
406 	u16  maxd2;               /* max dma2 length reg. */
407 	u32  ecamptr;             /* external CAM address */
408 	u32  l2qt;                /* VLAN priority mapping table. */
409 	u32  l3qt[0x8];           /* IP   priority mapping table. */
410 	u16  vlantype;            /* vlan type */
411 	u16  vlantci;             /* default vlan tci */
412 	u8   addressfiltering[64];/* address filtering data structure */
413 	u32  exfGlobalParam;      /* extended filtering global parameters */
414 	u8   res6[0x100-0xC4];    /* Initialize to zero */
415 } __attribute__ ((packed)) uec_rx_global_pram_t;
416 
417 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
418 
419 
420 /****** UEC common ******/
421 /* UCC statistics - hardware counters
422 */
423 typedef struct uec_hardware_statistics {
424 	u32 tx64;
425 	u32 tx127;
426 	u32 tx255;
427 	u32 rx64;
428 	u32 rx127;
429 	u32 rx255;
430 	u32 txok;
431 	u16 txcf;
432 	u32 tmca;
433 	u32 tbca;
434 	u32 rxfok;
435 	u32 rxbok;
436 	u32 rbyt;
437 	u32 rmca;
438 	u32 rbca;
439 } __attribute__ ((packed)) uec_hardware_statistics_t;
440 
441 /* InitEnet command parameter
442 */
443 typedef struct uec_init_cmd_pram {
444 	u8   resinit0;
445 	u8   resinit1;
446 	u8   resinit2;
447 	u8   resinit3;
448 	u16  resinit4;
449 	u8   res1[0x1];
450 	u8   largestexternallookupkeysize;
451 	u32  rgftgfrxglobal;
452 	u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
453 	u8   res2[0x38 - 0x30];
454 	u32  txglobal;				   /* tx global  */
455 	u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
456 	u8   res3[0x1];
457 } __attribute__ ((packed)) uec_init_cmd_pram_t;
458 
459 #define ENET_INIT_PARAM_RGF_SHIFT		(32 - 4)
460 #define ENET_INIT_PARAM_TGF_SHIFT		(32 - 8)
461 
462 #define ENET_INIT_PARAM_RISC_MASK		0x0000003f
463 #define ENET_INIT_PARAM_PTR_MASK		0x00ffffc0
464 #define ENET_INIT_PARAM_SNUM_MASK		0xff000000
465 #define ENET_INIT_PARAM_SNUM_SHIFT		24
466 
467 #define ENET_INIT_PARAM_MAGIC_RES_INIT0		0x06
468 #define ENET_INIT_PARAM_MAGIC_RES_INIT1		0x30
469 #define ENET_INIT_PARAM_MAGIC_RES_INIT2		0xff
470 #define ENET_INIT_PARAM_MAGIC_RES_INIT3		0x00
471 #define ENET_INIT_PARAM_MAGIC_RES_INIT4		0x0400
472 
473 /* structure representing 82xx Address Filtering Enet Address in PRAM
474 */
475 typedef struct uec_82xx_enet_address {
476 	u8   res1[0x2];
477 	u16  h;       /* address (MSB) */
478 	u16  m;       /* address       */
479 	u16  l;       /* address (LSB) */
480 } __attribute__ ((packed)) uec_82xx_enet_address_t;
481 
482 /* structure representing 82xx Address Filtering PRAM
483 */
484 typedef struct uec_82xx_address_filtering_pram {
485 	u32  iaddr_h;        /* individual address filter, high */
486 	u32  iaddr_l;        /* individual address filter, low  */
487 	u32  gaddr_h;        /* group address filter, high      */
488 	u32  gaddr_l;        /* group address filter, low       */
489 	uec_82xx_enet_address_t    taddr;
490 	uec_82xx_enet_address_t    paddr[4];
491 	u8                         res0[0x40-0x38];
492 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
493 
494 /* Buffer Descriptor
495 */
496 typedef struct buffer_descriptor {
497 	u16 status;
498 	u16 len;
499 	u32 data;
500 } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
501 
502 #define	SIZEOFBD		sizeof(qe_bd_t)
503 
504 /* Common BD flags
505 */
506 #define BD_WRAP			0x2000
507 #define BD_INT			0x1000
508 #define BD_LAST			0x0800
509 #define BD_CLEAN		0x3000
510 
511 /* TxBD status flags
512 */
513 #define TxBD_READY		0x8000
514 #define TxBD_PADCRC		0x4000
515 #define TxBD_WRAP		BD_WRAP
516 #define TxBD_INT		BD_INT
517 #define TxBD_LAST		BD_LAST
518 #define TxBD_TXCRC		0x0400
519 #define TxBD_DEF		0x0200
520 #define TxBD_PP			0x0100
521 #define TxBD_LC			0x0080
522 #define TxBD_RL			0x0040
523 #define TxBD_RC			0x003C
524 #define TxBD_UNDERRUN		0x0002
525 #define TxBD_TRUNC		0x0001
526 
527 #define TxBD_ERROR		(TxBD_UNDERRUN | TxBD_TRUNC)
528 
529 /* RxBD status flags
530 */
531 #define RxBD_EMPTY		0x8000
532 #define RxBD_OWNER		0x4000
533 #define RxBD_WRAP		BD_WRAP
534 #define RxBD_INT		BD_INT
535 #define RxBD_LAST		BD_LAST
536 #define RxBD_FIRST		0x0400
537 #define RxBD_CMR		0x0200
538 #define RxBD_MISS		0x0100
539 #define RxBD_BCAST		0x0080
540 #define RxBD_MCAST		0x0040
541 #define RxBD_LG			0x0020
542 #define RxBD_NO			0x0010
543 #define RxBD_SHORT		0x0008
544 #define RxBD_CRCERR		0x0004
545 #define RxBD_OVERRUN		0x0002
546 #define RxBD_IPCH		0x0001
547 
548 #define RxBD_ERROR		(RxBD_LG | RxBD_NO | RxBD_SHORT | \
549 				 RxBD_CRCERR | RxBD_OVERRUN)
550 
551 /* BD access macros
552 */
553 #define BD_STATUS(_bd)			(((p_bd_t)(_bd))->status)
554 #define BD_STATUS_SET(_bd, _val)	(((p_bd_t)(_bd))->status = _val)
555 #define BD_LENGTH(_bd)			(((p_bd_t)(_bd))->len)
556 #define BD_LENGTH_SET(_bd, _val)	(((p_bd_t)(_bd))->len = _val)
557 #define BD_DATA_CLEAR(_bd)		(((p_bd_t)(_bd))->data = 0)
558 #define BD_IS_DATA(_bd)			(((p_bd_t)(_bd))->data)
559 #define BD_DATA(_bd)			((u8 *)(((p_bd_t)(_bd))->data))
560 #define BD_DATA_SET(_bd, _data)		(((p_bd_t)(_bd))->data = (u32)(_data))
561 #define BD_ADVANCE(_bd,_status,_base)	\
562 	(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
563 
564 /* Rx Prefetched BDs
565 */
566 typedef struct uec_rx_prefetched_bds {
567     qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
568 } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
569 
570 /* Alignments
571  */
572 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT				64
573 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT				64
574 #define UEC_THREAD_RX_PRAM_ALIGNMENT				128
575 #define UEC_THREAD_TX_PRAM_ALIGNMENT				64
576 #define UEC_THREAD_DATA_ALIGNMENT				256
577 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT		32
578 #define UEC_SCHEDULER_ALIGNMENT					4
579 #define UEC_TX_STATISTICS_ALIGNMENT				4
580 #define UEC_RX_STATISTICS_ALIGNMENT				4
581 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT			4
582 #define UEC_RX_BD_QUEUES_ALIGNMENT				8
583 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT				128
584 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT	4
585 #define UEC_RX_BD_RING_ALIGNMENT				32
586 #define UEC_TX_BD_RING_ALIGNMENT				32
587 #define UEC_MRBLR_ALIGNMENT					128
588 #define UEC_RX_BD_RING_SIZE_ALIGNMENT				4
589 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT			32
590 #define UEC_RX_DATA_BUF_ALIGNMENT				64
591 
592 #define UEC_VLAN_PRIORITY_MAX					8
593 #define UEC_IP_PRIORITY_MAX					64
594 #define UEC_TX_VTAG_TABLE_ENTRY_MAX				8
595 #define UEC_RX_BD_RING_SIZE_MIN					8
596 #define UEC_TX_BD_RING_SIZE_MIN					2
597 
598 /* Ethernet speed
599 */
600 typedef enum enet_speed {
601 	ENET_SPEED_10BT,   /* 10 Base T */
602 	ENET_SPEED_100BT,  /* 100 Base T */
603 	ENET_SPEED_1000BT  /* 1000 Base T */
604 } enet_speed_e;
605 
606 /* Ethernet Address Type.
607 */
608 typedef enum enet_addr_type {
609 	ENET_ADDR_TYPE_INDIVIDUAL,
610 	ENET_ADDR_TYPE_GROUP,
611 	ENET_ADDR_TYPE_BROADCAST
612 } enet_addr_type_e;
613 
614 /* TBI / MII Set Register
615 */
616 typedef enum enet_tbi_mii_reg {
617 	ENET_TBI_MII_CR        = 0x00,
618 	ENET_TBI_MII_SR        = 0x01,
619 	ENET_TBI_MII_ANA       = 0x04,
620 	ENET_TBI_MII_ANLPBPA   = 0x05,
621 	ENET_TBI_MII_ANEX      = 0x06,
622 	ENET_TBI_MII_ANNPT     = 0x07,
623 	ENET_TBI_MII_ANLPANP   = 0x08,
624 	ENET_TBI_MII_EXST      = 0x0F,
625 	ENET_TBI_MII_JD        = 0x10,
626 	ENET_TBI_MII_TBICON    = 0x11
627 } enet_tbi_mii_reg_e;
628 
629 /* TBI MDIO register bit fields*/
630 #define TBICON_CLK_SELECT	0x0020
631 #define TBIANA_ASYMMETRIC_PAUSE	0x0100
632 #define TBIANA_SYMMETRIC_PAUSE	0x0080
633 #define TBIANA_HALF_DUPLEX	0x0040
634 #define TBIANA_FULL_DUPLEX	0x0020
635 #define TBICR_PHY_RESET		0x8000
636 #define TBICR_ANEG_ENABLE	0x1000
637 #define TBICR_RESTART_ANEG	0x0200
638 #define TBICR_FULL_DUPLEX	0x0100
639 #define TBICR_SPEED1_SET	0x0040
640 
641 #define TBIANA_SETTINGS ( \
642 		TBIANA_ASYMMETRIC_PAUSE \
643 		| TBIANA_SYMMETRIC_PAUSE \
644 		| TBIANA_FULL_DUPLEX \
645 		)
646 
647 #define TBICR_SETTINGS ( \
648 		TBICR_PHY_RESET \
649 		| TBICR_ANEG_ENABLE \
650 		| TBICR_FULL_DUPLEX \
651 		| TBICR_SPEED1_SET \
652 		)
653 
654 /* UEC number of threads
655 */
656 typedef enum uec_num_of_threads {
657 	UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
658 	UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
659 	UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
660 	UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
661 	UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
662 } uec_num_of_threads_e;
663 
664 /* UEC initialization info struct
665 */
666 #define STD_UEC_INFO(num) \
667 {			\
668 	.uf_info		= {	\
669 		.ucc_num	= CONFIG_SYS_UEC##num##_UCC_NUM,\
670 		.rx_clock	= CONFIG_SYS_UEC##num##_RX_CLK,	\
671 		.tx_clock	= CONFIG_SYS_UEC##num##_TX_CLK,	\
672 		.eth_type	= CONFIG_SYS_UEC##num##_ETH_TYPE,\
673 	},	\
674 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,	\
675 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,	\
676 	.risc_tx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
677 	.risc_rx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
678 	.tx_bd_ring_len		= 16,	\
679 	.rx_bd_ring_len		= 16,	\
680 	.phy_address		= CONFIG_SYS_UEC##num##_PHY_ADDR, \
681 	.enet_interface_type	= CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
682 	.speed			= CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
683 }
684 
685 typedef struct uec_info {
686 	ucc_fast_info_t			uf_info;
687 	uec_num_of_threads_e		num_threads_tx;
688 	uec_num_of_threads_e		num_threads_rx;
689 	unsigned int			risc_tx;
690 	unsigned int			risc_rx;
691 	u16				rx_bd_ring_len;
692 	u16				tx_bd_ring_len;
693 	u8				phy_address;
694 	enum fsl_phy_enet_if		enet_interface_type;
695 	int				speed;
696 } uec_info_t;
697 
698 /* UEC driver initialized info
699 */
700 #define MAX_RXBUF_LEN			1536
701 #define MAX_FRAME_LEN			1518
702 #define MIN_FRAME_LEN			64
703 #define MAX_DMA1_LEN			1520
704 #define MAX_DMA2_LEN			1520
705 
706 /* UEC driver private struct
707 */
708 typedef struct uec_private {
709 	uec_info_t			*uec_info;
710 	ucc_fast_private_t		*uccf;
711 	struct eth_device		*dev;
712 	uec_t				*uec_regs;
713 	uec_mii_t			*uec_mii_regs;
714 	/* enet init command parameter */
715 	uec_init_cmd_pram_t		*p_init_enet_param;
716 	u32				init_enet_param_offset;
717 	/* Rx and Tx paramter */
718 	uec_rx_global_pram_t		*p_rx_glbl_pram;
719 	u32				rx_glbl_pram_offset;
720 	uec_tx_global_pram_t		*p_tx_glbl_pram;
721 	u32				tx_glbl_pram_offset;
722 	uec_send_queue_mem_region_t	*p_send_q_mem_reg;
723 	u32				send_q_mem_reg_offset;
724 	uec_thread_data_tx_t		*p_thread_data_tx;
725 	u32				thread_dat_tx_offset;
726 	uec_thread_data_rx_t		*p_thread_data_rx;
727 	u32				thread_dat_rx_offset;
728 	uec_rx_bd_queues_entry_t	*p_rx_bd_qs_tbl;
729 	u32				rx_bd_qs_tbl_offset;
730 	/* BDs specific */
731 	u8				*p_tx_bd_ring;
732 	u32				tx_bd_ring_offset;
733 	u8				*p_rx_bd_ring;
734 	u32				rx_bd_ring_offset;
735 	u8				*p_rx_buf;
736 	u32				rx_buf_offset;
737 	volatile qe_bd_t		*txBd;
738 	volatile qe_bd_t		*rxBd;
739 	/* Status */
740 	int				mac_tx_enabled;
741 	int				mac_rx_enabled;
742 	int				grace_stopped_tx;
743 	int				grace_stopped_rx;
744 	int				the_first_run;
745 	/* PHY specific */
746 	struct uec_mii_info		*mii_info;
747 	int				oldspeed;
748 	int				oldduplex;
749 	int				oldlink;
750 } uec_private_t;
751 
752 int uec_initialize(bd_t *bis, uec_info_t *uec_info);
753 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
754 int uec_standard_init(bd_t *bis);
755 #endif /* __UEC_H__ */
756