1 /* 2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * based on source code of Shlomi Gridish 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __UEC_H__ 11 #define __UEC_H__ 12 13 #include "qe.h" 14 #include "uccf.h" 15 #include <phy.h> 16 #include <asm/fsl_enet.h> 17 18 #define MAX_TX_THREADS 8 19 #define MAX_RX_THREADS 8 20 #define MAX_TX_QUEUES 8 21 #define MAX_RX_QUEUES 8 22 #define MAX_PREFETCHED_BDS 4 23 #define MAX_IPH_OFFSET_ENTRY 8 24 #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 25 #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 26 27 /* UEC UPSMR (Protocol Specific Mode Register) 28 */ 29 #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ 30 #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ 31 #define UPSMR_PRO 0x00400000 /* Promiscuous */ 32 #define UPSMR_CAP 0x00200000 /* CAM polarity */ 33 #define UPSMR_RSH 0x00100000 /* Receive Short Frames */ 34 #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ 35 #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ 36 #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ 37 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ 38 #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ 39 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ 40 #define UPSMR_BRO 0x00000200 /* Broadcast Address */ 41 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ 42 #define UPSMR_SGMM 0x00000020 /* SGMII mode */ 43 44 #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) 45 46 /* UEC MACCFG1 (MAC Configuration 1 Register) 47 */ 48 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ 49 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ 50 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ 51 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ 52 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ 53 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ 54 55 #define MACCFG1_INIT_VALUE (0) 56 57 /* UEC MACCFG2 (MAC Configuration 2 Register) 58 */ 59 #define MACCFG2_PREL 0x00007000 60 #define MACCFG2_PREL_SHIFT (31 - 19) 61 #define MACCFG2_PREL_MASK 0x0000f000 62 #define MACCFG2_SRP 0x00000080 63 #define MACCFG2_STP 0x00000040 64 #define MACCFG2_RESERVED_1 0x00000020 /* must be set */ 65 #define MACCFG2_LC 0x00000010 /* Length Check */ 66 #define MACCFG2_MPE 0x00000008 67 #define MACCFG2_FDX 0x00000001 /* Full Duplex */ 68 #define MACCFG2_FDX_MASK 0x00000001 69 #define MACCFG2_PAD_CRC 0x00000004 70 #define MACCFG2_CRC_EN 0x00000002 71 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 72 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 73 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 74 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 75 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 76 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 77 78 #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ 79 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) 80 81 /* UEC Event Register 82 */ 83 #define UCCE_MPD 0x80000000 84 #define UCCE_SCAR 0x40000000 85 #define UCCE_GRA 0x20000000 86 #define UCCE_CBPR 0x10000000 87 #define UCCE_BSY 0x08000000 88 #define UCCE_RXC 0x04000000 89 #define UCCE_TXC 0x02000000 90 #define UCCE_TXE 0x01000000 91 #define UCCE_TXB7 0x00800000 92 #define UCCE_TXB6 0x00400000 93 #define UCCE_TXB5 0x00200000 94 #define UCCE_TXB4 0x00100000 95 #define UCCE_TXB3 0x00080000 96 #define UCCE_TXB2 0x00040000 97 #define UCCE_TXB1 0x00020000 98 #define UCCE_TXB0 0x00010000 99 #define UCCE_RXB7 0x00008000 100 #define UCCE_RXB6 0x00004000 101 #define UCCE_RXB5 0x00002000 102 #define UCCE_RXB4 0x00001000 103 #define UCCE_RXB3 0x00000800 104 #define UCCE_RXB2 0x00000400 105 #define UCCE_RXB1 0x00000200 106 #define UCCE_RXB0 0x00000100 107 #define UCCE_RXF7 0x00000080 108 #define UCCE_RXF6 0x00000040 109 #define UCCE_RXF5 0x00000020 110 #define UCCE_RXF4 0x00000010 111 #define UCCE_RXF3 0x00000008 112 #define UCCE_RXF2 0x00000004 113 #define UCCE_RXF1 0x00000002 114 #define UCCE_RXF0 0x00000001 115 116 #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ 117 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) 118 #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ 119 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) 120 #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ 121 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) 122 #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ 123 UCCE_RXC | UCCE_TXC | UCCE_TXE) 124 125 /* UEC TEMODR Register 126 */ 127 #define TEMODER_SCHEDULER_ENABLE 0x2000 128 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 129 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 130 #define TEMODER_RMON_STATISTICS 0x0100 131 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) 132 133 #define TEMODER_INIT_VALUE 0xc000 134 135 /* UEC REMODR Register 136 */ 137 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 138 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 139 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) 140 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) 141 #define REMODER_RX_QOS_MODE_SHIFT (31-15) 142 #define REMODER_RMON_STATISTICS 0x00001000 143 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 144 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) 145 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 146 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 147 #define REMODER_IP_CHECKSUM_CHECK 0x00000002 148 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 149 150 #define REMODER_INIT_VALUE 0 151 152 /* BMRx - Bus Mode Register */ 153 #define BMR_GLB 0x20 154 #define BMR_BO_BE 0x10 155 #define BMR_DTB_SECONDARY_BUS 0x02 156 #define BMR_BDB_SECONDARY_BUS 0x01 157 158 #define BMR_SHIFT 24 159 #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) 160 161 /* UEC UCCS (Ethernet Status Register) 162 */ 163 #define UCCS_BPR 0x02 164 #define UCCS_PAU 0x02 165 #define UCCS_MPD 0x01 166 167 /* UEC MIIMCFG (MII Management Configuration Register) 168 */ 169 #define MIIMCFG_RESET_MANAGEMENT 0x80000000 170 #define MIIMCFG_NO_PREAMBLE 0x00000010 171 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) 172 #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f 173 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 174 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 175 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 176 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 177 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 178 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 179 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 180 181 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ 182 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 183 184 /* UEC MIIMCOM (MII Management Command Register) 185 */ 186 #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ 187 #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ 188 189 /* UEC MIIMADD (MII Management Address Register) 190 */ 191 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) 192 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) 193 194 /* UEC MIIMCON (MII Management Control Register) 195 */ 196 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) 197 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) 198 199 /* UEC MIIMIND (MII Management Indicator Register) 200 */ 201 #define MIIMIND_NOT_VALID 0x00000004 202 #define MIIMIND_SCAN 0x00000002 203 #define MIIMIND_BUSY 0x00000001 204 205 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register) 206 */ 207 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) 208 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f 209 210 /* UEC UESCR (Ethernet Statistics Control Register) 211 */ 212 #define UESCR_AUTOZ 0x8000 213 #define UESCR_CLRCNT 0x4000 214 #define UESCR_MAXCOV_SHIFT (15 - 7) 215 #define UESCR_SCOV_SHIFT (15 - 15) 216 217 /****** Tx data struct collection ******/ 218 /* Tx thread data, each Tx thread has one this struct. 219 */ 220 typedef struct uec_thread_data_tx { 221 u8 res0[136]; 222 } __attribute__ ((packed)) uec_thread_data_tx_t; 223 224 /* Tx thread parameter, each Tx thread has one this struct. 225 */ 226 typedef struct uec_thread_tx_pram { 227 u8 res0[64]; 228 } __attribute__ ((packed)) uec_thread_tx_pram_t; 229 230 /* Send queue queue-descriptor, each Tx queue has one this QD 231 */ 232 typedef struct uec_send_queue_qd { 233 u32 bd_ring_base; /* pointer to BD ring base address */ 234 u8 res0[0x8]; 235 u32 last_bd_completed_address; /* last entry in BD ring */ 236 u8 res1[0x30]; 237 } __attribute__ ((packed)) uec_send_queue_qd_t; 238 239 /* Send queue memory region */ 240 typedef struct uec_send_queue_mem_region { 241 uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; 242 } __attribute__ ((packed)) uec_send_queue_mem_region_t; 243 244 /* Scheduler struct 245 */ 246 typedef struct uec_scheduler { 247 u16 cpucount0; /* CPU packet counter */ 248 u16 cpucount1; /* CPU packet counter */ 249 u16 cecount0; /* QE packet counter */ 250 u16 cecount1; /* QE packet counter */ 251 u16 cpucount2; /* CPU packet counter */ 252 u16 cpucount3; /* CPU packet counter */ 253 u16 cecount2; /* QE packet counter */ 254 u16 cecount3; /* QE packet counter */ 255 u16 cpucount4; /* CPU packet counter */ 256 u16 cpucount5; /* CPU packet counter */ 257 u16 cecount4; /* QE packet counter */ 258 u16 cecount5; /* QE packet counter */ 259 u16 cpucount6; /* CPU packet counter */ 260 u16 cpucount7; /* CPU packet counter */ 261 u16 cecount6; /* QE packet counter */ 262 u16 cecount7; /* QE packet counter */ 263 u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ 264 u32 rtsrshadow; /* temporary variable handled by QE */ 265 u32 time; /* temporary variable handled by QE */ 266 u32 ttl; /* temporary variable handled by QE */ 267 u32 mblinterval; /* max burst length interval */ 268 u16 nortsrbytetime; /* normalized value of byte time in tsr units */ 269 u8 fracsiz; 270 u8 res0[1]; 271 u8 strictpriorityq; /* Strict Priority Mask register */ 272 u8 txasap; /* Transmit ASAP register */ 273 u8 extrabw; /* Extra BandWidth register */ 274 u8 oldwfqmask; /* temporary variable handled by QE */ 275 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ 276 u32 minw; /* temporary variable handled by QE */ 277 u8 res1[0x70-0x64]; 278 } __attribute__ ((packed)) uec_scheduler_t; 279 280 /* Tx firmware counters 281 */ 282 typedef struct uec_tx_firmware_statistics_pram { 283 u32 sicoltx; /* single collision */ 284 u32 mulcoltx; /* multiple collision */ 285 u32 latecoltxfr; /* late collision */ 286 u32 frabortduecol; /* frames aborted due to tx collision */ 287 u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ 288 u32 carriersenseertx; /* carrier sense error */ 289 u32 frtxok; /* frames transmitted OK */ 290 u32 txfrexcessivedefer; 291 u32 txpkts256; /* total packets(including bad) 256~511 B */ 292 u32 txpkts512; /* total packets(including bad) 512~1023B */ 293 u32 txpkts1024; /* total packets(including bad) 1024~1518B */ 294 u32 txpktsjumbo; /* total packets(including bad) >1024 */ 295 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; 296 297 /* Tx global parameter table 298 */ 299 typedef struct uec_tx_global_pram { 300 u16 temoder; 301 u8 res0[0x38-0x02]; 302 u32 sqptr; 303 u32 schedulerbasepointer; 304 u32 txrmonbaseptr; 305 u32 tstate; 306 u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; 307 u32 vtagtable[0x8]; 308 u32 tqptr; 309 u8 res2[0x80-0x74]; 310 } __attribute__ ((packed)) uec_tx_global_pram_t; 311 312 313 /****** Rx data struct collection ******/ 314 /* Rx thread data, each Rx thread has one this struct. 315 */ 316 typedef struct uec_thread_data_rx { 317 u8 res0[40]; 318 } __attribute__ ((packed)) uec_thread_data_rx_t; 319 320 /* Rx thread parameter, each Rx thread has one this struct. 321 */ 322 typedef struct uec_thread_rx_pram { 323 u8 res0[128]; 324 } __attribute__ ((packed)) uec_thread_rx_pram_t; 325 326 /* Rx firmware counters 327 */ 328 typedef struct uec_rx_firmware_statistics_pram { 329 u32 frrxfcser; /* frames with crc error */ 330 u32 fraligner; /* frames with alignment error */ 331 u32 inrangelenrxer; /* in range length error */ 332 u32 outrangelenrxer; /* out of range length error */ 333 u32 frtoolong; /* frame too long */ 334 u32 runt; /* runt */ 335 u32 verylongevent; /* very long event */ 336 u32 symbolerror; /* symbol error */ 337 u32 dropbsy; /* drop because of BD not ready */ 338 u8 res0[0x8]; 339 u32 mismatchdrop; /* drop because of MAC filtering */ 340 u32 underpkts; /* total frames less than 64 octets */ 341 u32 pkts256; /* total frames(including bad)256~511 B */ 342 u32 pkts512; /* total frames(including bad)512~1023 B */ 343 u32 pkts1024; /* total frames(including bad)1024~1518 B */ 344 u32 pktsjumbo; /* total frames(including bad) >1024 B */ 345 u32 frlossinmacer; 346 u32 pausefr; /* pause frames */ 347 u8 res1[0x4]; 348 u32 removevlan; 349 u32 replacevlan; 350 u32 insertvlan; 351 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; 352 353 /* Rx interrupt coalescing entry, each Rx queue has one this entry. 354 */ 355 typedef struct uec_rx_interrupt_coalescing_entry { 356 u32 maxvalue; 357 u32 counter; 358 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; 359 360 typedef struct uec_rx_interrupt_coalescing_table { 361 uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; 362 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; 363 364 /* RxBD queue entry, each Rx queue has one this entry. 365 */ 366 typedef struct uec_rx_bd_queues_entry { 367 u32 bdbaseptr; /* BD base pointer */ 368 u32 bdptr; /* BD pointer */ 369 u32 externalbdbaseptr; /* external BD base pointer */ 370 u32 externalbdptr; /* external BD pointer */ 371 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t; 372 373 /* Rx global paramter table 374 */ 375 typedef struct uec_rx_global_pram { 376 u32 remoder; /* ethernet mode reg. */ 377 u32 rqptr; /* base pointer to the Rx Queues */ 378 u32 res0[0x1]; 379 u8 res1[0x20-0xC]; 380 u16 typeorlen; 381 u8 res2[0x1]; 382 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ 383 u32 rxrmonbaseptr; /* Rx RMON statistics base */ 384 u8 res3[0x30-0x28]; 385 u32 intcoalescingptr; /* Interrupt coalescing table pointer */ 386 u8 res4[0x36-0x34]; 387 u8 rstate; 388 u8 res5[0x46-0x37]; 389 u16 mrblr; /* max receive buffer length reg. */ 390 u32 rbdqptr; /* RxBD parameter table description */ 391 u16 mflr; /* max frame length reg. */ 392 u16 minflr; /* min frame length reg. */ 393 u16 maxd1; /* max dma1 length reg. */ 394 u16 maxd2; /* max dma2 length reg. */ 395 u32 ecamptr; /* external CAM address */ 396 u32 l2qt; /* VLAN priority mapping table. */ 397 u32 l3qt[0x8]; /* IP priority mapping table. */ 398 u16 vlantype; /* vlan type */ 399 u16 vlantci; /* default vlan tci */ 400 u8 addressfiltering[64];/* address filtering data structure */ 401 u32 exfGlobalParam; /* extended filtering global parameters */ 402 u8 res6[0x100-0xC4]; /* Initialize to zero */ 403 } __attribute__ ((packed)) uec_rx_global_pram_t; 404 405 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 406 407 408 /****** UEC common ******/ 409 /* UCC statistics - hardware counters 410 */ 411 typedef struct uec_hardware_statistics { 412 u32 tx64; 413 u32 tx127; 414 u32 tx255; 415 u32 rx64; 416 u32 rx127; 417 u32 rx255; 418 u32 txok; 419 u16 txcf; 420 u32 tmca; 421 u32 tbca; 422 u32 rxfok; 423 u32 rxbok; 424 u32 rbyt; 425 u32 rmca; 426 u32 rbca; 427 } __attribute__ ((packed)) uec_hardware_statistics_t; 428 429 /* InitEnet command parameter 430 */ 431 typedef struct uec_init_cmd_pram { 432 u8 resinit0; 433 u8 resinit1; 434 u8 resinit2; 435 u8 resinit3; 436 u16 resinit4; 437 u8 res1[0x1]; 438 u8 largestexternallookupkeysize; 439 u32 rgftgfrxglobal; 440 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ 441 u8 res2[0x38 - 0x30]; 442 u32 txglobal; /* tx global */ 443 u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ 444 u8 res3[0x1]; 445 } __attribute__ ((packed)) uec_init_cmd_pram_t; 446 447 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) 448 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) 449 450 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f 451 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 452 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 453 #define ENET_INIT_PARAM_SNUM_SHIFT 24 454 455 #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 456 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 457 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff 458 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 459 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 460 461 /* structure representing 82xx Address Filtering Enet Address in PRAM 462 */ 463 typedef struct uec_82xx_enet_address { 464 u8 res1[0x2]; 465 u16 h; /* address (MSB) */ 466 u16 m; /* address */ 467 u16 l; /* address (LSB) */ 468 } __attribute__ ((packed)) uec_82xx_enet_address_t; 469 470 /* structure representing 82xx Address Filtering PRAM 471 */ 472 typedef struct uec_82xx_address_filtering_pram { 473 u32 iaddr_h; /* individual address filter, high */ 474 u32 iaddr_l; /* individual address filter, low */ 475 u32 gaddr_h; /* group address filter, high */ 476 u32 gaddr_l; /* group address filter, low */ 477 uec_82xx_enet_address_t taddr; 478 uec_82xx_enet_address_t paddr[4]; 479 u8 res0[0x40-0x38]; 480 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; 481 482 /* Buffer Descriptor 483 */ 484 typedef struct buffer_descriptor { 485 u16 status; 486 u16 len; 487 u32 data; 488 } __attribute__ ((packed)) qe_bd_t, *p_bd_t; 489 490 #define SIZEOFBD sizeof(qe_bd_t) 491 492 /* Common BD flags 493 */ 494 #define BD_WRAP 0x2000 495 #define BD_INT 0x1000 496 #define BD_LAST 0x0800 497 #define BD_CLEAN 0x3000 498 499 /* TxBD status flags 500 */ 501 #define TxBD_READY 0x8000 502 #define TxBD_PADCRC 0x4000 503 #define TxBD_WRAP BD_WRAP 504 #define TxBD_INT BD_INT 505 #define TxBD_LAST BD_LAST 506 #define TxBD_TXCRC 0x0400 507 #define TxBD_DEF 0x0200 508 #define TxBD_PP 0x0100 509 #define TxBD_LC 0x0080 510 #define TxBD_RL 0x0040 511 #define TxBD_RC 0x003C 512 #define TxBD_UNDERRUN 0x0002 513 #define TxBD_TRUNC 0x0001 514 515 #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) 516 517 /* RxBD status flags 518 */ 519 #define RxBD_EMPTY 0x8000 520 #define RxBD_OWNER 0x4000 521 #define RxBD_WRAP BD_WRAP 522 #define RxBD_INT BD_INT 523 #define RxBD_LAST BD_LAST 524 #define RxBD_FIRST 0x0400 525 #define RxBD_CMR 0x0200 526 #define RxBD_MISS 0x0100 527 #define RxBD_BCAST 0x0080 528 #define RxBD_MCAST 0x0040 529 #define RxBD_LG 0x0020 530 #define RxBD_NO 0x0010 531 #define RxBD_SHORT 0x0008 532 #define RxBD_CRCERR 0x0004 533 #define RxBD_OVERRUN 0x0002 534 #define RxBD_IPCH 0x0001 535 536 #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ 537 RxBD_CRCERR | RxBD_OVERRUN) 538 539 /* BD access macros 540 */ 541 #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) 542 #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) 543 #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) 544 #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) 545 #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) 546 #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) 547 #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) 548 #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) 549 #define BD_ADVANCE(_bd,_status,_base) \ 550 (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) 551 552 /* Rx Prefetched BDs 553 */ 554 typedef struct uec_rx_prefetched_bds { 555 qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ 556 } __attribute__ ((packed)) uec_rx_prefetched_bds_t; 557 558 /* Alignments 559 */ 560 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 561 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 562 #define UEC_THREAD_RX_PRAM_ALIGNMENT 128 563 #define UEC_THREAD_TX_PRAM_ALIGNMENT 64 564 #define UEC_THREAD_DATA_ALIGNMENT 256 565 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 566 #define UEC_SCHEDULER_ALIGNMENT 4 567 #define UEC_TX_STATISTICS_ALIGNMENT 4 568 #define UEC_RX_STATISTICS_ALIGNMENT 4 569 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 570 #define UEC_RX_BD_QUEUES_ALIGNMENT 8 571 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 572 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 573 #define UEC_RX_BD_RING_ALIGNMENT 32 574 #define UEC_TX_BD_RING_ALIGNMENT 32 575 #define UEC_MRBLR_ALIGNMENT 128 576 #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 577 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 578 #define UEC_RX_DATA_BUF_ALIGNMENT 64 579 580 #define UEC_VLAN_PRIORITY_MAX 8 581 #define UEC_IP_PRIORITY_MAX 64 582 #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 583 #define UEC_RX_BD_RING_SIZE_MIN 8 584 #define UEC_TX_BD_RING_SIZE_MIN 2 585 586 /* Ethernet speed 587 */ 588 typedef enum enet_speed { 589 ENET_SPEED_10BT, /* 10 Base T */ 590 ENET_SPEED_100BT, /* 100 Base T */ 591 ENET_SPEED_1000BT /* 1000 Base T */ 592 } enet_speed_e; 593 594 /* Ethernet Address Type. 595 */ 596 typedef enum enet_addr_type { 597 ENET_ADDR_TYPE_INDIVIDUAL, 598 ENET_ADDR_TYPE_GROUP, 599 ENET_ADDR_TYPE_BROADCAST 600 } enet_addr_type_e; 601 602 /* TBI / MII Set Register 603 */ 604 typedef enum enet_tbi_mii_reg { 605 ENET_TBI_MII_CR = 0x00, 606 ENET_TBI_MII_SR = 0x01, 607 ENET_TBI_MII_ANA = 0x04, 608 ENET_TBI_MII_ANLPBPA = 0x05, 609 ENET_TBI_MII_ANEX = 0x06, 610 ENET_TBI_MII_ANNPT = 0x07, 611 ENET_TBI_MII_ANLPANP = 0x08, 612 ENET_TBI_MII_EXST = 0x0F, 613 ENET_TBI_MII_JD = 0x10, 614 ENET_TBI_MII_TBICON = 0x11 615 } enet_tbi_mii_reg_e; 616 617 /* TBI MDIO register bit fields*/ 618 #define TBICON_CLK_SELECT 0x0020 619 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 620 #define TBIANA_SYMMETRIC_PAUSE 0x0080 621 #define TBIANA_HALF_DUPLEX 0x0040 622 #define TBIANA_FULL_DUPLEX 0x0020 623 #define TBICR_PHY_RESET 0x8000 624 #define TBICR_ANEG_ENABLE 0x1000 625 #define TBICR_RESTART_ANEG 0x0200 626 #define TBICR_FULL_DUPLEX 0x0100 627 #define TBICR_SPEED1_SET 0x0040 628 629 #define TBIANA_SETTINGS ( \ 630 TBIANA_ASYMMETRIC_PAUSE \ 631 | TBIANA_SYMMETRIC_PAUSE \ 632 | TBIANA_FULL_DUPLEX \ 633 ) 634 635 #define TBICR_SETTINGS ( \ 636 TBICR_PHY_RESET \ 637 | TBICR_ANEG_ENABLE \ 638 | TBICR_FULL_DUPLEX \ 639 | TBICR_SPEED1_SET \ 640 ) 641 642 /* UEC number of threads 643 */ 644 typedef enum uec_num_of_threads { 645 UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ 646 UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ 647 UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ 648 UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ 649 UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ 650 } uec_num_of_threads_e; 651 652 /* UEC initialization info struct 653 */ 654 #define STD_UEC_INFO(num) \ 655 { \ 656 .uf_info = { \ 657 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ 658 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ 659 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ 660 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ 661 }, \ 662 .num_threads_tx = UEC_NUM_OF_THREADS_1, \ 663 .num_threads_rx = UEC_NUM_OF_THREADS_1, \ 664 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 665 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 666 .tx_bd_ring_len = 16, \ 667 .rx_bd_ring_len = 16, \ 668 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ 669 .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ 670 .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ 671 } 672 673 typedef struct uec_info { 674 ucc_fast_info_t uf_info; 675 uec_num_of_threads_e num_threads_tx; 676 uec_num_of_threads_e num_threads_rx; 677 unsigned int risc_tx; 678 unsigned int risc_rx; 679 u16 rx_bd_ring_len; 680 u16 tx_bd_ring_len; 681 u8 phy_address; 682 phy_interface_t enet_interface_type; 683 int speed; 684 } uec_info_t; 685 686 /* UEC driver initialized info 687 */ 688 #define MAX_RXBUF_LEN 1536 689 #define MAX_FRAME_LEN 1518 690 #define MIN_FRAME_LEN 64 691 #define MAX_DMA1_LEN 1520 692 #define MAX_DMA2_LEN 1520 693 694 /* UEC driver private struct 695 */ 696 typedef struct uec_private { 697 uec_info_t *uec_info; 698 ucc_fast_private_t *uccf; 699 struct eth_device *dev; 700 uec_t *uec_regs; 701 uec_mii_t *uec_mii_regs; 702 /* enet init command parameter */ 703 uec_init_cmd_pram_t *p_init_enet_param; 704 u32 init_enet_param_offset; 705 /* Rx and Tx paramter */ 706 uec_rx_global_pram_t *p_rx_glbl_pram; 707 u32 rx_glbl_pram_offset; 708 uec_tx_global_pram_t *p_tx_glbl_pram; 709 u32 tx_glbl_pram_offset; 710 uec_send_queue_mem_region_t *p_send_q_mem_reg; 711 u32 send_q_mem_reg_offset; 712 uec_thread_data_tx_t *p_thread_data_tx; 713 u32 thread_dat_tx_offset; 714 uec_thread_data_rx_t *p_thread_data_rx; 715 u32 thread_dat_rx_offset; 716 uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; 717 u32 rx_bd_qs_tbl_offset; 718 /* BDs specific */ 719 u8 *p_tx_bd_ring; 720 u32 tx_bd_ring_offset; 721 u8 *p_rx_bd_ring; 722 u32 rx_bd_ring_offset; 723 u8 *p_rx_buf; 724 u32 rx_buf_offset; 725 volatile qe_bd_t *txBd; 726 volatile qe_bd_t *rxBd; 727 /* Status */ 728 int mac_tx_enabled; 729 int mac_rx_enabled; 730 int grace_stopped_tx; 731 int grace_stopped_rx; 732 int the_first_run; 733 /* PHY specific */ 734 struct uec_mii_info *mii_info; 735 int oldspeed; 736 int oldduplex; 737 int oldlink; 738 } uec_private_t; 739 740 int uec_initialize(bd_t *bis, uec_info_t *uec_info); 741 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num); 742 int uec_standard_init(bd_t *bis); 743 #endif /* __UEC_H__ */ 744