1 /* 2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * based on source code of Shlomi Gridish 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __UEC_H__ 24 #define __UEC_H__ 25 26 #include "qe.h" 27 #include "uccf.h" 28 #include <phy.h> 29 #include <asm/fsl_enet.h> 30 31 #define MAX_TX_THREADS 8 32 #define MAX_RX_THREADS 8 33 #define MAX_TX_QUEUES 8 34 #define MAX_RX_QUEUES 8 35 #define MAX_PREFETCHED_BDS 4 36 #define MAX_IPH_OFFSET_ENTRY 8 37 #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 38 #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 39 40 /* UEC UPSMR (Protocol Specific Mode Register) 41 */ 42 #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ 43 #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ 44 #define UPSMR_PRO 0x00400000 /* Promiscuous */ 45 #define UPSMR_CAP 0x00200000 /* CAM polarity */ 46 #define UPSMR_RSH 0x00100000 /* Receive Short Frames */ 47 #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ 48 #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ 49 #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ 50 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ 51 #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ 52 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ 53 #define UPSMR_BRO 0x00000200 /* Broadcast Address */ 54 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ 55 #define UPSMR_SGMM 0x00000020 /* SGMII mode */ 56 57 #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) 58 59 /* UEC MACCFG1 (MAC Configuration 1 Register) 60 */ 61 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ 62 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ 63 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ 64 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ 65 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ 66 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ 67 68 #define MACCFG1_INIT_VALUE (0) 69 70 /* UEC MACCFG2 (MAC Configuration 2 Register) 71 */ 72 #define MACCFG2_PREL 0x00007000 73 #define MACCFG2_PREL_SHIFT (31 - 19) 74 #define MACCFG2_PREL_MASK 0x0000f000 75 #define MACCFG2_SRP 0x00000080 76 #define MACCFG2_STP 0x00000040 77 #define MACCFG2_RESERVED_1 0x00000020 /* must be set */ 78 #define MACCFG2_LC 0x00000010 /* Length Check */ 79 #define MACCFG2_MPE 0x00000008 80 #define MACCFG2_FDX 0x00000001 /* Full Duplex */ 81 #define MACCFG2_FDX_MASK 0x00000001 82 #define MACCFG2_PAD_CRC 0x00000004 83 #define MACCFG2_CRC_EN 0x00000002 84 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 85 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 86 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 87 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 88 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 89 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 90 91 #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ 92 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) 93 94 /* UEC Event Register 95 */ 96 #define UCCE_MPD 0x80000000 97 #define UCCE_SCAR 0x40000000 98 #define UCCE_GRA 0x20000000 99 #define UCCE_CBPR 0x10000000 100 #define UCCE_BSY 0x08000000 101 #define UCCE_RXC 0x04000000 102 #define UCCE_TXC 0x02000000 103 #define UCCE_TXE 0x01000000 104 #define UCCE_TXB7 0x00800000 105 #define UCCE_TXB6 0x00400000 106 #define UCCE_TXB5 0x00200000 107 #define UCCE_TXB4 0x00100000 108 #define UCCE_TXB3 0x00080000 109 #define UCCE_TXB2 0x00040000 110 #define UCCE_TXB1 0x00020000 111 #define UCCE_TXB0 0x00010000 112 #define UCCE_RXB7 0x00008000 113 #define UCCE_RXB6 0x00004000 114 #define UCCE_RXB5 0x00002000 115 #define UCCE_RXB4 0x00001000 116 #define UCCE_RXB3 0x00000800 117 #define UCCE_RXB2 0x00000400 118 #define UCCE_RXB1 0x00000200 119 #define UCCE_RXB0 0x00000100 120 #define UCCE_RXF7 0x00000080 121 #define UCCE_RXF6 0x00000040 122 #define UCCE_RXF5 0x00000020 123 #define UCCE_RXF4 0x00000010 124 #define UCCE_RXF3 0x00000008 125 #define UCCE_RXF2 0x00000004 126 #define UCCE_RXF1 0x00000002 127 #define UCCE_RXF0 0x00000001 128 129 #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ 130 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) 131 #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ 132 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) 133 #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ 134 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) 135 #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ 136 UCCE_RXC | UCCE_TXC | UCCE_TXE) 137 138 /* UEC TEMODR Register 139 */ 140 #define TEMODER_SCHEDULER_ENABLE 0x2000 141 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 142 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 143 #define TEMODER_RMON_STATISTICS 0x0100 144 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) 145 146 #define TEMODER_INIT_VALUE 0xc000 147 148 /* UEC REMODR Register 149 */ 150 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 151 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 152 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) 153 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) 154 #define REMODER_RX_QOS_MODE_SHIFT (31-15) 155 #define REMODER_RMON_STATISTICS 0x00001000 156 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 157 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) 158 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 159 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 160 #define REMODER_IP_CHECKSUM_CHECK 0x00000002 161 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 162 163 #define REMODER_INIT_VALUE 0 164 165 /* BMRx - Bus Mode Register */ 166 #define BMR_GLB 0x20 167 #define BMR_BO_BE 0x10 168 #define BMR_DTB_SECONDARY_BUS 0x02 169 #define BMR_BDB_SECONDARY_BUS 0x01 170 171 #define BMR_SHIFT 24 172 #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) 173 174 /* UEC UCCS (Ethernet Status Register) 175 */ 176 #define UCCS_BPR 0x02 177 #define UCCS_PAU 0x02 178 #define UCCS_MPD 0x01 179 180 /* UEC MIIMCFG (MII Management Configuration Register) 181 */ 182 #define MIIMCFG_RESET_MANAGEMENT 0x80000000 183 #define MIIMCFG_NO_PREAMBLE 0x00000010 184 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) 185 #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f 186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 187 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 188 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 189 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 190 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 191 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 192 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 193 194 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ 195 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 196 197 /* UEC MIIMCOM (MII Management Command Register) 198 */ 199 #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ 200 #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ 201 202 /* UEC MIIMADD (MII Management Address Register) 203 */ 204 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) 205 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) 206 207 /* UEC MIIMCON (MII Management Control Register) 208 */ 209 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) 210 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) 211 212 /* UEC MIIMIND (MII Management Indicator Register) 213 */ 214 #define MIIMIND_NOT_VALID 0x00000004 215 #define MIIMIND_SCAN 0x00000002 216 #define MIIMIND_BUSY 0x00000001 217 218 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register) 219 */ 220 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) 221 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f 222 223 /* UEC UESCR (Ethernet Statistics Control Register) 224 */ 225 #define UESCR_AUTOZ 0x8000 226 #define UESCR_CLRCNT 0x4000 227 #define UESCR_MAXCOV_SHIFT (15 - 7) 228 #define UESCR_SCOV_SHIFT (15 - 15) 229 230 /****** Tx data struct collection ******/ 231 /* Tx thread data, each Tx thread has one this struct. 232 */ 233 typedef struct uec_thread_data_tx { 234 u8 res0[136]; 235 } __attribute__ ((packed)) uec_thread_data_tx_t; 236 237 /* Tx thread parameter, each Tx thread has one this struct. 238 */ 239 typedef struct uec_thread_tx_pram { 240 u8 res0[64]; 241 } __attribute__ ((packed)) uec_thread_tx_pram_t; 242 243 /* Send queue queue-descriptor, each Tx queue has one this QD 244 */ 245 typedef struct uec_send_queue_qd { 246 u32 bd_ring_base; /* pointer to BD ring base address */ 247 u8 res0[0x8]; 248 u32 last_bd_completed_address; /* last entry in BD ring */ 249 u8 res1[0x30]; 250 } __attribute__ ((packed)) uec_send_queue_qd_t; 251 252 /* Send queue memory region */ 253 typedef struct uec_send_queue_mem_region { 254 uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; 255 } __attribute__ ((packed)) uec_send_queue_mem_region_t; 256 257 /* Scheduler struct 258 */ 259 typedef struct uec_scheduler { 260 u16 cpucount0; /* CPU packet counter */ 261 u16 cpucount1; /* CPU packet counter */ 262 u16 cecount0; /* QE packet counter */ 263 u16 cecount1; /* QE packet counter */ 264 u16 cpucount2; /* CPU packet counter */ 265 u16 cpucount3; /* CPU packet counter */ 266 u16 cecount2; /* QE packet counter */ 267 u16 cecount3; /* QE packet counter */ 268 u16 cpucount4; /* CPU packet counter */ 269 u16 cpucount5; /* CPU packet counter */ 270 u16 cecount4; /* QE packet counter */ 271 u16 cecount5; /* QE packet counter */ 272 u16 cpucount6; /* CPU packet counter */ 273 u16 cpucount7; /* CPU packet counter */ 274 u16 cecount6; /* QE packet counter */ 275 u16 cecount7; /* QE packet counter */ 276 u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ 277 u32 rtsrshadow; /* temporary variable handled by QE */ 278 u32 time; /* temporary variable handled by QE */ 279 u32 ttl; /* temporary variable handled by QE */ 280 u32 mblinterval; /* max burst length interval */ 281 u16 nortsrbytetime; /* normalized value of byte time in tsr units */ 282 u8 fracsiz; 283 u8 res0[1]; 284 u8 strictpriorityq; /* Strict Priority Mask register */ 285 u8 txasap; /* Transmit ASAP register */ 286 u8 extrabw; /* Extra BandWidth register */ 287 u8 oldwfqmask; /* temporary variable handled by QE */ 288 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ 289 u32 minw; /* temporary variable handled by QE */ 290 u8 res1[0x70-0x64]; 291 } __attribute__ ((packed)) uec_scheduler_t; 292 293 /* Tx firmware counters 294 */ 295 typedef struct uec_tx_firmware_statistics_pram { 296 u32 sicoltx; /* single collision */ 297 u32 mulcoltx; /* multiple collision */ 298 u32 latecoltxfr; /* late collision */ 299 u32 frabortduecol; /* frames aborted due to tx collision */ 300 u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ 301 u32 carriersenseertx; /* carrier sense error */ 302 u32 frtxok; /* frames transmitted OK */ 303 u32 txfrexcessivedefer; 304 u32 txpkts256; /* total packets(including bad) 256~511 B */ 305 u32 txpkts512; /* total packets(including bad) 512~1023B */ 306 u32 txpkts1024; /* total packets(including bad) 1024~1518B */ 307 u32 txpktsjumbo; /* total packets(including bad) >1024 */ 308 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; 309 310 /* Tx global parameter table 311 */ 312 typedef struct uec_tx_global_pram { 313 u16 temoder; 314 u8 res0[0x38-0x02]; 315 u32 sqptr; 316 u32 schedulerbasepointer; 317 u32 txrmonbaseptr; 318 u32 tstate; 319 u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; 320 u32 vtagtable[0x8]; 321 u32 tqptr; 322 u8 res2[0x80-0x74]; 323 } __attribute__ ((packed)) uec_tx_global_pram_t; 324 325 326 /****** Rx data struct collection ******/ 327 /* Rx thread data, each Rx thread has one this struct. 328 */ 329 typedef struct uec_thread_data_rx { 330 u8 res0[40]; 331 } __attribute__ ((packed)) uec_thread_data_rx_t; 332 333 /* Rx thread parameter, each Rx thread has one this struct. 334 */ 335 typedef struct uec_thread_rx_pram { 336 u8 res0[128]; 337 } __attribute__ ((packed)) uec_thread_rx_pram_t; 338 339 /* Rx firmware counters 340 */ 341 typedef struct uec_rx_firmware_statistics_pram { 342 u32 frrxfcser; /* frames with crc error */ 343 u32 fraligner; /* frames with alignment error */ 344 u32 inrangelenrxer; /* in range length error */ 345 u32 outrangelenrxer; /* out of range length error */ 346 u32 frtoolong; /* frame too long */ 347 u32 runt; /* runt */ 348 u32 verylongevent; /* very long event */ 349 u32 symbolerror; /* symbol error */ 350 u32 dropbsy; /* drop because of BD not ready */ 351 u8 res0[0x8]; 352 u32 mismatchdrop; /* drop because of MAC filtering */ 353 u32 underpkts; /* total frames less than 64 octets */ 354 u32 pkts256; /* total frames(including bad)256~511 B */ 355 u32 pkts512; /* total frames(including bad)512~1023 B */ 356 u32 pkts1024; /* total frames(including bad)1024~1518 B */ 357 u32 pktsjumbo; /* total frames(including bad) >1024 B */ 358 u32 frlossinmacer; 359 u32 pausefr; /* pause frames */ 360 u8 res1[0x4]; 361 u32 removevlan; 362 u32 replacevlan; 363 u32 insertvlan; 364 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; 365 366 /* Rx interrupt coalescing entry, each Rx queue has one this entry. 367 */ 368 typedef struct uec_rx_interrupt_coalescing_entry { 369 u32 maxvalue; 370 u32 counter; 371 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; 372 373 typedef struct uec_rx_interrupt_coalescing_table { 374 uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; 375 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; 376 377 /* RxBD queue entry, each Rx queue has one this entry. 378 */ 379 typedef struct uec_rx_bd_queues_entry { 380 u32 bdbaseptr; /* BD base pointer */ 381 u32 bdptr; /* BD pointer */ 382 u32 externalbdbaseptr; /* external BD base pointer */ 383 u32 externalbdptr; /* external BD pointer */ 384 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t; 385 386 /* Rx global paramter table 387 */ 388 typedef struct uec_rx_global_pram { 389 u32 remoder; /* ethernet mode reg. */ 390 u32 rqptr; /* base pointer to the Rx Queues */ 391 u32 res0[0x1]; 392 u8 res1[0x20-0xC]; 393 u16 typeorlen; 394 u8 res2[0x1]; 395 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ 396 u32 rxrmonbaseptr; /* Rx RMON statistics base */ 397 u8 res3[0x30-0x28]; 398 u32 intcoalescingptr; /* Interrupt coalescing table pointer */ 399 u8 res4[0x36-0x34]; 400 u8 rstate; 401 u8 res5[0x46-0x37]; 402 u16 mrblr; /* max receive buffer length reg. */ 403 u32 rbdqptr; /* RxBD parameter table description */ 404 u16 mflr; /* max frame length reg. */ 405 u16 minflr; /* min frame length reg. */ 406 u16 maxd1; /* max dma1 length reg. */ 407 u16 maxd2; /* max dma2 length reg. */ 408 u32 ecamptr; /* external CAM address */ 409 u32 l2qt; /* VLAN priority mapping table. */ 410 u32 l3qt[0x8]; /* IP priority mapping table. */ 411 u16 vlantype; /* vlan type */ 412 u16 vlantci; /* default vlan tci */ 413 u8 addressfiltering[64];/* address filtering data structure */ 414 u32 exfGlobalParam; /* extended filtering global parameters */ 415 u8 res6[0x100-0xC4]; /* Initialize to zero */ 416 } __attribute__ ((packed)) uec_rx_global_pram_t; 417 418 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 419 420 421 /****** UEC common ******/ 422 /* UCC statistics - hardware counters 423 */ 424 typedef struct uec_hardware_statistics { 425 u32 tx64; 426 u32 tx127; 427 u32 tx255; 428 u32 rx64; 429 u32 rx127; 430 u32 rx255; 431 u32 txok; 432 u16 txcf; 433 u32 tmca; 434 u32 tbca; 435 u32 rxfok; 436 u32 rxbok; 437 u32 rbyt; 438 u32 rmca; 439 u32 rbca; 440 } __attribute__ ((packed)) uec_hardware_statistics_t; 441 442 /* InitEnet command parameter 443 */ 444 typedef struct uec_init_cmd_pram { 445 u8 resinit0; 446 u8 resinit1; 447 u8 resinit2; 448 u8 resinit3; 449 u16 resinit4; 450 u8 res1[0x1]; 451 u8 largestexternallookupkeysize; 452 u32 rgftgfrxglobal; 453 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ 454 u8 res2[0x38 - 0x30]; 455 u32 txglobal; /* tx global */ 456 u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ 457 u8 res3[0x1]; 458 } __attribute__ ((packed)) uec_init_cmd_pram_t; 459 460 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) 461 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) 462 463 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f 464 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 465 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 466 #define ENET_INIT_PARAM_SNUM_SHIFT 24 467 468 #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 469 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 470 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff 471 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 472 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 473 474 /* structure representing 82xx Address Filtering Enet Address in PRAM 475 */ 476 typedef struct uec_82xx_enet_address { 477 u8 res1[0x2]; 478 u16 h; /* address (MSB) */ 479 u16 m; /* address */ 480 u16 l; /* address (LSB) */ 481 } __attribute__ ((packed)) uec_82xx_enet_address_t; 482 483 /* structure representing 82xx Address Filtering PRAM 484 */ 485 typedef struct uec_82xx_address_filtering_pram { 486 u32 iaddr_h; /* individual address filter, high */ 487 u32 iaddr_l; /* individual address filter, low */ 488 u32 gaddr_h; /* group address filter, high */ 489 u32 gaddr_l; /* group address filter, low */ 490 uec_82xx_enet_address_t taddr; 491 uec_82xx_enet_address_t paddr[4]; 492 u8 res0[0x40-0x38]; 493 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; 494 495 /* Buffer Descriptor 496 */ 497 typedef struct buffer_descriptor { 498 u16 status; 499 u16 len; 500 u32 data; 501 } __attribute__ ((packed)) qe_bd_t, *p_bd_t; 502 503 #define SIZEOFBD sizeof(qe_bd_t) 504 505 /* Common BD flags 506 */ 507 #define BD_WRAP 0x2000 508 #define BD_INT 0x1000 509 #define BD_LAST 0x0800 510 #define BD_CLEAN 0x3000 511 512 /* TxBD status flags 513 */ 514 #define TxBD_READY 0x8000 515 #define TxBD_PADCRC 0x4000 516 #define TxBD_WRAP BD_WRAP 517 #define TxBD_INT BD_INT 518 #define TxBD_LAST BD_LAST 519 #define TxBD_TXCRC 0x0400 520 #define TxBD_DEF 0x0200 521 #define TxBD_PP 0x0100 522 #define TxBD_LC 0x0080 523 #define TxBD_RL 0x0040 524 #define TxBD_RC 0x003C 525 #define TxBD_UNDERRUN 0x0002 526 #define TxBD_TRUNC 0x0001 527 528 #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) 529 530 /* RxBD status flags 531 */ 532 #define RxBD_EMPTY 0x8000 533 #define RxBD_OWNER 0x4000 534 #define RxBD_WRAP BD_WRAP 535 #define RxBD_INT BD_INT 536 #define RxBD_LAST BD_LAST 537 #define RxBD_FIRST 0x0400 538 #define RxBD_CMR 0x0200 539 #define RxBD_MISS 0x0100 540 #define RxBD_BCAST 0x0080 541 #define RxBD_MCAST 0x0040 542 #define RxBD_LG 0x0020 543 #define RxBD_NO 0x0010 544 #define RxBD_SHORT 0x0008 545 #define RxBD_CRCERR 0x0004 546 #define RxBD_OVERRUN 0x0002 547 #define RxBD_IPCH 0x0001 548 549 #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ 550 RxBD_CRCERR | RxBD_OVERRUN) 551 552 /* BD access macros 553 */ 554 #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) 555 #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) 556 #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) 557 #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) 558 #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) 559 #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) 560 #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) 561 #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) 562 #define BD_ADVANCE(_bd,_status,_base) \ 563 (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) 564 565 /* Rx Prefetched BDs 566 */ 567 typedef struct uec_rx_prefetched_bds { 568 qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ 569 } __attribute__ ((packed)) uec_rx_prefetched_bds_t; 570 571 /* Alignments 572 */ 573 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 574 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 575 #define UEC_THREAD_RX_PRAM_ALIGNMENT 128 576 #define UEC_THREAD_TX_PRAM_ALIGNMENT 64 577 #define UEC_THREAD_DATA_ALIGNMENT 256 578 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 579 #define UEC_SCHEDULER_ALIGNMENT 4 580 #define UEC_TX_STATISTICS_ALIGNMENT 4 581 #define UEC_RX_STATISTICS_ALIGNMENT 4 582 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 583 #define UEC_RX_BD_QUEUES_ALIGNMENT 8 584 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 585 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 586 #define UEC_RX_BD_RING_ALIGNMENT 32 587 #define UEC_TX_BD_RING_ALIGNMENT 32 588 #define UEC_MRBLR_ALIGNMENT 128 589 #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 590 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 591 #define UEC_RX_DATA_BUF_ALIGNMENT 64 592 593 #define UEC_VLAN_PRIORITY_MAX 8 594 #define UEC_IP_PRIORITY_MAX 64 595 #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 596 #define UEC_RX_BD_RING_SIZE_MIN 8 597 #define UEC_TX_BD_RING_SIZE_MIN 2 598 599 /* Ethernet speed 600 */ 601 typedef enum enet_speed { 602 ENET_SPEED_10BT, /* 10 Base T */ 603 ENET_SPEED_100BT, /* 100 Base T */ 604 ENET_SPEED_1000BT /* 1000 Base T */ 605 } enet_speed_e; 606 607 /* Ethernet Address Type. 608 */ 609 typedef enum enet_addr_type { 610 ENET_ADDR_TYPE_INDIVIDUAL, 611 ENET_ADDR_TYPE_GROUP, 612 ENET_ADDR_TYPE_BROADCAST 613 } enet_addr_type_e; 614 615 /* TBI / MII Set Register 616 */ 617 typedef enum enet_tbi_mii_reg { 618 ENET_TBI_MII_CR = 0x00, 619 ENET_TBI_MII_SR = 0x01, 620 ENET_TBI_MII_ANA = 0x04, 621 ENET_TBI_MII_ANLPBPA = 0x05, 622 ENET_TBI_MII_ANEX = 0x06, 623 ENET_TBI_MII_ANNPT = 0x07, 624 ENET_TBI_MII_ANLPANP = 0x08, 625 ENET_TBI_MII_EXST = 0x0F, 626 ENET_TBI_MII_JD = 0x10, 627 ENET_TBI_MII_TBICON = 0x11 628 } enet_tbi_mii_reg_e; 629 630 /* TBI MDIO register bit fields*/ 631 #define TBICON_CLK_SELECT 0x0020 632 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 633 #define TBIANA_SYMMETRIC_PAUSE 0x0080 634 #define TBIANA_HALF_DUPLEX 0x0040 635 #define TBIANA_FULL_DUPLEX 0x0020 636 #define TBICR_PHY_RESET 0x8000 637 #define TBICR_ANEG_ENABLE 0x1000 638 #define TBICR_RESTART_ANEG 0x0200 639 #define TBICR_FULL_DUPLEX 0x0100 640 #define TBICR_SPEED1_SET 0x0040 641 642 #define TBIANA_SETTINGS ( \ 643 TBIANA_ASYMMETRIC_PAUSE \ 644 | TBIANA_SYMMETRIC_PAUSE \ 645 | TBIANA_FULL_DUPLEX \ 646 ) 647 648 #define TBICR_SETTINGS ( \ 649 TBICR_PHY_RESET \ 650 | TBICR_ANEG_ENABLE \ 651 | TBICR_FULL_DUPLEX \ 652 | TBICR_SPEED1_SET \ 653 ) 654 655 /* UEC number of threads 656 */ 657 typedef enum uec_num_of_threads { 658 UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ 659 UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ 660 UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ 661 UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ 662 UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ 663 } uec_num_of_threads_e; 664 665 /* UEC initialization info struct 666 */ 667 #define STD_UEC_INFO(num) \ 668 { \ 669 .uf_info = { \ 670 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ 671 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ 672 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ 673 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ 674 }, \ 675 .num_threads_tx = UEC_NUM_OF_THREADS_1, \ 676 .num_threads_rx = UEC_NUM_OF_THREADS_1, \ 677 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 678 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 679 .tx_bd_ring_len = 16, \ 680 .rx_bd_ring_len = 16, \ 681 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ 682 .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ 683 .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ 684 } 685 686 typedef struct uec_info { 687 ucc_fast_info_t uf_info; 688 uec_num_of_threads_e num_threads_tx; 689 uec_num_of_threads_e num_threads_rx; 690 unsigned int risc_tx; 691 unsigned int risc_rx; 692 u16 rx_bd_ring_len; 693 u16 tx_bd_ring_len; 694 u8 phy_address; 695 phy_interface_t enet_interface_type; 696 int speed; 697 } uec_info_t; 698 699 /* UEC driver initialized info 700 */ 701 #define MAX_RXBUF_LEN 1536 702 #define MAX_FRAME_LEN 1518 703 #define MIN_FRAME_LEN 64 704 #define MAX_DMA1_LEN 1520 705 #define MAX_DMA2_LEN 1520 706 707 /* UEC driver private struct 708 */ 709 typedef struct uec_private { 710 uec_info_t *uec_info; 711 ucc_fast_private_t *uccf; 712 struct eth_device *dev; 713 uec_t *uec_regs; 714 uec_mii_t *uec_mii_regs; 715 /* enet init command parameter */ 716 uec_init_cmd_pram_t *p_init_enet_param; 717 u32 init_enet_param_offset; 718 /* Rx and Tx paramter */ 719 uec_rx_global_pram_t *p_rx_glbl_pram; 720 u32 rx_glbl_pram_offset; 721 uec_tx_global_pram_t *p_tx_glbl_pram; 722 u32 tx_glbl_pram_offset; 723 uec_send_queue_mem_region_t *p_send_q_mem_reg; 724 u32 send_q_mem_reg_offset; 725 uec_thread_data_tx_t *p_thread_data_tx; 726 u32 thread_dat_tx_offset; 727 uec_thread_data_rx_t *p_thread_data_rx; 728 u32 thread_dat_rx_offset; 729 uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; 730 u32 rx_bd_qs_tbl_offset; 731 /* BDs specific */ 732 u8 *p_tx_bd_ring; 733 u32 tx_bd_ring_offset; 734 u8 *p_rx_bd_ring; 735 u32 rx_bd_ring_offset; 736 u8 *p_rx_buf; 737 u32 rx_buf_offset; 738 volatile qe_bd_t *txBd; 739 volatile qe_bd_t *rxBd; 740 /* Status */ 741 int mac_tx_enabled; 742 int mac_rx_enabled; 743 int grace_stopped_tx; 744 int grace_stopped_rx; 745 int the_first_run; 746 /* PHY specific */ 747 struct uec_mii_info *mii_info; 748 int oldspeed; 749 int oldduplex; 750 int oldlink; 751 } uec_private_t; 752 753 int uec_initialize(bd_t *bis, uec_info_t *uec_info); 754 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num); 755 int uec_standard_init(bd_t *bis); 756 #endif /* __UEC_H__ */ 757