1 /* 2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include "common.h" 23 #include "net.h" 24 #include "malloc.h" 25 #include "asm/errno.h" 26 #include "asm/io.h" 27 #include "asm/immap_qe.h" 28 #include "qe.h" 29 #include "uccf.h" 30 #include "uec.h" 31 #include "uec_phy.h" 32 #include "miiphy.h" 33 34 /* Default UTBIPAR SMI address */ 35 #ifndef CONFIG_UTBIPAR_INIT_TBIPA 36 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F 37 #endif 38 39 static uec_info_t uec_info[] = { 40 #ifdef CONFIG_UEC_ETH1 41 STD_UEC_INFO(1), /* UEC1 */ 42 #endif 43 #ifdef CONFIG_UEC_ETH2 44 STD_UEC_INFO(2), /* UEC2 */ 45 #endif 46 #ifdef CONFIG_UEC_ETH3 47 STD_UEC_INFO(3), /* UEC3 */ 48 #endif 49 #ifdef CONFIG_UEC_ETH4 50 STD_UEC_INFO(4), /* UEC4 */ 51 #endif 52 #ifdef CONFIG_UEC_ETH5 53 STD_UEC_INFO(5), /* UEC5 */ 54 #endif 55 #ifdef CONFIG_UEC_ETH6 56 STD_UEC_INFO(6), /* UEC6 */ 57 #endif 58 #ifdef CONFIG_UEC_ETH7 59 STD_UEC_INFO(7), /* UEC7 */ 60 #endif 61 #ifdef CONFIG_UEC_ETH8 62 STD_UEC_INFO(8), /* UEC8 */ 63 #endif 64 }; 65 66 #define MAXCONTROLLERS (8) 67 68 static struct eth_device *devlist[MAXCONTROLLERS]; 69 70 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); 71 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); 72 73 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) 74 { 75 uec_t *uec_regs; 76 u32 maccfg1; 77 78 if (!uec) { 79 printf("%s: uec not initial\n", __FUNCTION__); 80 return -EINVAL; 81 } 82 uec_regs = uec->uec_regs; 83 84 maccfg1 = in_be32(&uec_regs->maccfg1); 85 86 if (mode & COMM_DIR_TX) { 87 maccfg1 |= MACCFG1_ENABLE_TX; 88 out_be32(&uec_regs->maccfg1, maccfg1); 89 uec->mac_tx_enabled = 1; 90 } 91 92 if (mode & COMM_DIR_RX) { 93 maccfg1 |= MACCFG1_ENABLE_RX; 94 out_be32(&uec_regs->maccfg1, maccfg1); 95 uec->mac_rx_enabled = 1; 96 } 97 98 return 0; 99 } 100 101 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode) 102 { 103 uec_t *uec_regs; 104 u32 maccfg1; 105 106 if (!uec) { 107 printf("%s: uec not initial\n", __FUNCTION__); 108 return -EINVAL; 109 } 110 uec_regs = uec->uec_regs; 111 112 maccfg1 = in_be32(&uec_regs->maccfg1); 113 114 if (mode & COMM_DIR_TX) { 115 maccfg1 &= ~MACCFG1_ENABLE_TX; 116 out_be32(&uec_regs->maccfg1, maccfg1); 117 uec->mac_tx_enabled = 0; 118 } 119 120 if (mode & COMM_DIR_RX) { 121 maccfg1 &= ~MACCFG1_ENABLE_RX; 122 out_be32(&uec_regs->maccfg1, maccfg1); 123 uec->mac_rx_enabled = 0; 124 } 125 126 return 0; 127 } 128 129 static int uec_graceful_stop_tx(uec_private_t *uec) 130 { 131 ucc_fast_t *uf_regs; 132 u32 cecr_subblock; 133 u32 ucce; 134 135 if (!uec || !uec->uccf) { 136 printf("%s: No handle passed.\n", __FUNCTION__); 137 return -EINVAL; 138 } 139 140 uf_regs = uec->uccf->uf_regs; 141 142 /* Clear the grace stop event */ 143 out_be32(&uf_regs->ucce, UCCE_GRA); 144 145 /* Issue host command */ 146 cecr_subblock = 147 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 148 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 149 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 150 151 /* Wait for command to complete */ 152 do { 153 ucce = in_be32(&uf_regs->ucce); 154 } while (! (ucce & UCCE_GRA)); 155 156 uec->grace_stopped_tx = 1; 157 158 return 0; 159 } 160 161 static int uec_graceful_stop_rx(uec_private_t *uec) 162 { 163 u32 cecr_subblock; 164 u8 ack; 165 166 if (!uec) { 167 printf("%s: No handle passed.\n", __FUNCTION__); 168 return -EINVAL; 169 } 170 171 if (!uec->p_rx_glbl_pram) { 172 printf("%s: No init rx global parameter\n", __FUNCTION__); 173 return -EINVAL; 174 } 175 176 /* Clear acknowledge bit */ 177 ack = uec->p_rx_glbl_pram->rxgstpack; 178 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 179 uec->p_rx_glbl_pram->rxgstpack = ack; 180 181 /* Keep issuing cmd and checking ack bit until it is asserted */ 182 do { 183 /* Issue host command */ 184 cecr_subblock = 185 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 186 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 187 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 188 ack = uec->p_rx_glbl_pram->rxgstpack; 189 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX )); 190 191 uec->grace_stopped_rx = 1; 192 193 return 0; 194 } 195 196 static int uec_restart_tx(uec_private_t *uec) 197 { 198 u32 cecr_subblock; 199 200 if (!uec || !uec->uec_info) { 201 printf("%s: No handle passed.\n", __FUNCTION__); 202 return -EINVAL; 203 } 204 205 cecr_subblock = 206 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 207 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, 208 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 209 210 uec->grace_stopped_tx = 0; 211 212 return 0; 213 } 214 215 static int uec_restart_rx(uec_private_t *uec) 216 { 217 u32 cecr_subblock; 218 219 if (!uec || !uec->uec_info) { 220 printf("%s: No handle passed.\n", __FUNCTION__); 221 return -EINVAL; 222 } 223 224 cecr_subblock = 225 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); 226 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, 227 (u8)QE_CR_PROTOCOL_ETHERNET, 0); 228 229 uec->grace_stopped_rx = 0; 230 231 return 0; 232 } 233 234 static int uec_open(uec_private_t *uec, comm_dir_e mode) 235 { 236 ucc_fast_private_t *uccf; 237 238 if (!uec || !uec->uccf) { 239 printf("%s: No handle passed.\n", __FUNCTION__); 240 return -EINVAL; 241 } 242 uccf = uec->uccf; 243 244 /* check if the UCC number is in range. */ 245 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { 246 printf("%s: ucc_num out of range.\n", __FUNCTION__); 247 return -EINVAL; 248 } 249 250 /* Enable MAC */ 251 uec_mac_enable(uec, mode); 252 253 /* Enable UCC fast */ 254 ucc_fast_enable(uccf, mode); 255 256 /* RISC microcode start */ 257 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) { 258 uec_restart_tx(uec); 259 } 260 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) { 261 uec_restart_rx(uec); 262 } 263 264 return 0; 265 } 266 267 static int uec_stop(uec_private_t *uec, comm_dir_e mode) 268 { 269 ucc_fast_private_t *uccf; 270 271 if (!uec || !uec->uccf) { 272 printf("%s: No handle passed.\n", __FUNCTION__); 273 return -EINVAL; 274 } 275 uccf = uec->uccf; 276 277 /* check if the UCC number is in range. */ 278 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { 279 printf("%s: ucc_num out of range.\n", __FUNCTION__); 280 return -EINVAL; 281 } 282 /* Stop any transmissions */ 283 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) { 284 uec_graceful_stop_tx(uec); 285 } 286 /* Stop any receptions */ 287 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) { 288 uec_graceful_stop_rx(uec); 289 } 290 291 /* Disable the UCC fast */ 292 ucc_fast_disable(uec->uccf, mode); 293 294 /* Disable the MAC */ 295 uec_mac_disable(uec, mode); 296 297 return 0; 298 } 299 300 static int uec_set_mac_duplex(uec_private_t *uec, int duplex) 301 { 302 uec_t *uec_regs; 303 u32 maccfg2; 304 305 if (!uec) { 306 printf("%s: uec not initial\n", __FUNCTION__); 307 return -EINVAL; 308 } 309 uec_regs = uec->uec_regs; 310 311 if (duplex == DUPLEX_HALF) { 312 maccfg2 = in_be32(&uec_regs->maccfg2); 313 maccfg2 &= ~MACCFG2_FDX; 314 out_be32(&uec_regs->maccfg2, maccfg2); 315 } 316 317 if (duplex == DUPLEX_FULL) { 318 maccfg2 = in_be32(&uec_regs->maccfg2); 319 maccfg2 |= MACCFG2_FDX; 320 out_be32(&uec_regs->maccfg2, maccfg2); 321 } 322 323 return 0; 324 } 325 326 static int uec_set_mac_if_mode(uec_private_t *uec, 327 enet_interface_type_e if_mode, int speed) 328 { 329 enet_interface_type_e enet_if_mode; 330 uec_info_t *uec_info; 331 uec_t *uec_regs; 332 u32 upsmr; 333 u32 maccfg2; 334 335 if (!uec) { 336 printf("%s: uec not initial\n", __FUNCTION__); 337 return -EINVAL; 338 } 339 340 uec_info = uec->uec_info; 341 uec_regs = uec->uec_regs; 342 enet_if_mode = if_mode; 343 344 maccfg2 = in_be32(&uec_regs->maccfg2); 345 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 346 347 upsmr = in_be32(&uec->uccf->uf_regs->upsmr); 348 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); 349 350 switch (speed) { 351 case 10: 352 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 353 switch (enet_if_mode) { 354 case MII: 355 break; 356 case RGMII: 357 upsmr |= (UPSMR_RPM | UPSMR_R10M); 358 break; 359 case RMII: 360 upsmr |= (UPSMR_R10M | UPSMR_RMM); 361 break; 362 default: 363 return -EINVAL; 364 break; 365 } 366 break; 367 case 100: 368 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 369 switch (enet_if_mode) { 370 case MII: 371 break; 372 case RGMII: 373 upsmr |= UPSMR_RPM; 374 break; 375 case RMII: 376 upsmr |= UPSMR_RMM; 377 break; 378 default: 379 return -EINVAL; 380 break; 381 } 382 break; 383 case 1000: 384 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 385 switch (enet_if_mode) { 386 case GMII: 387 break; 388 case TBI: 389 upsmr |= UPSMR_TBIM; 390 break; 391 case RTBI: 392 upsmr |= (UPSMR_RPM | UPSMR_TBIM); 393 break; 394 case RGMII_RXID: 395 case RGMII_ID: 396 case RGMII: 397 upsmr |= UPSMR_RPM; 398 break; 399 case SGMII: 400 upsmr |= UPSMR_SGMM; 401 break; 402 default: 403 return -EINVAL; 404 break; 405 } 406 break; 407 default: 408 return -EINVAL; 409 break; 410 } 411 412 out_be32(&uec_regs->maccfg2, maccfg2); 413 out_be32(&uec->uccf->uf_regs->upsmr, upsmr); 414 415 return 0; 416 } 417 418 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) 419 { 420 uint timeout = 0x1000; 421 u32 miimcfg = 0; 422 423 miimcfg = in_be32(&uec_mii_regs->miimcfg); 424 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; 425 out_be32(&uec_mii_regs->miimcfg, miimcfg); 426 427 /* Wait until the bus is free */ 428 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); 429 if (timeout <= 0) { 430 printf("%s: The MII Bus is stuck!", __FUNCTION__); 431 return -ETIMEDOUT; 432 } 433 434 return 0; 435 } 436 437 static int init_phy(struct eth_device *dev) 438 { 439 uec_private_t *uec; 440 uec_mii_t *umii_regs; 441 struct uec_mii_info *mii_info; 442 struct phy_info *curphy; 443 int err; 444 445 uec = (uec_private_t *)dev->priv; 446 umii_regs = uec->uec_mii_regs; 447 448 uec->oldlink = 0; 449 uec->oldspeed = 0; 450 uec->oldduplex = -1; 451 452 mii_info = malloc(sizeof(*mii_info)); 453 if (!mii_info) { 454 printf("%s: Could not allocate mii_info", dev->name); 455 return -ENOMEM; 456 } 457 memset(mii_info, 0, sizeof(*mii_info)); 458 459 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { 460 mii_info->speed = SPEED_1000; 461 } else { 462 mii_info->speed = SPEED_100; 463 } 464 465 mii_info->duplex = DUPLEX_FULL; 466 mii_info->pause = 0; 467 mii_info->link = 1; 468 469 mii_info->advertising = (ADVERTISED_10baseT_Half | 470 ADVERTISED_10baseT_Full | 471 ADVERTISED_100baseT_Half | 472 ADVERTISED_100baseT_Full | 473 ADVERTISED_1000baseT_Full); 474 mii_info->autoneg = 1; 475 mii_info->mii_id = uec->uec_info->phy_address; 476 mii_info->dev = dev; 477 478 mii_info->mdio_read = &uec_read_phy_reg; 479 mii_info->mdio_write = &uec_write_phy_reg; 480 481 uec->mii_info = mii_info; 482 483 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num); 484 485 if (init_mii_management_configuration(umii_regs)) { 486 printf("%s: The MII Bus is stuck!", dev->name); 487 err = -1; 488 goto bus_fail; 489 } 490 491 /* get info for this PHY */ 492 curphy = uec_get_phy_info(uec->mii_info); 493 if (!curphy) { 494 printf("%s: No PHY found", dev->name); 495 err = -1; 496 goto no_phy; 497 } 498 499 mii_info->phyinfo = curphy; 500 501 /* Run the commands which initialize the PHY */ 502 if (curphy->init) { 503 err = curphy->init(uec->mii_info); 504 if (err) 505 goto phy_init_fail; 506 } 507 508 return 0; 509 510 phy_init_fail: 511 no_phy: 512 bus_fail: 513 free(mii_info); 514 return err; 515 } 516 517 static void adjust_link(struct eth_device *dev) 518 { 519 uec_private_t *uec = (uec_private_t *)dev->priv; 520 uec_t *uec_regs; 521 struct uec_mii_info *mii_info = uec->mii_info; 522 523 extern void change_phy_interface_mode(struct eth_device *dev, 524 enet_interface_type_e mode, int speed); 525 uec_regs = uec->uec_regs; 526 527 if (mii_info->link) { 528 /* Now we make sure that we can be in full duplex mode. 529 * If not, we operate in half-duplex mode. */ 530 if (mii_info->duplex != uec->oldduplex) { 531 if (!(mii_info->duplex)) { 532 uec_set_mac_duplex(uec, DUPLEX_HALF); 533 printf("%s: Half Duplex\n", dev->name); 534 } else { 535 uec_set_mac_duplex(uec, DUPLEX_FULL); 536 printf("%s: Full Duplex\n", dev->name); 537 } 538 uec->oldduplex = mii_info->duplex; 539 } 540 541 if (mii_info->speed != uec->oldspeed) { 542 enet_interface_type_e mode = \ 543 uec->uec_info->enet_interface_type; 544 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { 545 switch (mii_info->speed) { 546 case 1000: 547 break; 548 case 100: 549 printf ("switching to rgmii 100\n"); 550 mode = RGMII; 551 break; 552 case 10: 553 printf ("switching to rgmii 10\n"); 554 mode = RGMII; 555 break; 556 default: 557 printf("%s: Ack,Speed(%d)is illegal\n", 558 dev->name, mii_info->speed); 559 break; 560 } 561 } 562 563 /* change phy */ 564 change_phy_interface_mode(dev, mode, mii_info->speed); 565 /* change the MAC interface mode */ 566 uec_set_mac_if_mode(uec, mode, mii_info->speed); 567 568 printf("%s: Speed %dBT\n", dev->name, mii_info->speed); 569 uec->oldspeed = mii_info->speed; 570 } 571 572 if (!uec->oldlink) { 573 printf("%s: Link is up\n", dev->name); 574 uec->oldlink = 1; 575 } 576 577 } else { /* if (mii_info->link) */ 578 if (uec->oldlink) { 579 printf("%s: Link is down\n", dev->name); 580 uec->oldlink = 0; 581 uec->oldspeed = 0; 582 uec->oldduplex = -1; 583 } 584 } 585 } 586 587 static void phy_change(struct eth_device *dev) 588 { 589 uec_private_t *uec = (uec_private_t *)dev->priv; 590 591 /* Update the link, speed, duplex */ 592 uec->mii_info->phyinfo->read_status(uec->mii_info); 593 594 /* Adjust the interface according to speed */ 595 adjust_link(dev); 596 } 597 598 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 599 && !defined(BITBANGMII) 600 601 /* 602 * Find a device index from the devlist by name 603 * 604 * Returns: 605 * The index where the device is located, -1 on error 606 */ 607 static int uec_miiphy_find_dev_by_name(char *devname) 608 { 609 int i; 610 611 for (i = 0; i < MAXCONTROLLERS; i++) { 612 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) { 613 break; 614 } 615 } 616 617 /* If device cannot be found, returns -1 */ 618 if (i == MAXCONTROLLERS) { 619 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname); 620 i = -1; 621 } 622 623 return i; 624 } 625 626 /* 627 * Read a MII PHY register. 628 * 629 * Returns: 630 * 0 on success 631 */ 632 static int uec_miiphy_read(char *devname, unsigned char addr, 633 unsigned char reg, unsigned short *value) 634 { 635 int devindex = 0; 636 637 if (devname == NULL || value == NULL) { 638 debug("%s: NULL pointer given\n", __FUNCTION__); 639 } else { 640 devindex = uec_miiphy_find_dev_by_name(devname); 641 if (devindex >= 0) { 642 *value = uec_read_phy_reg(devlist[devindex], addr, reg); 643 } 644 } 645 return 0; 646 } 647 648 /* 649 * Write a MII PHY register. 650 * 651 * Returns: 652 * 0 on success 653 */ 654 static int uec_miiphy_write(char *devname, unsigned char addr, 655 unsigned char reg, unsigned short value) 656 { 657 int devindex = 0; 658 659 if (devname == NULL) { 660 debug("%s: NULL pointer given\n", __FUNCTION__); 661 } else { 662 devindex = uec_miiphy_find_dev_by_name(devname); 663 if (devindex >= 0) { 664 uec_write_phy_reg(devlist[devindex], addr, reg, value); 665 } 666 } 667 return 0; 668 } 669 #endif 670 671 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr) 672 { 673 uec_t *uec_regs; 674 u32 mac_addr1; 675 u32 mac_addr2; 676 677 if (!uec) { 678 printf("%s: uec not initial\n", __FUNCTION__); 679 return -EINVAL; 680 } 681 682 uec_regs = uec->uec_regs; 683 684 /* if a station address of 0x12345678ABCD, perform a write to 685 MACSTNADDR1 of 0xCDAB7856, 686 MACSTNADDR2 of 0x34120000 */ 687 688 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ 689 (mac_addr[3] << 8) | (mac_addr[2]); 690 out_be32(&uec_regs->macstnaddr1, mac_addr1); 691 692 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; 693 out_be32(&uec_regs->macstnaddr2, mac_addr2); 694 695 return 0; 696 } 697 698 static int uec_convert_threads_num(uec_num_of_threads_e threads_num, 699 int *threads_num_ret) 700 { 701 int num_threads_numerica; 702 703 switch (threads_num) { 704 case UEC_NUM_OF_THREADS_1: 705 num_threads_numerica = 1; 706 break; 707 case UEC_NUM_OF_THREADS_2: 708 num_threads_numerica = 2; 709 break; 710 case UEC_NUM_OF_THREADS_4: 711 num_threads_numerica = 4; 712 break; 713 case UEC_NUM_OF_THREADS_6: 714 num_threads_numerica = 6; 715 break; 716 case UEC_NUM_OF_THREADS_8: 717 num_threads_numerica = 8; 718 break; 719 default: 720 printf("%s: Bad number of threads value.", 721 __FUNCTION__); 722 return -EINVAL; 723 } 724 725 *threads_num_ret = num_threads_numerica; 726 727 return 0; 728 } 729 730 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx) 731 { 732 uec_info_t *uec_info; 733 u32 end_bd; 734 u8 bmrx = 0; 735 int i; 736 737 uec_info = uec->uec_info; 738 739 /* Alloc global Tx parameter RAM page */ 740 uec->tx_glbl_pram_offset = qe_muram_alloc( 741 sizeof(uec_tx_global_pram_t), 742 UEC_TX_GLOBAL_PRAM_ALIGNMENT); 743 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) 744 qe_muram_addr(uec->tx_glbl_pram_offset); 745 746 /* Zero the global Tx prameter RAM */ 747 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); 748 749 /* Init global Tx parameter RAM */ 750 751 /* TEMODER, RMON statistics disable, one Tx queue */ 752 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); 753 754 /* SQPTR */ 755 uec->send_q_mem_reg_offset = qe_muram_alloc( 756 sizeof(uec_send_queue_qd_t), 757 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 758 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) 759 qe_muram_addr(uec->send_q_mem_reg_offset); 760 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); 761 762 /* Setup the table with TxBDs ring */ 763 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) 764 * SIZEOFBD; 765 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, 766 (u32)(uec->p_tx_bd_ring)); 767 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, 768 end_bd); 769 770 /* Scheduler Base Pointer, we have only one Tx queue, no need it */ 771 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); 772 773 /* TxRMON Base Pointer, TxRMON disable, we don't need it */ 774 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); 775 776 /* TSTATE, global snooping, big endian, the CSB bus selected */ 777 bmrx = BMR_INIT_VALUE; 778 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); 779 780 /* IPH_Offset */ 781 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) { 782 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); 783 } 784 785 /* VTAG table */ 786 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) { 787 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); 788 } 789 790 /* TQPTR */ 791 uec->thread_dat_tx_offset = qe_muram_alloc( 792 num_threads_tx * sizeof(uec_thread_data_tx_t) + 793 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT); 794 795 uec->p_thread_data_tx = (uec_thread_data_tx_t *) 796 qe_muram_addr(uec->thread_dat_tx_offset); 797 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); 798 } 799 800 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx) 801 { 802 u8 bmrx = 0; 803 int i; 804 uec_82xx_address_filtering_pram_t *p_af_pram; 805 806 /* Allocate global Rx parameter RAM page */ 807 uec->rx_glbl_pram_offset = qe_muram_alloc( 808 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT); 809 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) 810 qe_muram_addr(uec->rx_glbl_pram_offset); 811 812 /* Zero Global Rx parameter RAM */ 813 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); 814 815 /* Init global Rx parameter RAM */ 816 /* REMODER, Extended feature mode disable, VLAN disable, 817 LossLess flow control disable, Receive firmware statisic disable, 818 Extended address parsing mode disable, One Rx queues, 819 Dynamic maximum/minimum frame length disable, IP checksum check 820 disable, IP address alignment disable 821 */ 822 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); 823 824 /* RQPTR */ 825 uec->thread_dat_rx_offset = qe_muram_alloc( 826 num_threads_rx * sizeof(uec_thread_data_rx_t), 827 UEC_THREAD_DATA_ALIGNMENT); 828 uec->p_thread_data_rx = (uec_thread_data_rx_t *) 829 qe_muram_addr(uec->thread_dat_rx_offset); 830 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); 831 832 /* Type_or_Len */ 833 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); 834 835 /* RxRMON base pointer, we don't need it */ 836 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); 837 838 /* IntCoalescingPTR, we don't need it, no interrupt */ 839 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); 840 841 /* RSTATE, global snooping, big endian, the CSB bus selected */ 842 bmrx = BMR_INIT_VALUE; 843 out_8(&uec->p_rx_glbl_pram->rstate, bmrx); 844 845 /* MRBLR */ 846 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); 847 848 /* RBDQPTR */ 849 uec->rx_bd_qs_tbl_offset = qe_muram_alloc( 850 sizeof(uec_rx_bd_queues_entry_t) + \ 851 sizeof(uec_rx_prefetched_bds_t), 852 UEC_RX_BD_QUEUES_ALIGNMENT); 853 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) 854 qe_muram_addr(uec->rx_bd_qs_tbl_offset); 855 856 /* Zero it */ 857 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ 858 sizeof(uec_rx_prefetched_bds_t)); 859 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); 860 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, 861 (u32)uec->p_rx_bd_ring); 862 863 /* MFLR */ 864 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); 865 /* MINFLR */ 866 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); 867 /* MAXD1 */ 868 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); 869 /* MAXD2 */ 870 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); 871 /* ECAM_PTR */ 872 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); 873 /* L2QT */ 874 out_be32(&uec->p_rx_glbl_pram->l2qt, 0); 875 /* L3QT */ 876 for (i = 0; i < 8; i++) { 877 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); 878 } 879 880 /* VLAN_TYPE */ 881 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); 882 /* TCI */ 883 out_be16(&uec->p_rx_glbl_pram->vlantci, 0); 884 885 /* Clear PQ2 style address filtering hash table */ 886 p_af_pram = (uec_82xx_address_filtering_pram_t *) \ 887 uec->p_rx_glbl_pram->addressfiltering; 888 889 p_af_pram->iaddr_h = 0; 890 p_af_pram->iaddr_l = 0; 891 p_af_pram->gaddr_h = 0; 892 p_af_pram->gaddr_l = 0; 893 } 894 895 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, 896 int thread_tx, int thread_rx) 897 { 898 uec_init_cmd_pram_t *p_init_enet_param; 899 u32 init_enet_param_offset; 900 uec_info_t *uec_info; 901 int i; 902 int snum; 903 u32 init_enet_offset; 904 u32 entry_val; 905 u32 command; 906 u32 cecr_subblock; 907 908 uec_info = uec->uec_info; 909 910 /* Allocate init enet command parameter */ 911 uec->init_enet_param_offset = qe_muram_alloc( 912 sizeof(uec_init_cmd_pram_t), 4); 913 init_enet_param_offset = uec->init_enet_param_offset; 914 uec->p_init_enet_param = (uec_init_cmd_pram_t *) 915 qe_muram_addr(uec->init_enet_param_offset); 916 917 /* Zero init enet command struct */ 918 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); 919 920 /* Init the command struct */ 921 p_init_enet_param = uec->p_init_enet_param; 922 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; 923 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; 924 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; 925 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; 926 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; 927 p_init_enet_param->largestexternallookupkeysize = 0; 928 929 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) 930 << ENET_INIT_PARAM_RGF_SHIFT; 931 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) 932 << ENET_INIT_PARAM_TGF_SHIFT; 933 934 /* Init Rx global parameter pointer */ 935 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | 936 (u32)uec_info->risc_rx; 937 938 /* Init Rx threads */ 939 for (i = 0; i < (thread_rx + 1); i++) { 940 if ((snum = qe_get_snum()) < 0) { 941 printf("%s can not get snum\n", __FUNCTION__); 942 return -ENOMEM; 943 } 944 945 if (i==0) { 946 init_enet_offset = 0; 947 } else { 948 init_enet_offset = qe_muram_alloc( 949 sizeof(uec_thread_rx_pram_t), 950 UEC_THREAD_RX_PRAM_ALIGNMENT); 951 } 952 953 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | 954 init_enet_offset | (u32)uec_info->risc_rx; 955 p_init_enet_param->rxthread[i] = entry_val; 956 } 957 958 /* Init Tx global parameter pointer */ 959 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | 960 (u32)uec_info->risc_tx; 961 962 /* Init Tx threads */ 963 for (i = 0; i < thread_tx; i++) { 964 if ((snum = qe_get_snum()) < 0) { 965 printf("%s can not get snum\n", __FUNCTION__); 966 return -ENOMEM; 967 } 968 969 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t), 970 UEC_THREAD_TX_PRAM_ALIGNMENT); 971 972 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | 973 init_enet_offset | (u32)uec_info->risc_tx; 974 p_init_enet_param->txthread[i] = entry_val; 975 } 976 977 __asm__ __volatile__("sync"); 978 979 /* Issue QE command */ 980 command = QE_INIT_TX_RX; 981 cecr_subblock = ucc_fast_get_qe_cr_subblock( 982 uec->uec_info->uf_info.ucc_num); 983 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET, 984 init_enet_param_offset); 985 986 return 0; 987 } 988 989 static int uec_startup(uec_private_t *uec) 990 { 991 uec_info_t *uec_info; 992 ucc_fast_info_t *uf_info; 993 ucc_fast_private_t *uccf; 994 ucc_fast_t *uf_regs; 995 uec_t *uec_regs; 996 int num_threads_tx; 997 int num_threads_rx; 998 u32 utbipar; 999 u32 length; 1000 u32 align; 1001 qe_bd_t *bd; 1002 u8 *buf; 1003 int i; 1004 1005 if (!uec || !uec->uec_info) { 1006 printf("%s: uec or uec_info not initial\n", __FUNCTION__); 1007 return -EINVAL; 1008 } 1009 1010 uec_info = uec->uec_info; 1011 uf_info = &(uec_info->uf_info); 1012 1013 /* Check if Rx BD ring len is illegal */ 1014 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ 1015 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { 1016 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", 1017 __FUNCTION__); 1018 return -EINVAL; 1019 } 1020 1021 /* Check if Tx BD ring len is illegal */ 1022 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { 1023 printf("%s: Tx BD ring length must not be smaller than 2.\n", 1024 __FUNCTION__); 1025 return -EINVAL; 1026 } 1027 1028 /* Check if MRBLR is illegal */ 1029 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) { 1030 printf("%s: max rx buffer length must be mutliple of 128.\n", 1031 __FUNCTION__); 1032 return -EINVAL; 1033 } 1034 1035 /* Both Rx and Tx are stopped */ 1036 uec->grace_stopped_rx = 1; 1037 uec->grace_stopped_tx = 1; 1038 1039 /* Init UCC fast */ 1040 if (ucc_fast_init(uf_info, &uccf)) { 1041 printf("%s: failed to init ucc fast\n", __FUNCTION__); 1042 return -ENOMEM; 1043 } 1044 1045 /* Save uccf */ 1046 uec->uccf = uccf; 1047 1048 /* Convert the Tx threads number */ 1049 if (uec_convert_threads_num(uec_info->num_threads_tx, 1050 &num_threads_tx)) { 1051 return -EINVAL; 1052 } 1053 1054 /* Convert the Rx threads number */ 1055 if (uec_convert_threads_num(uec_info->num_threads_rx, 1056 &num_threads_rx)) { 1057 return -EINVAL; 1058 } 1059 1060 uf_regs = uccf->uf_regs; 1061 1062 /* UEC register is following UCC fast registers */ 1063 uec_regs = (uec_t *)(&uf_regs->ucc_eth); 1064 1065 /* Save the UEC register pointer to UEC private struct */ 1066 uec->uec_regs = uec_regs; 1067 1068 /* Init UPSMR, enable hardware statistics (UCC) */ 1069 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); 1070 1071 /* Init MACCFG1, flow control disable, disable Tx and Rx */ 1072 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); 1073 1074 /* Init MACCFG2, length check, MAC PAD and CRC enable */ 1075 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); 1076 1077 /* Setup MAC interface mode */ 1078 uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed); 1079 1080 /* Setup MII management base */ 1081 #ifndef CONFIG_eTSEC_MDIO_BUS 1082 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); 1083 #else 1084 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; 1085 #endif 1086 1087 /* Setup MII master clock source */ 1088 qe_set_mii_clk_src(uec_info->uf_info.ucc_num); 1089 1090 /* Setup UTBIPAR */ 1091 utbipar = in_be32(&uec_regs->utbipar); 1092 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; 1093 1094 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. 1095 * This frees up the remaining SMI addresses for use. 1096 */ 1097 utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT; 1098 out_be32(&uec_regs->utbipar, utbipar); 1099 1100 /* Configure the TBI for SGMII operation */ 1101 if ((uec->uec_info->enet_interface_type == SGMII) && 1102 (uec->uec_info->speed == 1000)) { 1103 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1104 ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1105 1106 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1107 ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1108 1109 uec_write_phy_reg(uec->dev, uec_regs->utbipar, 1110 ENET_TBI_MII_CR, TBICR_SETTINGS); 1111 } 1112 1113 /* Allocate Tx BDs */ 1114 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / 1115 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * 1116 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 1117 if ((uec_info->tx_bd_ring_len * SIZEOFBD) % 1118 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) { 1119 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 1120 } 1121 1122 align = UEC_TX_BD_RING_ALIGNMENT; 1123 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); 1124 if (uec->tx_bd_ring_offset != 0) { 1125 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) 1126 & ~(align - 1)); 1127 } 1128 1129 /* Zero all of Tx BDs */ 1130 memset((void *)(uec->tx_bd_ring_offset), 0, length + align); 1131 1132 /* Allocate Rx BDs */ 1133 length = uec_info->rx_bd_ring_len * SIZEOFBD; 1134 align = UEC_RX_BD_RING_ALIGNMENT; 1135 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); 1136 if (uec->rx_bd_ring_offset != 0) { 1137 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) 1138 & ~(align - 1)); 1139 } 1140 1141 /* Zero all of Rx BDs */ 1142 memset((void *)(uec->rx_bd_ring_offset), 0, length + align); 1143 1144 /* Allocate Rx buffer */ 1145 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; 1146 align = UEC_RX_DATA_BUF_ALIGNMENT; 1147 uec->rx_buf_offset = (u32)malloc(length + align); 1148 if (uec->rx_buf_offset != 0) { 1149 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) 1150 & ~(align - 1)); 1151 } 1152 1153 /* Zero all of the Rx buffer */ 1154 memset((void *)(uec->rx_buf_offset), 0, length + align); 1155 1156 /* Init TxBD ring */ 1157 bd = (qe_bd_t *)uec->p_tx_bd_ring; 1158 uec->txBd = bd; 1159 1160 for (i = 0; i < uec_info->tx_bd_ring_len; i++) { 1161 BD_DATA_CLEAR(bd); 1162 BD_STATUS_SET(bd, 0); 1163 BD_LENGTH_SET(bd, 0); 1164 bd ++; 1165 } 1166 BD_STATUS_SET((--bd), TxBD_WRAP); 1167 1168 /* Init RxBD ring */ 1169 bd = (qe_bd_t *)uec->p_rx_bd_ring; 1170 uec->rxBd = bd; 1171 buf = uec->p_rx_buf; 1172 for (i = 0; i < uec_info->rx_bd_ring_len; i++) { 1173 BD_DATA_SET(bd, buf); 1174 BD_LENGTH_SET(bd, 0); 1175 BD_STATUS_SET(bd, RxBD_EMPTY); 1176 buf += MAX_RXBUF_LEN; 1177 bd ++; 1178 } 1179 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); 1180 1181 /* Init global Tx parameter RAM */ 1182 uec_init_tx_parameter(uec, num_threads_tx); 1183 1184 /* Init global Rx parameter RAM */ 1185 uec_init_rx_parameter(uec, num_threads_rx); 1186 1187 /* Init ethernet Tx and Rx parameter command */ 1188 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, 1189 num_threads_rx)) { 1190 printf("%s issue init enet cmd failed\n", __FUNCTION__); 1191 return -ENOMEM; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int uec_init(struct eth_device* dev, bd_t *bd) 1198 { 1199 uec_private_t *uec; 1200 int err, i; 1201 struct phy_info *curphy; 1202 1203 uec = (uec_private_t *)dev->priv; 1204 1205 if (uec->the_first_run == 0) { 1206 err = init_phy(dev); 1207 if (err) { 1208 printf("%s: Cannot initialize PHY, aborting.\n", 1209 dev->name); 1210 return err; 1211 } 1212 1213 curphy = uec->mii_info->phyinfo; 1214 1215 if (curphy->config_aneg) { 1216 err = curphy->config_aneg(uec->mii_info); 1217 if (err) { 1218 printf("%s: Can't negotiate PHY\n", dev->name); 1219 return err; 1220 } 1221 } 1222 1223 /* Give PHYs up to 5 sec to report a link */ 1224 i = 50; 1225 do { 1226 err = curphy->read_status(uec->mii_info); 1227 udelay(100000); 1228 } while (((i-- > 0) && !uec->mii_info->link) || err); 1229 1230 if (err || i <= 0) 1231 printf("warning: %s: timeout on PHY link\n", dev->name); 1232 1233 adjust_link(dev); 1234 uec->the_first_run = 1; 1235 } 1236 1237 /* Set up the MAC address */ 1238 if (dev->enetaddr[0] & 0x01) { 1239 printf("%s: MacAddress is multcast address\n", 1240 __FUNCTION__); 1241 return -1; 1242 } 1243 uec_set_mac_address(uec, dev->enetaddr); 1244 1245 1246 err = uec_open(uec, COMM_DIR_RX_AND_TX); 1247 if (err) { 1248 printf("%s: cannot enable UEC device\n", dev->name); 1249 return -1; 1250 } 1251 1252 phy_change(dev); 1253 1254 return (uec->mii_info->link ? 0 : -1); 1255 } 1256 1257 static void uec_halt(struct eth_device* dev) 1258 { 1259 uec_private_t *uec = (uec_private_t *)dev->priv; 1260 uec_stop(uec, COMM_DIR_RX_AND_TX); 1261 } 1262 1263 static int uec_send(struct eth_device* dev, volatile void *buf, int len) 1264 { 1265 uec_private_t *uec; 1266 ucc_fast_private_t *uccf; 1267 volatile qe_bd_t *bd; 1268 u16 status; 1269 int i; 1270 int result = 0; 1271 1272 uec = (uec_private_t *)dev->priv; 1273 uccf = uec->uccf; 1274 bd = uec->txBd; 1275 1276 /* Find an empty TxBD */ 1277 for (i = 0; bd->status & TxBD_READY; i++) { 1278 if (i > 0x100000) { 1279 printf("%s: tx buffer not ready\n", dev->name); 1280 return result; 1281 } 1282 } 1283 1284 /* Init TxBD */ 1285 BD_DATA_SET(bd, buf); 1286 BD_LENGTH_SET(bd, len); 1287 status = bd->status; 1288 status &= BD_WRAP; 1289 status |= (TxBD_READY | TxBD_LAST); 1290 BD_STATUS_SET(bd, status); 1291 1292 /* Tell UCC to transmit the buffer */ 1293 ucc_fast_transmit_on_demand(uccf); 1294 1295 /* Wait for buffer to be transmitted */ 1296 for (i = 0; bd->status & TxBD_READY; i++) { 1297 if (i > 0x100000) { 1298 printf("%s: tx error\n", dev->name); 1299 return result; 1300 } 1301 } 1302 1303 /* Ok, the buffer be transimitted */ 1304 BD_ADVANCE(bd, status, uec->p_tx_bd_ring); 1305 uec->txBd = bd; 1306 result = 1; 1307 1308 return result; 1309 } 1310 1311 static int uec_recv(struct eth_device* dev) 1312 { 1313 uec_private_t *uec = dev->priv; 1314 volatile qe_bd_t *bd; 1315 u16 status; 1316 u16 len; 1317 u8 *data; 1318 1319 bd = uec->rxBd; 1320 status = bd->status; 1321 1322 while (!(status & RxBD_EMPTY)) { 1323 if (!(status & RxBD_ERROR)) { 1324 data = BD_DATA(bd); 1325 len = BD_LENGTH(bd); 1326 NetReceive(data, len); 1327 } else { 1328 printf("%s: Rx error\n", dev->name); 1329 } 1330 status &= BD_CLEAN; 1331 BD_LENGTH_SET(bd, 0); 1332 BD_STATUS_SET(bd, status | RxBD_EMPTY); 1333 BD_ADVANCE(bd, status, uec->p_rx_bd_ring); 1334 status = bd->status; 1335 } 1336 uec->rxBd = bd; 1337 1338 return 1; 1339 } 1340 1341 int uec_initialize(bd_t *bis, uec_info_t *uec_info) 1342 { 1343 struct eth_device *dev; 1344 int i; 1345 uec_private_t *uec; 1346 int err; 1347 1348 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 1349 if (!dev) 1350 return 0; 1351 memset(dev, 0, sizeof(struct eth_device)); 1352 1353 /* Allocate the UEC private struct */ 1354 uec = (uec_private_t *)malloc(sizeof(uec_private_t)); 1355 if (!uec) { 1356 return -ENOMEM; 1357 } 1358 memset(uec, 0, sizeof(uec_private_t)); 1359 1360 /* Adjust uec_info */ 1361 #if (MAX_QE_RISC == 4) 1362 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; 1363 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; 1364 #endif 1365 1366 devlist[uec_info->uf_info.ucc_num] = dev; 1367 1368 uec->uec_info = uec_info; 1369 uec->dev = dev; 1370 1371 sprintf(dev->name, "FSL UEC%d", uec_info->uf_info.ucc_num); 1372 dev->iobase = 0; 1373 dev->priv = (void *)uec; 1374 dev->init = uec_init; 1375 dev->halt = uec_halt; 1376 dev->send = uec_send; 1377 dev->recv = uec_recv; 1378 1379 /* Clear the ethnet address */ 1380 for (i = 0; i < 6; i++) 1381 dev->enetaddr[i] = 0; 1382 1383 eth_register(dev); 1384 1385 err = uec_startup(uec); 1386 if (err) { 1387 printf("%s: Cannot configure net device, aborting.",dev->name); 1388 return err; 1389 } 1390 1391 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1392 && !defined(BITBANGMII) 1393 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); 1394 #endif 1395 1396 return 1; 1397 } 1398 1399 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num) 1400 { 1401 int i; 1402 1403 for (i = 0; i < num; i++) 1404 uec_initialize(bis, &uecs[i]); 1405 1406 return 0; 1407 } 1408 1409 int uec_standard_init(bd_t *bis) 1410 { 1411 return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info)); 1412 } 1413