xref: /openbmc/u-boot/drivers/qe/uccf.h (revision 3bddafaa)
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  * based on source code of Shlomi Gridish
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __UCCF_H__
11 #define __UCCF_H__
12 
13 #include "common.h"
14 #include "qe.h"
15 #include "asm/immap_qe.h"
16 
17 /* Fast or Giga ethernet
18 */
19 typedef enum enet_type {
20 	FAST_ETH,
21 	GIGA_ETH,
22 } enet_type_e;
23 
24 /* General UCC Extended Mode Register
25 */
26 #define UCC_GUEMR_MODE_MASK_RX		0x02
27 #define UCC_GUEMR_MODE_MASK_TX		0x01
28 #define UCC_GUEMR_MODE_FAST_RX		0x02
29 #define UCC_GUEMR_MODE_FAST_TX		0x01
30 #define UCC_GUEMR_MODE_SLOW_RX		0x00
31 #define UCC_GUEMR_MODE_SLOW_TX		0x00
32 #define UCC_GUEMR_SET_RESERVED3		0x10 /* Bit 3 must be set 1 */
33 
34 /* General UCC FAST Mode Register
35 */
36 #define UCC_FAST_GUMR_TCI		0x20000000
37 #define UCC_FAST_GUMR_TRX		0x10000000
38 #define UCC_FAST_GUMR_TTX		0x08000000
39 #define UCC_FAST_GUMR_CDP		0x04000000
40 #define UCC_FAST_GUMR_CTSP		0x02000000
41 #define UCC_FAST_GUMR_CDS		0x01000000
42 #define UCC_FAST_GUMR_CTSS		0x00800000
43 #define UCC_FAST_GUMR_TXSY		0x00020000
44 #define UCC_FAST_GUMR_RSYN		0x00010000
45 #define UCC_FAST_GUMR_RTSM		0x00002000
46 #define UCC_FAST_GUMR_REVD		0x00000400
47 #define UCC_FAST_GUMR_ENR		0x00000020
48 #define UCC_FAST_GUMR_ENT		0x00000010
49 
50 /* GUMR [MODE] bit maps
51 */
52 #define UCC_FAST_GUMR_HDLC		0x00000000
53 #define UCC_FAST_GUMR_QMC		0x00000002
54 #define UCC_FAST_GUMR_UART		0x00000004
55 #define UCC_FAST_GUMR_BISYNC		0x00000008
56 #define UCC_FAST_GUMR_ATM		0x0000000a
57 #define UCC_FAST_GUMR_ETH		0x0000000c
58 
59 /* Transmit On Demand (UTORD)
60 */
61 #define UCC_SLOW_TOD			0x8000
62 #define UCC_FAST_TOD			0x8000
63 
64 /* Fast Ethernet (10/100 Mbps)
65 */
66 #define UCC_GETH_URFS_INIT		512        /* Rx virtual FIFO size */
67 #define UCC_GETH_URFET_INIT		256        /* 1/2 urfs */
68 #define UCC_GETH_URFSET_INIT		384        /* 3/4 urfs */
69 #define UCC_GETH_UTFS_INIT		512        /* Tx virtual FIFO size */
70 #define UCC_GETH_UTFET_INIT		256        /* 1/2 utfs */
71 #define UCC_GETH_UTFTT_INIT		128
72 
73 /* Gigabit Ethernet (1000 Mbps)
74 */
75 #define UCC_GETH_URFS_GIGA_INIT		4096/*2048*/    /* Rx virtual FIFO size */
76 #define UCC_GETH_URFET_GIGA_INIT	2048/*1024*/    /* 1/2 urfs */
77 #define UCC_GETH_URFSET_GIGA_INIT	3072/*1536*/    /* 3/4 urfs */
78 #define UCC_GETH_UTFS_GIGA_INIT		8192/*2048*/    /* Tx virtual FIFO size */
79 #define UCC_GETH_UTFET_GIGA_INIT	4096/*1024*/    /* 1/2 utfs */
80 #define UCC_GETH_UTFTT_GIGA_INIT	0x400/*0x40*/   /*  */
81 
82 /* UCC fast alignment
83 */
84 #define UCC_FAST_RX_ALIGN			4
85 #define UCC_FAST_MRBLR_ALIGNMENT		4
86 #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
87 
88 /* Sizes
89 */
90 #define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD	8
91 
92 /* UCC fast structure.
93 */
94 typedef struct ucc_fast_info {
95 	int		ucc_num;
96 	qe_clock_e	rx_clock;
97 	qe_clock_e	tx_clock;
98 	enet_type_e	eth_type;
99 } ucc_fast_info_t;
100 
101 typedef struct ucc_fast_private {
102 	ucc_fast_info_t	*uf_info;
103 	ucc_fast_t	*uf_regs; /* a pointer to memory map of UCC regs */
104 	u32		*p_ucce; /* a pointer to the event register */
105 	u32		*p_uccm; /* a pointer to the mask register */
106 	int		enabled_tx; /* whether UCC is enabled for Tx (ENT) */
107 	int		enabled_rx; /* whether UCC is enabled for Rx (ENR) */
108 	u32		ucc_fast_tx_virtual_fifo_base_offset;
109 	u32		ucc_fast_rx_virtual_fifo_base_offset;
110 } ucc_fast_private_t;
111 
112 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf);
113 u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
114 void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode);
115 void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode);
116 int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret);
117 
118 #endif /* __UCCF_H__ */
119