1 /* 2 * Copyright (c) 2016 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <div64.h> 11 #include <dm.h> 12 #include <pwm.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/pwm.h> 17 #include <power/regulator.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct rk_pwm_priv { 22 struct rk3288_pwm *regs; 23 ulong freq; 24 uint enable_conf; 25 }; 26 27 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) 28 { 29 struct rk_pwm_priv *priv = dev_get_priv(dev); 30 31 debug("%s: polarity=%u\n", __func__, polarity); 32 priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); 33 if (polarity) 34 priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; 35 else 36 priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; 37 38 return 0; 39 } 40 41 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, 42 uint duty_ns) 43 { 44 struct rk_pwm_priv *priv = dev_get_priv(dev); 45 struct rk3288_pwm *regs = priv->regs; 46 unsigned long period, duty; 47 48 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns); 49 writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | 50 PWM_CONTINUOUS | priv->enable_conf | 51 RK_PWM_DISABLE, 52 ®s->ctrl); 53 54 period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000); 55 duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000); 56 57 writel(period, ®s->period_hpr); 58 writel(duty, ®s->duty_lpr); 59 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); 60 61 return 0; 62 } 63 64 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) 65 { 66 struct rk_pwm_priv *priv = dev_get_priv(dev); 67 struct rk3288_pwm *regs = priv->regs; 68 69 debug("%s: Enable '%s'\n", __func__, dev->name); 70 clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0); 71 72 return 0; 73 } 74 75 static int rk_pwm_ofdata_to_platdata(struct udevice *dev) 76 { 77 struct rk_pwm_priv *priv = dev_get_priv(dev); 78 79 priv->regs = (struct rk3288_pwm *)dev_read_addr(dev); 80 81 return 0; 82 } 83 84 static int rk_pwm_probe(struct udevice *dev) 85 { 86 struct rk_pwm_priv *priv = dev_get_priv(dev); 87 struct clk clk; 88 int ret = 0; 89 90 ret = clk_get_by_index(dev, 0, &clk); 91 if (ret < 0) { 92 debug("%s get clock fail!\n", __func__); 93 return -EINVAL; 94 } 95 priv->freq = clk_get_rate(&clk); 96 priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; 97 98 return 0; 99 } 100 101 static const struct pwm_ops rk_pwm_ops = { 102 .set_invert = rk_pwm_set_invert, 103 .set_config = rk_pwm_set_config, 104 .set_enable = rk_pwm_set_enable, 105 }; 106 107 static const struct udevice_id rk_pwm_ids[] = { 108 { .compatible = "rockchip,rk3288-pwm" }, 109 { } 110 }; 111 112 U_BOOT_DRIVER(rk_pwm) = { 113 .name = "rk_pwm", 114 .id = UCLASS_PWM, 115 .of_match = rk_pwm_ids, 116 .ops = &rk_pwm_ops, 117 .ofdata_to_platdata = rk_pwm_ofdata_to_platdata, 118 .probe = rk_pwm_probe, 119 .priv_auto_alloc_size = sizeof(struct rk_pwm_priv), 120 }; 121