1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <power/pmic.h> 11 #include <power/regulator.h> 12 #include <power/stpmu1.h> 13 14 struct stpmu1_range { 15 int min_uv; 16 int min_sel; 17 int max_sel; 18 int step; 19 }; 20 21 struct stpmu1_output_range { 22 const struct stpmu1_range *ranges; 23 int nbranges; 24 }; 25 26 #define STPMU1_MODE(_id, _val, _name) { \ 27 .id = _id, \ 28 .register_value = _val, \ 29 .name = _name, \ 30 } 31 32 #define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \ 33 .min_uv = _min_uv, \ 34 .min_sel = _min_sel, \ 35 .max_sel = _max_sel, \ 36 .step = _step, \ 37 } 38 39 #define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \ 40 .ranges = _ranges, \ 41 .nbranges = _nbranges, \ 42 } 43 44 static int stpmu1_output_find_uv(int sel, 45 const struct stpmu1_output_range *output_range) 46 { 47 const struct stpmu1_range *range; 48 int i; 49 50 for (i = 0, range = output_range->ranges; 51 i < output_range->nbranges; i++, range++) { 52 if (sel >= range->min_sel && sel <= range->max_sel) 53 return range->min_uv + 54 (sel - range->min_sel) * range->step; 55 } 56 57 return -EINVAL; 58 } 59 60 static int stpmu1_output_find_sel(int uv, 61 const struct stpmu1_output_range *output_range) 62 { 63 const struct stpmu1_range *range; 64 int i; 65 66 for (i = 0, range = output_range->ranges; 67 i < output_range->nbranges; i++, range++) { 68 if (uv == range->min_uv && !range->step) 69 return range->min_sel; 70 71 if (uv >= range->min_uv && 72 uv <= range->min_uv + 73 (range->max_sel - range->min_sel) * range->step) 74 return range->min_sel + 75 (uv - range->min_uv) / range->step; 76 } 77 78 return -EINVAL; 79 } 80 81 /* 82 * BUCK regulators 83 */ 84 85 static const struct stpmu1_range buck1_ranges[] = { 86 STPMU1_RANGE(600000, 0, 30, 25000), 87 STPMU1_RANGE(1350000, 31, 63, 0), 88 }; 89 90 static const struct stpmu1_range buck2_ranges[] = { 91 STPMU1_RANGE(1000000, 0, 17, 0), 92 STPMU1_RANGE(1050000, 18, 19, 0), 93 STPMU1_RANGE(1100000, 20, 21, 0), 94 STPMU1_RANGE(1150000, 22, 23, 0), 95 STPMU1_RANGE(1200000, 24, 25, 0), 96 STPMU1_RANGE(1250000, 26, 27, 0), 97 STPMU1_RANGE(1300000, 28, 29, 0), 98 STPMU1_RANGE(1350000, 30, 31, 0), 99 STPMU1_RANGE(1400000, 32, 33, 0), 100 STPMU1_RANGE(1450000, 34, 35, 0), 101 STPMU1_RANGE(1500000, 36, 63, 0), 102 }; 103 104 static const struct stpmu1_range buck3_ranges[] = { 105 STPMU1_RANGE(1000000, 0, 19, 0), 106 STPMU1_RANGE(1100000, 20, 23, 0), 107 STPMU1_RANGE(1200000, 24, 27, 0), 108 STPMU1_RANGE(1300000, 28, 31, 0), 109 STPMU1_RANGE(1400000, 32, 35, 0), 110 STPMU1_RANGE(1500000, 36, 55, 100000), 111 STPMU1_RANGE(3400000, 56, 63, 0), 112 }; 113 114 static const struct stpmu1_range buck4_ranges[] = { 115 STPMU1_RANGE(600000, 0, 27, 25000), 116 STPMU1_RANGE(1300000, 28, 29, 0), 117 STPMU1_RANGE(1350000, 30, 31, 0), 118 STPMU1_RANGE(1400000, 32, 33, 0), 119 STPMU1_RANGE(1450000, 34, 35, 0), 120 STPMU1_RANGE(1500000, 36, 60, 100000), 121 STPMU1_RANGE(3900000, 61, 63, 0), 122 }; 123 124 /* BUCK: 1,2,3,4 - voltage ranges */ 125 static const struct stpmu1_output_range buck_voltage_range[] = { 126 STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)), 127 STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)), 128 STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)), 129 STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)), 130 }; 131 132 /* BUCK modes */ 133 static const struct dm_regulator_mode buck_modes[] = { 134 STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"), 135 STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"), 136 }; 137 138 static int stpmu1_buck_get_uv(struct udevice *dev, int buck) 139 { 140 int sel; 141 142 sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck)); 143 if (sel < 0) 144 return sel; 145 146 sel &= STPMU1_BUCK_OUTPUT_MASK; 147 sel >>= STPMU1_BUCK_OUTPUT_SHIFT; 148 149 return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]); 150 } 151 152 static int stpmu1_buck_get_value(struct udevice *dev) 153 { 154 return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1); 155 } 156 157 static int stpmu1_buck_set_value(struct udevice *dev, int uv) 158 { 159 int sel, buck = dev->driver_data - 1; 160 161 sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]); 162 if (sel < 0) 163 return sel; 164 165 return pmic_clrsetbits(dev->parent, 166 STPMU1_BUCKX_CTRL_REG(buck), 167 STPMU1_BUCK_OUTPUT_MASK, 168 sel << STPMU1_BUCK_OUTPUT_SHIFT); 169 } 170 171 static int stpmu1_buck_get_enable(struct udevice *dev) 172 { 173 int ret; 174 175 ret = pmic_reg_read(dev->parent, 176 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1)); 177 if (ret < 0) 178 return false; 179 180 return ret & STPMU1_BUCK_EN ? true : false; 181 } 182 183 static int stpmu1_buck_set_enable(struct udevice *dev, bool enable) 184 { 185 struct dm_regulator_uclass_platdata *uc_pdata; 186 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : 187 STPMU1_DEFAULT_STOP_DELAY_MS; 188 int ret, uv; 189 190 /* if regulator is already in the wanted state, nothing to do */ 191 if (stpmu1_buck_get_enable(dev) == enable) 192 return 0; 193 194 if (enable) { 195 uc_pdata = dev_get_uclass_platdata(dev); 196 uv = stpmu1_buck_get_value(dev); 197 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV)) 198 stpmu1_buck_set_value(dev, uc_pdata->min_uV); 199 } 200 201 ret = pmic_clrsetbits(dev->parent, 202 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1), 203 STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0); 204 mdelay(delay); 205 206 return ret; 207 } 208 209 static int stpmu1_buck_get_mode(struct udevice *dev) 210 { 211 int ret; 212 213 ret = pmic_reg_read(dev->parent, 214 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1)); 215 if (ret < 0) 216 return ret; 217 218 return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP : 219 STPMU1_BUCK_MODE_HP; 220 } 221 222 static int stpmu1_buck_set_mode(struct udevice *dev, int mode) 223 { 224 return pmic_clrsetbits(dev->parent, 225 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1), 226 STPMU1_BUCK_MODE, 227 mode ? STPMU1_BUCK_MODE : 0); 228 } 229 230 static int stpmu1_buck_probe(struct udevice *dev) 231 { 232 struct dm_regulator_uclass_platdata *uc_pdata; 233 234 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK) 235 return -EINVAL; 236 237 uc_pdata = dev_get_uclass_platdata(dev); 238 239 uc_pdata->type = REGULATOR_TYPE_BUCK; 240 uc_pdata->mode = (struct dm_regulator_mode *)buck_modes; 241 uc_pdata->mode_count = ARRAY_SIZE(buck_modes); 242 243 return 0; 244 } 245 246 static const struct dm_regulator_ops stpmu1_buck_ops = { 247 .get_value = stpmu1_buck_get_value, 248 .set_value = stpmu1_buck_set_value, 249 .get_enable = stpmu1_buck_get_enable, 250 .set_enable = stpmu1_buck_set_enable, 251 .get_mode = stpmu1_buck_get_mode, 252 .set_mode = stpmu1_buck_set_mode, 253 }; 254 255 U_BOOT_DRIVER(stpmu1_buck) = { 256 .name = "stpmu1_buck", 257 .id = UCLASS_REGULATOR, 258 .ops = &stpmu1_buck_ops, 259 .probe = stpmu1_buck_probe, 260 }; 261 262 /* 263 * LDO regulators 264 */ 265 266 static const struct stpmu1_range ldo12_ranges[] = { 267 STPMU1_RANGE(1700000, 0, 7, 0), 268 STPMU1_RANGE(1700000, 8, 24, 100000), 269 STPMU1_RANGE(3300000, 25, 31, 0), 270 }; 271 272 static const struct stpmu1_range ldo3_ranges[] = { 273 STPMU1_RANGE(1700000, 0, 7, 0), 274 STPMU1_RANGE(1700000, 8, 24, 100000), 275 STPMU1_RANGE(3300000, 25, 30, 0), 276 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */ 277 }; 278 279 static const struct stpmu1_range ldo5_ranges[] = { 280 STPMU1_RANGE(1700000, 0, 7, 0), 281 STPMU1_RANGE(1700000, 8, 30, 100000), 282 STPMU1_RANGE(3900000, 31, 31, 0), 283 }; 284 285 static const struct stpmu1_range ldo6_ranges[] = { 286 STPMU1_RANGE(900000, 0, 24, 100000), 287 STPMU1_RANGE(3300000, 25, 31, 0), 288 }; 289 290 /* LDO: 1,2,3,4,5,6 - voltage ranges */ 291 static const struct stpmu1_output_range ldo_voltage_range[] = { 292 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 293 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 294 STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)), 295 STPMU1_OUTPUT_RANGE(NULL, 0), 296 STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)), 297 STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)), 298 }; 299 300 /* LDO modes */ 301 static const struct dm_regulator_mode ldo_modes[] = { 302 STPMU1_MODE(STPMU1_LDO_MODE_NORMAL, 303 STPMU1_LDO_MODE_NORMAL, "NORMAL"), 304 STPMU1_MODE(STPMU1_LDO_MODE_BYPASS, 305 STPMU1_LDO_MODE_BYPASS, "BYPASS"), 306 STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE, 307 STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"), 308 }; 309 310 static int stpmu1_ldo_get_value(struct udevice *dev) 311 { 312 int sel, ldo = dev->driver_data - 1; 313 314 sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 315 if (sel < 0) 316 return sel; 317 318 /* ldo4 => 3,3V */ 319 if (ldo == STPMU1_LDO4) 320 return STPMU1_LDO4_UV; 321 322 sel &= STPMU1_LDO12356_OUTPUT_MASK; 323 sel >>= STPMU1_LDO12356_OUTPUT_SHIFT; 324 325 /* ldo3, sel = 31 => BUCK2/2 */ 326 if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL) 327 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2; 328 329 return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]); 330 } 331 332 static int stpmu1_ldo_set_value(struct udevice *dev, int uv) 333 { 334 int sel, ldo = dev->driver_data - 1; 335 336 /* ldo4 => not possible */ 337 if (ldo == STPMU1_LDO4) 338 return -EINVAL; 339 340 sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]); 341 if (sel < 0) 342 return sel; 343 344 return pmic_clrsetbits(dev->parent, 345 STPMU1_LDOX_CTRL_REG(ldo), 346 STPMU1_LDO12356_OUTPUT_MASK, 347 sel << STPMU1_LDO12356_OUTPUT_SHIFT); 348 } 349 350 static int stpmu1_ldo_get_enable(struct udevice *dev) 351 { 352 int ret; 353 354 ret = pmic_reg_read(dev->parent, 355 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1)); 356 if (ret < 0) 357 return false; 358 359 return ret & STPMU1_LDO_EN ? true : false; 360 } 361 362 static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable) 363 { 364 struct dm_regulator_uclass_platdata *uc_pdata; 365 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : 366 STPMU1_DEFAULT_STOP_DELAY_MS; 367 int ret, uv; 368 369 /* if regulator is already in the wanted state, nothing to do */ 370 if (stpmu1_ldo_get_enable(dev) == enable) 371 return 0; 372 373 if (enable) { 374 uc_pdata = dev_get_uclass_platdata(dev); 375 uv = stpmu1_ldo_get_value(dev); 376 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV)) 377 stpmu1_ldo_set_value(dev, uc_pdata->min_uV); 378 } 379 380 ret = pmic_clrsetbits(dev->parent, 381 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1), 382 STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0); 383 mdelay(delay); 384 385 return ret; 386 } 387 388 static int stpmu1_ldo_get_mode(struct udevice *dev) 389 { 390 int ret, ldo = dev->driver_data - 1; 391 392 if (ldo != STPMU1_LDO3) 393 return -EINVAL; 394 395 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 396 if (ret < 0) 397 return ret; 398 399 if (ret & STPMU1_LDO3_MODE) 400 return STPMU1_LDO_MODE_BYPASS; 401 402 ret &= STPMU1_LDO12356_OUTPUT_MASK; 403 ret >>= STPMU1_LDO12356_OUTPUT_SHIFT; 404 405 return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE : 406 STPMU1_LDO_MODE_NORMAL; 407 } 408 409 static int stpmu1_ldo_set_mode(struct udevice *dev, int mode) 410 { 411 int ret, ldo = dev->driver_data - 1; 412 413 if (ldo != STPMU1_LDO3) 414 return -EINVAL; 415 416 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 417 if (ret < 0) 418 return ret; 419 420 switch (mode) { 421 case STPMU1_LDO_MODE_SINK_SOURCE: 422 ret &= ~STPMU1_LDO12356_OUTPUT_MASK; 423 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT; 424 case STPMU1_LDO_MODE_NORMAL: 425 ret &= ~STPMU1_LDO3_MODE; 426 break; 427 case STPMU1_LDO_MODE_BYPASS: 428 ret |= STPMU1_LDO3_MODE; 429 break; 430 } 431 432 return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret); 433 } 434 435 static int stpmu1_ldo_probe(struct udevice *dev) 436 { 437 struct dm_regulator_uclass_platdata *uc_pdata; 438 439 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO) 440 return -EINVAL; 441 442 uc_pdata = dev_get_uclass_platdata(dev); 443 444 uc_pdata->type = REGULATOR_TYPE_LDO; 445 if (dev->driver_data - 1 == STPMU1_LDO3) { 446 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes; 447 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes); 448 } else { 449 uc_pdata->mode_count = 0; 450 } 451 452 return 0; 453 } 454 455 static const struct dm_regulator_ops stpmu1_ldo_ops = { 456 .get_value = stpmu1_ldo_get_value, 457 .set_value = stpmu1_ldo_set_value, 458 .get_enable = stpmu1_ldo_get_enable, 459 .set_enable = stpmu1_ldo_set_enable, 460 .get_mode = stpmu1_ldo_get_mode, 461 .set_mode = stpmu1_ldo_set_mode, 462 }; 463 464 U_BOOT_DRIVER(stpmu1_ldo) = { 465 .name = "stpmu1_ldo", 466 .id = UCLASS_REGULATOR, 467 .ops = &stpmu1_ldo_ops, 468 .probe = stpmu1_ldo_probe, 469 }; 470 471 /* 472 * VREF DDR regulator 473 */ 474 475 static int stpmu1_vref_ddr_get_value(struct udevice *dev) 476 { 477 /* BUCK2/2 */ 478 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2; 479 } 480 481 static int stpmu1_vref_ddr_get_enable(struct udevice *dev) 482 { 483 int ret; 484 485 ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG); 486 if (ret < 0) 487 return false; 488 489 return ret & STPMU1_VREF_EN ? true : false; 490 } 491 492 static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable) 493 { 494 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : 495 STPMU1_DEFAULT_STOP_DELAY_MS; 496 int ret; 497 498 /* if regulator is already in the wanted state, nothing to do */ 499 if (stpmu1_vref_ddr_get_enable(dev) == enable) 500 return 0; 501 502 ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG, 503 STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0); 504 mdelay(delay); 505 506 return ret; 507 } 508 509 static int stpmu1_vref_ddr_probe(struct udevice *dev) 510 { 511 struct dm_regulator_uclass_platdata *uc_pdata; 512 513 uc_pdata = dev_get_uclass_platdata(dev); 514 515 uc_pdata->type = REGULATOR_TYPE_FIXED; 516 uc_pdata->mode_count = 0; 517 518 return 0; 519 } 520 521 static const struct dm_regulator_ops stpmu1_vref_ddr_ops = { 522 .get_value = stpmu1_vref_ddr_get_value, 523 .get_enable = stpmu1_vref_ddr_get_enable, 524 .set_enable = stpmu1_vref_ddr_set_enable, 525 }; 526 527 U_BOOT_DRIVER(stpmu1_vref_ddr) = { 528 .name = "stpmu1_vref_ddr", 529 .id = UCLASS_REGULATOR, 530 .ops = &stpmu1_vref_ddr_ops, 531 .probe = stpmu1_vref_ddr_probe, 532 }; 533 534 /* 535 * BOOST regulator 536 */ 537 538 static int stpmu1_boost_get_enable(struct udevice *dev) 539 { 540 int ret; 541 542 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 543 if (ret < 0) 544 return false; 545 546 return ret & STPMU1_USB_BOOST_EN ? true : false; 547 } 548 549 static int stpmu1_boost_set_enable(struct udevice *dev, bool enable) 550 { 551 int ret; 552 553 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 554 if (ret < 0) 555 return ret; 556 557 if (!enable && ret & STPMU1_USB_PWR_SW_EN) 558 return -EINVAL; 559 560 /* if regulator is already in the wanted state, nothing to do */ 561 if (!!(ret & STPMU1_USB_BOOST_EN) == enable) 562 return 0; 563 564 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 565 STPMU1_USB_BOOST_EN, 566 enable ? STPMU1_USB_BOOST_EN : 0); 567 if (enable) 568 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS); 569 570 return ret; 571 } 572 573 static int stpmu1_boost_probe(struct udevice *dev) 574 { 575 struct dm_regulator_uclass_platdata *uc_pdata; 576 577 uc_pdata = dev_get_uclass_platdata(dev); 578 579 uc_pdata->type = REGULATOR_TYPE_FIXED; 580 uc_pdata->mode_count = 0; 581 582 return 0; 583 } 584 585 static const struct dm_regulator_ops stpmu1_boost_ops = { 586 .get_enable = stpmu1_boost_get_enable, 587 .set_enable = stpmu1_boost_set_enable, 588 }; 589 590 U_BOOT_DRIVER(stpmu1_boost) = { 591 .name = "stpmu1_boost", 592 .id = UCLASS_REGULATOR, 593 .ops = &stpmu1_boost_ops, 594 .probe = stpmu1_boost_probe, 595 }; 596 597 /* 598 * USB power switch 599 */ 600 601 static int stpmu1_pwr_sw_get_enable(struct udevice *dev) 602 { 603 uint mask = 1 << dev->driver_data; 604 int ret; 605 606 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 607 if (ret < 0) 608 return false; 609 610 return ret & mask ? true : false; 611 } 612 613 static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable) 614 { 615 uint mask = 1 << dev->driver_data; 616 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS : 617 STPMU1_DEFAULT_STOP_DELAY_MS; 618 int ret; 619 620 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 621 if (ret < 0) 622 return ret; 623 624 /* if regulator is already in the wanted state, nothing to do */ 625 if (!!(ret & mask) == enable) 626 return 0; 627 628 /* Boost management */ 629 if (enable && !(ret & STPMU1_USB_BOOST_EN)) { 630 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 631 STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN); 632 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS); 633 } else if (!enable && ret & STPMU1_USB_BOOST_EN && 634 (ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) { 635 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 636 STPMU1_USB_BOOST_EN, 0); 637 } 638 639 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 640 mask, enable ? mask : 0); 641 mdelay(delay); 642 643 return ret; 644 } 645 646 static int stpmu1_pwr_sw_probe(struct udevice *dev) 647 { 648 struct dm_regulator_uclass_platdata *uc_pdata; 649 650 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW) 651 return -EINVAL; 652 653 uc_pdata = dev_get_uclass_platdata(dev); 654 655 uc_pdata->type = REGULATOR_TYPE_FIXED; 656 uc_pdata->mode_count = 0; 657 658 return 0; 659 } 660 661 static const struct dm_regulator_ops stpmu1_pwr_sw_ops = { 662 .get_enable = stpmu1_pwr_sw_get_enable, 663 .set_enable = stpmu1_pwr_sw_set_enable, 664 }; 665 666 U_BOOT_DRIVER(stpmu1_pwr_sw) = { 667 .name = "stpmu1_pwr_sw", 668 .id = UCLASS_REGULATOR, 669 .ops = &stpmu1_pwr_sw_ops, 670 .probe = stpmu1_pwr_sw_probe, 671 }; 672