1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <power/pmic.h> 11 #include <power/regulator.h> 12 #include <power/stpmu1.h> 13 14 struct stpmu1_range { 15 int min_uv; 16 int min_sel; 17 int max_sel; 18 int step; 19 }; 20 21 struct stpmu1_output_range { 22 const struct stpmu1_range *ranges; 23 int nbranges; 24 }; 25 26 #define STPMU1_MODE(_id, _val, _name) { \ 27 .id = _id, \ 28 .register_value = _val, \ 29 .name = _name, \ 30 } 31 32 #define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \ 33 .min_uv = _min_uv, \ 34 .min_sel = _min_sel, \ 35 .max_sel = _max_sel, \ 36 .step = _step, \ 37 } 38 39 #define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \ 40 .ranges = _ranges, \ 41 .nbranges = _nbranges, \ 42 } 43 44 static int stpmu1_output_find_uv(int sel, 45 const struct stpmu1_output_range *output_range) 46 { 47 const struct stpmu1_range *range; 48 int i; 49 50 for (i = 0, range = output_range->ranges; 51 i < output_range->nbranges; i++, range++) { 52 if (sel >= range->min_sel && sel <= range->max_sel) 53 return range->min_uv + 54 (sel - range->min_sel) * range->step; 55 } 56 57 return -EINVAL; 58 } 59 60 static int stpmu1_output_find_sel(int uv, 61 const struct stpmu1_output_range *output_range) 62 { 63 const struct stpmu1_range *range; 64 int i; 65 66 for (i = 0, range = output_range->ranges; 67 i < output_range->nbranges; i++, range++) { 68 if (uv == range->min_uv && !range->step) 69 return range->min_sel; 70 71 if (uv >= range->min_uv && 72 uv <= range->min_uv + 73 (range->max_sel - range->min_sel) * range->step) 74 return range->min_sel + 75 (uv - range->min_uv) / range->step; 76 } 77 78 return -EINVAL; 79 } 80 81 /* 82 * BUCK regulators 83 */ 84 85 static const struct stpmu1_range buck1_ranges[] = { 86 STPMU1_RANGE(600000, 0, 30, 25000), 87 STPMU1_RANGE(1350000, 31, 63, 0), 88 }; 89 90 static const struct stpmu1_range buck2_ranges[] = { 91 STPMU1_RANGE(1000000, 0, 17, 0), 92 STPMU1_RANGE(1050000, 18, 19, 0), 93 STPMU1_RANGE(1100000, 20, 21, 0), 94 STPMU1_RANGE(1150000, 22, 23, 0), 95 STPMU1_RANGE(1200000, 24, 25, 0), 96 STPMU1_RANGE(1250000, 26, 27, 0), 97 STPMU1_RANGE(1300000, 28, 29, 0), 98 STPMU1_RANGE(1350000, 30, 31, 0), 99 STPMU1_RANGE(1400000, 32, 33, 0), 100 STPMU1_RANGE(1450000, 34, 35, 0), 101 STPMU1_RANGE(1500000, 36, 63, 0), 102 }; 103 104 static const struct stpmu1_range buck3_ranges[] = { 105 STPMU1_RANGE(1000000, 0, 19, 0), 106 STPMU1_RANGE(1100000, 20, 23, 0), 107 STPMU1_RANGE(1200000, 24, 27, 0), 108 STPMU1_RANGE(1300000, 28, 31, 0), 109 STPMU1_RANGE(1400000, 32, 35, 0), 110 STPMU1_RANGE(1500000, 36, 55, 100000), 111 STPMU1_RANGE(3400000, 56, 63, 0), 112 }; 113 114 static const struct stpmu1_range buck4_ranges[] = { 115 STPMU1_RANGE(600000, 0, 27, 25000), 116 STPMU1_RANGE(1300000, 28, 29, 0), 117 STPMU1_RANGE(1350000, 30, 31, 0), 118 STPMU1_RANGE(1400000, 32, 33, 0), 119 STPMU1_RANGE(1450000, 34, 35, 0), 120 STPMU1_RANGE(1500000, 36, 60, 100000), 121 STPMU1_RANGE(3900000, 61, 63, 0), 122 }; 123 124 /* BUCK: 1,2,3,4 - voltage ranges */ 125 static const struct stpmu1_output_range buck_voltage_range[] = { 126 STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)), 127 STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)), 128 STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)), 129 STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)), 130 }; 131 132 /* BUCK modes */ 133 static const struct dm_regulator_mode buck_modes[] = { 134 STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"), 135 STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"), 136 }; 137 138 static int stpmu1_buck_get_uv(struct udevice *dev, int buck) 139 { 140 int sel; 141 142 sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck)); 143 if (sel < 0) 144 return sel; 145 146 sel &= STPMU1_BUCK_OUTPUT_MASK; 147 sel >>= STPMU1_BUCK_OUTPUT_SHIFT; 148 149 return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]); 150 } 151 152 static int stpmu1_buck_get_value(struct udevice *dev) 153 { 154 return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1); 155 } 156 157 static int stpmu1_buck_set_value(struct udevice *dev, int uv) 158 { 159 int sel, buck = dev->driver_data - 1; 160 161 sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]); 162 if (sel < 0) 163 return sel; 164 165 return pmic_clrsetbits(dev->parent, 166 STPMU1_BUCKX_CTRL_REG(buck), 167 STPMU1_BUCK_OUTPUT_MASK, 168 sel << STPMU1_BUCK_OUTPUT_SHIFT); 169 } 170 171 static int stpmu1_buck_get_enable(struct udevice *dev) 172 { 173 int ret; 174 175 ret = pmic_reg_read(dev->parent, 176 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1)); 177 if (ret < 0) 178 return false; 179 180 return ret & STPMU1_BUCK_EN ? true : false; 181 } 182 183 static int stpmu1_buck_set_enable(struct udevice *dev, bool enable) 184 { 185 struct dm_regulator_uclass_platdata *uc_pdata; 186 int ret, uv; 187 188 /* if regulator is already in the wanted state, nothing to do */ 189 if (stpmu1_buck_get_enable(dev) == enable) 190 return 0; 191 192 if (enable) { 193 uc_pdata = dev_get_uclass_platdata(dev); 194 uv = stpmu1_buck_get_value(dev); 195 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV)) 196 stpmu1_buck_set_value(dev, uc_pdata->min_uV); 197 } 198 199 ret = pmic_clrsetbits(dev->parent, 200 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1), 201 STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0); 202 if (enable) 203 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 204 205 return ret; 206 } 207 208 static int stpmu1_buck_get_mode(struct udevice *dev) 209 { 210 int ret; 211 212 ret = pmic_reg_read(dev->parent, 213 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1)); 214 if (ret < 0) 215 return ret; 216 217 return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP : 218 STPMU1_BUCK_MODE_HP; 219 } 220 221 static int stpmu1_buck_set_mode(struct udevice *dev, int mode) 222 { 223 return pmic_clrsetbits(dev->parent, 224 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1), 225 STPMU1_BUCK_MODE, 226 mode ? STPMU1_BUCK_MODE : 0); 227 } 228 229 static int stpmu1_buck_probe(struct udevice *dev) 230 { 231 struct dm_regulator_uclass_platdata *uc_pdata; 232 233 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK) 234 return -EINVAL; 235 236 uc_pdata = dev_get_uclass_platdata(dev); 237 238 uc_pdata->type = REGULATOR_TYPE_BUCK; 239 uc_pdata->mode = (struct dm_regulator_mode *)buck_modes; 240 uc_pdata->mode_count = ARRAY_SIZE(buck_modes); 241 242 return 0; 243 } 244 245 static const struct dm_regulator_ops stpmu1_buck_ops = { 246 .get_value = stpmu1_buck_get_value, 247 .set_value = stpmu1_buck_set_value, 248 .get_enable = stpmu1_buck_get_enable, 249 .set_enable = stpmu1_buck_set_enable, 250 .get_mode = stpmu1_buck_get_mode, 251 .set_mode = stpmu1_buck_set_mode, 252 }; 253 254 U_BOOT_DRIVER(stpmu1_buck) = { 255 .name = "stpmu1_buck", 256 .id = UCLASS_REGULATOR, 257 .ops = &stpmu1_buck_ops, 258 .probe = stpmu1_buck_probe, 259 }; 260 261 /* 262 * LDO regulators 263 */ 264 265 static const struct stpmu1_range ldo12_ranges[] = { 266 STPMU1_RANGE(1700000, 0, 7, 0), 267 STPMU1_RANGE(1700000, 8, 24, 100000), 268 STPMU1_RANGE(3300000, 25, 31, 0), 269 }; 270 271 static const struct stpmu1_range ldo3_ranges[] = { 272 STPMU1_RANGE(1700000, 0, 7, 0), 273 STPMU1_RANGE(1700000, 8, 24, 100000), 274 STPMU1_RANGE(3300000, 25, 30, 0), 275 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */ 276 }; 277 278 static const struct stpmu1_range ldo5_ranges[] = { 279 STPMU1_RANGE(1700000, 0, 7, 0), 280 STPMU1_RANGE(1700000, 8, 30, 100000), 281 STPMU1_RANGE(3900000, 31, 31, 0), 282 }; 283 284 static const struct stpmu1_range ldo6_ranges[] = { 285 STPMU1_RANGE(900000, 0, 24, 100000), 286 STPMU1_RANGE(3300000, 25, 31, 0), 287 }; 288 289 /* LDO: 1,2,3,4,5,6 - voltage ranges */ 290 static const struct stpmu1_output_range ldo_voltage_range[] = { 291 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 292 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)), 293 STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)), 294 STPMU1_OUTPUT_RANGE(NULL, 0), 295 STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)), 296 STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)), 297 }; 298 299 /* LDO modes */ 300 static const struct dm_regulator_mode ldo_modes[] = { 301 STPMU1_MODE(STPMU1_LDO_MODE_NORMAL, 302 STPMU1_LDO_MODE_NORMAL, "NORMAL"), 303 STPMU1_MODE(STPMU1_LDO_MODE_BYPASS, 304 STPMU1_LDO_MODE_BYPASS, "BYPASS"), 305 STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE, 306 STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"), 307 }; 308 309 static int stpmu1_ldo_get_value(struct udevice *dev) 310 { 311 int sel, ldo = dev->driver_data - 1; 312 313 sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 314 if (sel < 0) 315 return sel; 316 317 /* ldo4 => 3,3V */ 318 if (ldo == STPMU1_LDO4) 319 return STPMU1_LDO4_UV; 320 321 sel &= STPMU1_LDO12356_OUTPUT_MASK; 322 sel >>= STPMU1_LDO12356_OUTPUT_SHIFT; 323 324 /* ldo3, sel = 31 => BUCK2/2 */ 325 if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL) 326 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2; 327 328 return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]); 329 } 330 331 static int stpmu1_ldo_set_value(struct udevice *dev, int uv) 332 { 333 int sel, ldo = dev->driver_data - 1; 334 335 /* ldo4 => not possible */ 336 if (ldo == STPMU1_LDO4) 337 return -EINVAL; 338 339 sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]); 340 if (sel < 0) 341 return sel; 342 343 return pmic_clrsetbits(dev->parent, 344 STPMU1_LDOX_CTRL_REG(ldo), 345 STPMU1_LDO12356_OUTPUT_MASK, 346 sel << STPMU1_LDO12356_OUTPUT_SHIFT); 347 } 348 349 static int stpmu1_ldo_get_enable(struct udevice *dev) 350 { 351 int ret; 352 353 ret = pmic_reg_read(dev->parent, 354 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1)); 355 if (ret < 0) 356 return false; 357 358 return ret & STPMU1_LDO_EN ? true : false; 359 } 360 361 static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable) 362 { 363 struct dm_regulator_uclass_platdata *uc_pdata; 364 int ret, uv; 365 366 /* if regulator is already in the wanted state, nothing to do */ 367 if (stpmu1_ldo_get_enable(dev) == enable) 368 return 0; 369 370 if (enable) { 371 uc_pdata = dev_get_uclass_platdata(dev); 372 uv = stpmu1_ldo_get_value(dev); 373 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV)) 374 stpmu1_ldo_set_value(dev, uc_pdata->min_uV); 375 } 376 377 ret = pmic_clrsetbits(dev->parent, 378 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1), 379 STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0); 380 if (enable) 381 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 382 383 return ret; 384 } 385 386 static int stpmu1_ldo_get_mode(struct udevice *dev) 387 { 388 int ret, ldo = dev->driver_data - 1; 389 390 if (ldo != STPMU1_LDO3) 391 return -EINVAL; 392 393 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 394 if (ret < 0) 395 return ret; 396 397 if (ret & STPMU1_LDO3_MODE) 398 return STPMU1_LDO_MODE_BYPASS; 399 400 ret &= STPMU1_LDO12356_OUTPUT_MASK; 401 ret >>= STPMU1_LDO12356_OUTPUT_SHIFT; 402 403 return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE : 404 STPMU1_LDO_MODE_NORMAL; 405 } 406 407 static int stpmu1_ldo_set_mode(struct udevice *dev, int mode) 408 { 409 int ret, ldo = dev->driver_data - 1; 410 411 if (ldo != STPMU1_LDO3) 412 return -EINVAL; 413 414 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo)); 415 if (ret < 0) 416 return ret; 417 418 switch (mode) { 419 case STPMU1_LDO_MODE_SINK_SOURCE: 420 ret &= ~STPMU1_LDO12356_OUTPUT_MASK; 421 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT; 422 case STPMU1_LDO_MODE_NORMAL: 423 ret &= ~STPMU1_LDO3_MODE; 424 break; 425 case STPMU1_LDO_MODE_BYPASS: 426 ret |= STPMU1_LDO3_MODE; 427 break; 428 } 429 430 return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret); 431 } 432 433 static int stpmu1_ldo_probe(struct udevice *dev) 434 { 435 struct dm_regulator_uclass_platdata *uc_pdata; 436 437 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO) 438 return -EINVAL; 439 440 uc_pdata = dev_get_uclass_platdata(dev); 441 442 uc_pdata->type = REGULATOR_TYPE_LDO; 443 if (dev->driver_data - 1 == STPMU1_LDO3) { 444 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes; 445 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes); 446 } else { 447 uc_pdata->mode_count = 0; 448 } 449 450 return 0; 451 } 452 453 static const struct dm_regulator_ops stpmu1_ldo_ops = { 454 .get_value = stpmu1_ldo_get_value, 455 .set_value = stpmu1_ldo_set_value, 456 .get_enable = stpmu1_ldo_get_enable, 457 .set_enable = stpmu1_ldo_set_enable, 458 .get_mode = stpmu1_ldo_get_mode, 459 .set_mode = stpmu1_ldo_set_mode, 460 }; 461 462 U_BOOT_DRIVER(stpmu1_ldo) = { 463 .name = "stpmu1_ldo", 464 .id = UCLASS_REGULATOR, 465 .ops = &stpmu1_ldo_ops, 466 .probe = stpmu1_ldo_probe, 467 }; 468 469 /* 470 * VREF DDR regulator 471 */ 472 473 static int stpmu1_vref_ddr_get_value(struct udevice *dev) 474 { 475 /* BUCK2/2 */ 476 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2; 477 } 478 479 static int stpmu1_vref_ddr_get_enable(struct udevice *dev) 480 { 481 int ret; 482 483 ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG); 484 if (ret < 0) 485 return false; 486 487 return ret & STPMU1_VREF_EN ? true : false; 488 } 489 490 static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable) 491 { 492 int ret; 493 494 /* if regulator is already in the wanted state, nothing to do */ 495 if (stpmu1_vref_ddr_get_enable(dev) == enable) 496 return 0; 497 498 ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG, 499 STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0); 500 if (enable) 501 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 502 503 return ret; 504 } 505 506 static int stpmu1_vref_ddr_probe(struct udevice *dev) 507 { 508 struct dm_regulator_uclass_platdata *uc_pdata; 509 510 uc_pdata = dev_get_uclass_platdata(dev); 511 512 uc_pdata->type = REGULATOR_TYPE_FIXED; 513 uc_pdata->mode_count = 0; 514 515 return 0; 516 } 517 518 static const struct dm_regulator_ops stpmu1_vref_ddr_ops = { 519 .get_value = stpmu1_vref_ddr_get_value, 520 .get_enable = stpmu1_vref_ddr_get_enable, 521 .set_enable = stpmu1_vref_ddr_set_enable, 522 }; 523 524 U_BOOT_DRIVER(stpmu1_vref_ddr) = { 525 .name = "stpmu1_vref_ddr", 526 .id = UCLASS_REGULATOR, 527 .ops = &stpmu1_vref_ddr_ops, 528 .probe = stpmu1_vref_ddr_probe, 529 }; 530 531 /* 532 * BOOST regulator 533 */ 534 535 static int stpmu1_boost_get_enable(struct udevice *dev) 536 { 537 int ret; 538 539 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 540 if (ret < 0) 541 return false; 542 543 return ret & STPMU1_USB_BOOST_EN ? true : false; 544 } 545 546 static int stpmu1_boost_set_enable(struct udevice *dev, bool enable) 547 { 548 int ret; 549 550 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 551 if (ret < 0) 552 return ret; 553 554 if (!enable && ret & STPMU1_USB_PWR_SW_EN) 555 return -EINVAL; 556 557 /* if regulator is already in the wanted state, nothing to do */ 558 if (!!(ret & STPMU1_USB_BOOST_EN) == enable) 559 return 0; 560 561 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 562 STPMU1_USB_BOOST_EN, 563 enable ? STPMU1_USB_BOOST_EN : 0); 564 if (enable) 565 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS); 566 567 return ret; 568 } 569 570 static int stpmu1_boost_probe(struct udevice *dev) 571 { 572 struct dm_regulator_uclass_platdata *uc_pdata; 573 574 uc_pdata = dev_get_uclass_platdata(dev); 575 576 uc_pdata->type = REGULATOR_TYPE_FIXED; 577 uc_pdata->mode_count = 0; 578 579 return 0; 580 } 581 582 static const struct dm_regulator_ops stpmu1_boost_ops = { 583 .get_enable = stpmu1_boost_get_enable, 584 .set_enable = stpmu1_boost_set_enable, 585 }; 586 587 U_BOOT_DRIVER(stpmu1_boost) = { 588 .name = "stpmu1_boost", 589 .id = UCLASS_REGULATOR, 590 .ops = &stpmu1_boost_ops, 591 .probe = stpmu1_boost_probe, 592 }; 593 594 /* 595 * USB power switch 596 */ 597 598 static int stpmu1_pwr_sw_get_enable(struct udevice *dev) 599 { 600 uint mask = 1 << dev->driver_data; 601 int ret; 602 603 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 604 if (ret < 0) 605 return false; 606 607 return ret & mask ? true : false; 608 } 609 610 static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable) 611 { 612 uint mask = 1 << dev->driver_data; 613 int ret; 614 615 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG); 616 if (ret < 0) 617 return ret; 618 619 /* if regulator is already in the wanted state, nothing to do */ 620 if (!!(ret & mask) == enable) 621 return 0; 622 623 /* Boost management */ 624 if (enable && !(ret & STPMU1_USB_BOOST_EN)) { 625 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 626 STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN); 627 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS); 628 } else if (!enable && ret & STPMU1_USB_BOOST_EN && 629 (ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) { 630 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 631 STPMU1_USB_BOOST_EN, 0); 632 } 633 634 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG, 635 mask, enable ? mask : 0); 636 if (enable) 637 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 638 639 return ret; 640 } 641 642 static int stpmu1_pwr_sw_probe(struct udevice *dev) 643 { 644 struct dm_regulator_uclass_platdata *uc_pdata; 645 646 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW) 647 return -EINVAL; 648 649 uc_pdata = dev_get_uclass_platdata(dev); 650 651 uc_pdata->type = REGULATOR_TYPE_FIXED; 652 uc_pdata->mode_count = 0; 653 654 return 0; 655 } 656 657 static const struct dm_regulator_ops stpmu1_pwr_sw_ops = { 658 .get_enable = stpmu1_pwr_sw_get_enable, 659 .set_enable = stpmu1_pwr_sw_set_enable, 660 }; 661 662 U_BOOT_DRIVER(stpmu1_pwr_sw) = { 663 .name = "stpmu1_pwr_sw", 664 .id = UCLASS_REGULATOR, 665 .ops = &stpmu1_pwr_sw_ops, 666 .probe = stpmu1_pwr_sw_probe, 667 }; 668