1 /*
2  * Copyright (C) 2015 Google, Inc
3  * Written by Simon Glass <sjg@chromium.org>
4  *
5  * Based on Rockchip's drivers/power/pmic/pmic_act8846.c:
6  * Copyright (C) 2012 rockchips
7  * zyw <zyw@rock-chips.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <power/act8846_pmic.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
18 
19 static const u16 voltage_map[] = {
20 	600, 625, 650, 675, 700, 725, 750, 775,
21 	800, 825, 850, 875, 900, 925, 950, 975,
22 	1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175,
23 	1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550,
24 	1600, 1650, 1700, 1750, 1800, 1850, 1900, 1950,
25 	2000, 2050, 2100, 2150, 2200, 2250, 2300, 2350,
26 	2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100,
27 	3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900,
28 };
29 
30 enum {
31 	REG_SYS0,
32 	REG_SYS1,
33 	REG1_VOL	= 0x10,
34 	REG1_CTL	= 0X11,
35 	REG2_VOL0	= 0x20,
36 	REG2_VOL1,
37 	REG2_CTL,
38 	REG3_VOL0	= 0x30,
39 	REG3_VOL1,
40 	REG3_CTL,
41 	REG4_VOL0	= 0x40,
42 	REG4_VOL1,
43 	REG4_CTL,
44 	REG5_VOL	= 0x50,
45 	REG5_CTL,
46 	REG6_VOL	= 0X58,
47 	REG6_CTL,
48 	REG7_VOL	= 0x60,
49 	REG7_CTL,
50 	REG8_VOL	= 0x68,
51 	REG8_CTL,
52 	REG9_VOL	= 0x70,
53 	REG9_CTL,
54 	REG10_VOL	= 0x80,
55 	REG10_CTL,
56 	REG11_VOL	= 0x90,
57 	REG11_CTL,
58 	REG12_VOL	= 0xa0,
59 	REG12_CTL,
60 	REG13		= 0xb1,
61 };
62 
63 static const u8 addr_vol[] = {
64 	0, REG1_VOL, REG2_VOL0, REG3_VOL0, REG4_VOL0,
65 	REG5_VOL, REG6_VOL, REG7_VOL, REG8_VOL, REG9_VOL,
66 	REG10_VOL, REG11_VOL, REG12_VOL,
67 };
68 
69 static const u8 addr_ctl[] = {
70 	0, REG1_CTL, REG2_CTL, REG3_CTL, REG4_CTL,
71 	REG5_CTL, REG6_CTL, REG7_CTL, REG8_CTL, REG9_CTL,
72 	REG10_CTL, REG11_CTL, REG12_CTL,
73 };
74 
75 static int check_volt_table(const u16 *volt_table, int uvolt)
76 {
77 	int i;
78 
79 	for (i = VOL_MIN_IDX; i < VOL_MAX_IDX; i++) {
80 		if (uvolt <= (volt_table[i] * 1000))
81 			return i;
82 	}
83 	return -EINVAL;
84 }
85 
86 static int reg_get_value(struct udevice *dev)
87 {
88 	int reg = dev->driver_data;
89 	int ret;
90 
91 	ret = pmic_reg_read(dev->parent, addr_vol[reg]);
92 	if (ret < 0)
93 		return ret;
94 
95 	return voltage_map[ret & LDO_VOL_MASK] * 1000;
96 }
97 
98 static int reg_set_value(struct udevice *dev, int uvolt)
99 {
100 	int reg = dev->driver_data;
101 	int val;
102 
103 	val = check_volt_table(voltage_map, uvolt);
104 	if (val < 0)
105 		return val;
106 
107 	return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
108 }
109 
110 static int reg_set_enable(struct udevice *dev, bool enable)
111 {
112 	int reg = dev->driver_data;
113 
114 	return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
115 			       enable ? LDO_EN_MASK : 0);
116 }
117 
118 static int reg_get_enable(struct udevice *dev)
119 {
120 	int reg = dev->driver_data;
121 	int ret;
122 
123 	ret = pmic_reg_read(dev->parent, addr_ctl[reg]);
124 	if (ret < 0)
125 		return ret;
126 
127 	return ret & LDO_EN_MASK ? true : false;
128 }
129 
130 static int act8846_reg_probe(struct udevice *dev)
131 {
132 	struct dm_regulator_uclass_platdata *uc_pdata;
133 	int reg = dev->driver_data;
134 
135 	uc_pdata = dev_get_uclass_platdata(dev);
136 
137 	uc_pdata->type = reg <= 4 ? REGULATOR_TYPE_BUCK : REGULATOR_TYPE_LDO;
138 	uc_pdata->mode_count = 0;
139 
140 	return 0;
141 }
142 
143 static const struct dm_regulator_ops act8846_reg_ops = {
144 	.get_value  = reg_get_value,
145 	.set_value  = reg_set_value,
146 	.get_enable = reg_get_enable,
147 	.set_enable = reg_set_enable,
148 };
149 
150 U_BOOT_DRIVER(act8846_buck) = {
151 	.name = "act8846_reg",
152 	.id = UCLASS_REGULATOR,
153 	.ops = &act8846_reg_ops,
154 	.probe = act8846_reg_probe,
155 };
156