15c7f10fdSOliver Schinagl /* 2bdcdf846SHans de Goede * AXP221 and AXP223 driver 3bdcdf846SHans de Goede * 4bdcdf846SHans de Goede * IMPORTANT when making changes to this file check that the registers 5bdcdf846SHans de Goede * used are the same for the axp221 and axp223. 6bdcdf846SHans de Goede * 7bdcdf846SHans de Goede * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 85c7f10fdSOliver Schinagl * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> 95c7f10fdSOliver Schinagl * 105c7f10fdSOliver Schinagl * SPDX-License-Identifier: GPL-2.0+ 115c7f10fdSOliver Schinagl */ 125c7f10fdSOliver Schinagl 135c7f10fdSOliver Schinagl #include <common.h> 145c7f10fdSOliver Schinagl #include <errno.h> 15f7c7ab63SPaul Kocialkowski #include <asm/arch/gpio.h> 16*1d624a4fSHans de Goede #include <asm/arch/pmic_bus.h> 175c7f10fdSOliver Schinagl #include <axp221.h> 185c7f10fdSOliver Schinagl 195c7f10fdSOliver Schinagl static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div) 205c7f10fdSOliver Schinagl { 215c7f10fdSOliver Schinagl if (mvolt < min) 225c7f10fdSOliver Schinagl mvolt = min; 235c7f10fdSOliver Schinagl else if (mvolt > max) 245c7f10fdSOliver Schinagl mvolt = max; 255c7f10fdSOliver Schinagl 265c7f10fdSOliver Schinagl return (mvolt - min) / div; 275c7f10fdSOliver Schinagl } 285c7f10fdSOliver Schinagl 295c7f10fdSOliver Schinagl int axp221_set_dcdc1(unsigned int mvolt) 305c7f10fdSOliver Schinagl { 315c7f10fdSOliver Schinagl int ret; 325c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); 335c7f10fdSOliver Schinagl 3450e0d5e6SHans de Goede if (mvolt == 0) 35*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 3650e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC1_EN); 3750e0d5e6SHans de Goede 38bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg); 395c7f10fdSOliver Schinagl if (ret) 405c7f10fdSOliver Schinagl return ret; 415c7f10fdSOliver Schinagl 42*1d624a4fSHans de Goede ret = pmic_bus_setbits(AXP221_OUTPUT_CTRL2, 4350e0d5e6SHans de Goede AXP221_OUTPUT_CTRL2_DCDC1SW_EN); 4450e0d5e6SHans de Goede if (ret) 4550e0d5e6SHans de Goede return ret; 4650e0d5e6SHans de Goede 47*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 4850e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC1_EN); 495c7f10fdSOliver Schinagl } 505c7f10fdSOliver Schinagl 515c7f10fdSOliver Schinagl int axp221_set_dcdc2(unsigned int mvolt) 525c7f10fdSOliver Schinagl { 5350e0d5e6SHans de Goede int ret; 545c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); 555c7f10fdSOliver Schinagl 5650e0d5e6SHans de Goede if (mvolt == 0) 57*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 5850e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC2_EN); 5950e0d5e6SHans de Goede 6050e0d5e6SHans de Goede ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg); 6150e0d5e6SHans de Goede if (ret) 6250e0d5e6SHans de Goede return ret; 6350e0d5e6SHans de Goede 64*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 6550e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC2_EN); 665c7f10fdSOliver Schinagl } 675c7f10fdSOliver Schinagl 685c7f10fdSOliver Schinagl int axp221_set_dcdc3(unsigned int mvolt) 695c7f10fdSOliver Schinagl { 7050e0d5e6SHans de Goede int ret; 715c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); 725c7f10fdSOliver Schinagl 7350e0d5e6SHans de Goede if (mvolt == 0) 74*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 7550e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC3_EN); 7650e0d5e6SHans de Goede 7750e0d5e6SHans de Goede ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg); 7850e0d5e6SHans de Goede if (ret) 7950e0d5e6SHans de Goede return ret; 8050e0d5e6SHans de Goede 81*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 8250e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC3_EN); 835c7f10fdSOliver Schinagl } 845c7f10fdSOliver Schinagl 855c7f10fdSOliver Schinagl int axp221_set_dcdc4(unsigned int mvolt) 865c7f10fdSOliver Schinagl { 8750e0d5e6SHans de Goede int ret; 885c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); 895c7f10fdSOliver Schinagl 9050e0d5e6SHans de Goede if (mvolt == 0) 91*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 9250e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC4_EN); 9350e0d5e6SHans de Goede 9450e0d5e6SHans de Goede ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg); 9550e0d5e6SHans de Goede if (ret) 9650e0d5e6SHans de Goede return ret; 9750e0d5e6SHans de Goede 98*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 9950e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC4_EN); 1005c7f10fdSOliver Schinagl } 1015c7f10fdSOliver Schinagl 1025c7f10fdSOliver Schinagl int axp221_set_dcdc5(unsigned int mvolt) 1035c7f10fdSOliver Schinagl { 10450e0d5e6SHans de Goede int ret; 1055c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50); 1065c7f10fdSOliver Schinagl 10750e0d5e6SHans de Goede if (mvolt == 0) 108*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 10950e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC5_EN); 11050e0d5e6SHans de Goede 11150e0d5e6SHans de Goede ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg); 11250e0d5e6SHans de Goede if (ret) 11350e0d5e6SHans de Goede return ret; 11450e0d5e6SHans de Goede 115*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 11650e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_DCDC5_EN); 1175c7f10fdSOliver Schinagl } 1185c7f10fdSOliver Schinagl 1195c7f10fdSOliver Schinagl int axp221_set_dldo1(unsigned int mvolt) 1205c7f10fdSOliver Schinagl { 1215c7f10fdSOliver Schinagl int ret; 1225c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 1235c7f10fdSOliver Schinagl 12450e0d5e6SHans de Goede if (mvolt == 0) 125*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, 12650e0d5e6SHans de Goede AXP221_OUTPUT_CTRL2_DLDO1_EN); 12750e0d5e6SHans de Goede 128bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg); 1295c7f10fdSOliver Schinagl if (ret) 1305c7f10fdSOliver Schinagl return ret; 1315c7f10fdSOliver Schinagl 132*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, 1335c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL2_DLDO1_EN); 1345c7f10fdSOliver Schinagl } 1355c7f10fdSOliver Schinagl 1365c7f10fdSOliver Schinagl int axp221_set_dldo2(unsigned int mvolt) 1375c7f10fdSOliver Schinagl { 1385c7f10fdSOliver Schinagl int ret; 1395c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 1405c7f10fdSOliver Schinagl 14150e0d5e6SHans de Goede if (mvolt == 0) 142*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, 14350e0d5e6SHans de Goede AXP221_OUTPUT_CTRL2_DLDO2_EN); 14450e0d5e6SHans de Goede 145bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg); 1465c7f10fdSOliver Schinagl if (ret) 1475c7f10fdSOliver Schinagl return ret; 1485c7f10fdSOliver Schinagl 149*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, 1505c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL2_DLDO2_EN); 1515c7f10fdSOliver Schinagl } 1525c7f10fdSOliver Schinagl 1535c7f10fdSOliver Schinagl int axp221_set_dldo3(unsigned int mvolt) 1545c7f10fdSOliver Schinagl { 1555c7f10fdSOliver Schinagl int ret; 1565c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 1575c7f10fdSOliver Schinagl 15850e0d5e6SHans de Goede if (mvolt == 0) 159*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, 16050e0d5e6SHans de Goede AXP221_OUTPUT_CTRL2_DLDO3_EN); 16150e0d5e6SHans de Goede 162bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg); 1635c7f10fdSOliver Schinagl if (ret) 1645c7f10fdSOliver Schinagl return ret; 1655c7f10fdSOliver Schinagl 166*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, 1675c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL2_DLDO3_EN); 1685c7f10fdSOliver Schinagl } 1695c7f10fdSOliver Schinagl 1705c7f10fdSOliver Schinagl int axp221_set_dldo4(unsigned int mvolt) 1715c7f10fdSOliver Schinagl { 1725c7f10fdSOliver Schinagl int ret; 1735c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 1745c7f10fdSOliver Schinagl 17550e0d5e6SHans de Goede if (mvolt == 0) 176*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, 17750e0d5e6SHans de Goede AXP221_OUTPUT_CTRL2_DLDO4_EN); 17850e0d5e6SHans de Goede 179bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg); 1805c7f10fdSOliver Schinagl if (ret) 1815c7f10fdSOliver Schinagl return ret; 1825c7f10fdSOliver Schinagl 183*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, 1845c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL2_DLDO4_EN); 1855c7f10fdSOliver Schinagl } 1865c7f10fdSOliver Schinagl 1875c7f10fdSOliver Schinagl int axp221_set_aldo1(unsigned int mvolt) 1885c7f10fdSOliver Schinagl { 1895c7f10fdSOliver Schinagl int ret; 1905c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 1915c7f10fdSOliver Schinagl 19250e0d5e6SHans de Goede if (mvolt == 0) 193*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 19450e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_ALDO1_EN); 19550e0d5e6SHans de Goede 196bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg); 1975c7f10fdSOliver Schinagl if (ret) 1985c7f10fdSOliver Schinagl return ret; 1995c7f10fdSOliver Schinagl 200*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 2015c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL1_ALDO1_EN); 2025c7f10fdSOliver Schinagl } 2035c7f10fdSOliver Schinagl 2045c7f10fdSOliver Schinagl int axp221_set_aldo2(unsigned int mvolt) 2055c7f10fdSOliver Schinagl { 2065c7f10fdSOliver Schinagl int ret; 2075c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 2085c7f10fdSOliver Schinagl 20950e0d5e6SHans de Goede if (mvolt == 0) 210*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1, 21150e0d5e6SHans de Goede AXP221_OUTPUT_CTRL1_ALDO2_EN); 21250e0d5e6SHans de Goede 213bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg); 2145c7f10fdSOliver Schinagl if (ret) 2155c7f10fdSOliver Schinagl return ret; 2165c7f10fdSOliver Schinagl 217*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL1, 2185c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL1_ALDO2_EN); 2195c7f10fdSOliver Schinagl } 2205c7f10fdSOliver Schinagl 2215c7f10fdSOliver Schinagl int axp221_set_aldo3(unsigned int mvolt) 2225c7f10fdSOliver Schinagl { 2235c7f10fdSOliver Schinagl int ret; 2245c7f10fdSOliver Schinagl u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 2255c7f10fdSOliver Schinagl 22650e0d5e6SHans de Goede if (mvolt == 0) 227*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL3, 22850e0d5e6SHans de Goede AXP221_OUTPUT_CTRL3_ALDO3_EN); 22950e0d5e6SHans de Goede 230bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg); 2315c7f10fdSOliver Schinagl if (ret) 2325c7f10fdSOliver Schinagl return ret; 2335c7f10fdSOliver Schinagl 234*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL3, 2355c7f10fdSOliver Schinagl AXP221_OUTPUT_CTRL3_ALDO3_EN); 2365c7f10fdSOliver Schinagl } 2375c7f10fdSOliver Schinagl 2386906df1aSSiarhei Siamashka int axp221_set_eldo(int eldo_num, unsigned int mvolt) 2396906df1aSSiarhei Siamashka { 2406906df1aSSiarhei Siamashka int ret; 2416906df1aSSiarhei Siamashka u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); 2426906df1aSSiarhei Siamashka u8 addr, bits; 2436906df1aSSiarhei Siamashka 2446906df1aSSiarhei Siamashka switch (eldo_num) { 2456906df1aSSiarhei Siamashka case 3: 2466906df1aSSiarhei Siamashka addr = AXP221_ELDO3_CTRL; 2476906df1aSSiarhei Siamashka bits = AXP221_OUTPUT_CTRL2_ELDO3_EN; 2486906df1aSSiarhei Siamashka break; 2496906df1aSSiarhei Siamashka case 2: 2506906df1aSSiarhei Siamashka addr = AXP221_ELDO2_CTRL; 2516906df1aSSiarhei Siamashka bits = AXP221_OUTPUT_CTRL2_ELDO2_EN; 2526906df1aSSiarhei Siamashka break; 2536906df1aSSiarhei Siamashka case 1: 2546906df1aSSiarhei Siamashka addr = AXP221_ELDO1_CTRL; 2556906df1aSSiarhei Siamashka bits = AXP221_OUTPUT_CTRL2_ELDO1_EN; 2566906df1aSSiarhei Siamashka break; 2576906df1aSSiarhei Siamashka default: 2586906df1aSSiarhei Siamashka return -EINVAL; 2596906df1aSSiarhei Siamashka } 2606906df1aSSiarhei Siamashka 2616906df1aSSiarhei Siamashka if (mvolt == 0) 262*1d624a4fSHans de Goede return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits); 2636906df1aSSiarhei Siamashka 2646906df1aSSiarhei Siamashka ret = pmic_bus_write(addr, cfg); 2656906df1aSSiarhei Siamashka if (ret) 2666906df1aSSiarhei Siamashka return ret; 2676906df1aSSiarhei Siamashka 268*1d624a4fSHans de Goede return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits); 2696906df1aSSiarhei Siamashka } 2706906df1aSSiarhei Siamashka 2715c7f10fdSOliver Schinagl int axp221_init(void) 2725c7f10fdSOliver Schinagl { 2733c781190SHans de Goede /* This cannot be 0 because it is used in SPL before BSS is ready */ 2743c781190SHans de Goede static int needs_init = 1; 2755c7f10fdSOliver Schinagl u8 axp_chip_id; 2765c7f10fdSOliver Schinagl int ret; 2775c7f10fdSOliver Schinagl 2783c781190SHans de Goede if (!needs_init) 2793c781190SHans de Goede return 0; 2803c781190SHans de Goede 281bdcdf846SHans de Goede ret = pmic_bus_init(); 2825c7f10fdSOliver Schinagl if (ret) 2835c7f10fdSOliver Schinagl return ret; 2845c7f10fdSOliver Schinagl 285bdcdf846SHans de Goede ret = pmic_bus_read(AXP221_CHIP_ID, &axp_chip_id); 2865c7f10fdSOliver Schinagl if (ret) 2875c7f10fdSOliver Schinagl return ret; 2885c7f10fdSOliver Schinagl 2895c7f10fdSOliver Schinagl if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17)) 2905c7f10fdSOliver Schinagl return -ENODEV; 2915c7f10fdSOliver Schinagl 2923c781190SHans de Goede needs_init = 0; 2935c7f10fdSOliver Schinagl return 0; 2945c7f10fdSOliver Schinagl } 295f3fba566SHans de Goede 296f3fba566SHans de Goede int axp221_get_sid(unsigned int *sid) 297f3fba566SHans de Goede { 298f3fba566SHans de Goede u8 *dest = (u8 *)sid; 299f3fba566SHans de Goede int i, ret; 300f3fba566SHans de Goede 301f3fba566SHans de Goede ret = axp221_init(); 302f3fba566SHans de Goede if (ret) 303f3fba566SHans de Goede return ret; 304f3fba566SHans de Goede 305bdcdf846SHans de Goede ret = pmic_bus_write(AXP221_PAGE, 1); 306f3fba566SHans de Goede if (ret) 307f3fba566SHans de Goede return ret; 308f3fba566SHans de Goede 309f3fba566SHans de Goede for (i = 0; i < 16; i++) { 310bdcdf846SHans de Goede ret = pmic_bus_read(AXP221_SID + i, &dest[i]); 311f3fba566SHans de Goede if (ret) 312f3fba566SHans de Goede return ret; 313f3fba566SHans de Goede } 314f3fba566SHans de Goede 315bdcdf846SHans de Goede pmic_bus_write(AXP221_PAGE, 0); 316f3fba566SHans de Goede 317f3fba566SHans de Goede for (i = 0; i < 4; i++) 318f3fba566SHans de Goede sid[i] = be32_to_cpu(sid[i]); 319f3fba566SHans de Goede 320f3fba566SHans de Goede return 0; 321f3fba566SHans de Goede } 3222abac621SHans de Goede 32312ce1553SHans de Goede int axp_gpio_direction_input(struct udevice *dev, unsigned pin) 324f7c7ab63SPaul Kocialkowski { 325f7c7ab63SPaul Kocialkowski switch (pin) { 326f7c7ab63SPaul Kocialkowski case SUNXI_GPIO_AXP0_VBUS_DETECT: 327f7c7ab63SPaul Kocialkowski return 0; 328f7c7ab63SPaul Kocialkowski default: 329f7c7ab63SPaul Kocialkowski return -EINVAL; 330f7c7ab63SPaul Kocialkowski } 331f7c7ab63SPaul Kocialkowski } 332f7c7ab63SPaul Kocialkowski 33312ce1553SHans de Goede int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int val) 334f7c7ab63SPaul Kocialkowski { 335f7c7ab63SPaul Kocialkowski int ret; 336f7c7ab63SPaul Kocialkowski 337f7c7ab63SPaul Kocialkowski switch (pin) { 338f7c7ab63SPaul Kocialkowski case SUNXI_GPIO_AXP0_VBUS_ENABLE: 339f7c7ab63SPaul Kocialkowski ret = axp221_clrbits(AXP221_MISC_CTRL, 340f7c7ab63SPaul Kocialkowski AXP221_MISC_CTRL_N_VBUSEN_FUNC); 341f7c7ab63SPaul Kocialkowski if (ret) 342f7c7ab63SPaul Kocialkowski return ret; 343f7c7ab63SPaul Kocialkowski 34412ce1553SHans de Goede return axp_gpio_set_value(dev, pin, val); 345f7c7ab63SPaul Kocialkowski default: 346f7c7ab63SPaul Kocialkowski return -EINVAL; 347f7c7ab63SPaul Kocialkowski } 348f7c7ab63SPaul Kocialkowski } 349f7c7ab63SPaul Kocialkowski 35012ce1553SHans de Goede int axp_gpio_get_value(struct udevice *dev, unsigned pin) 3511986c4caSChen-Yu Tsai { 3521986c4caSChen-Yu Tsai int ret; 3531986c4caSChen-Yu Tsai u8 val; 3541986c4caSChen-Yu Tsai 355f7c7ab63SPaul Kocialkowski switch (pin) { 356f7c7ab63SPaul Kocialkowski case SUNXI_GPIO_AXP0_VBUS_DETECT: 3571986c4caSChen-Yu Tsai ret = pmic_bus_read(AXP221_POWER_STATUS, &val); 3581986c4caSChen-Yu Tsai if (ret) 3591986c4caSChen-Yu Tsai return ret; 3601986c4caSChen-Yu Tsai 361750d49f5SHans de Goede return !!(val & AXP221_POWER_STATUS_VBUS_AVAIL); 362f7c7ab63SPaul Kocialkowski default: 363f7c7ab63SPaul Kocialkowski return -EINVAL; 364f7c7ab63SPaul Kocialkowski } 3651986c4caSChen-Yu Tsai } 3661986c4caSChen-Yu Tsai 36712ce1553SHans de Goede int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val) 3682abac621SHans de Goede { 3692abac621SHans de Goede int ret; 3702abac621SHans de Goede 371f7c7ab63SPaul Kocialkowski switch (pin) { 372f7c7ab63SPaul Kocialkowski case SUNXI_GPIO_AXP0_VBUS_ENABLE: 373f7c7ab63SPaul Kocialkowski if (val) 374f7c7ab63SPaul Kocialkowski ret = axp221_setbits(AXP221_VBUS_IPSOUT, 375f7c7ab63SPaul Kocialkowski AXP221_VBUS_IPSOUT_DRIVEBUS); 376f7c7ab63SPaul Kocialkowski else 377f7c7ab63SPaul Kocialkowski ret = axp221_clrbits(AXP221_VBUS_IPSOUT, 378f7c7ab63SPaul Kocialkowski AXP221_VBUS_IPSOUT_DRIVEBUS); 379f7c7ab63SPaul Kocialkowski 3802abac621SHans de Goede if (ret) 3812abac621SHans de Goede return ret; 3822abac621SHans de Goede } 3832abac621SHans de Goede 384f7c7ab63SPaul Kocialkowski return 0; 3852abac621SHans de Goede } 386