1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 #include <fdtdec.h> 12 13 #include "pinctrl-rockchip.h" 14 15 #define MAX_ROCKCHIP_PINS_ENTRIES 30 16 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 17 #define RK_FUNC_GPIO 0 18 19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 20 { 21 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 23 24 if (bank >= ctrl->nr_banks) { 25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 26 return -EINVAL; 27 } 28 29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 30 debug("pin conf pin %d >= %d\n", pin, 31 MAX_ROCKCHIP_GPIO_PER_BANK); 32 return -EINVAL; 33 } 34 35 return 0; 36 } 37 38 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 39 int *reg, u8 *bit, int *mask) 40 { 41 struct rockchip_pinctrl_priv *priv = bank->priv; 42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 43 struct rockchip_mux_recalced_data *data; 44 int i; 45 46 for (i = 0; i < ctrl->niomux_recalced; i++) { 47 data = &ctrl->iomux_recalced[i]; 48 if (data->num == bank->bank_num && 49 data->pin == pin) 50 break; 51 } 52 53 if (i >= ctrl->niomux_recalced) 54 return; 55 56 *reg = data->reg; 57 *mask = data->mask; 58 *bit = data->bit; 59 } 60 61 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 62 int mux, u32 *reg, u32 *value) 63 { 64 struct rockchip_pinctrl_priv *priv = bank->priv; 65 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 66 struct rockchip_mux_route_data *data; 67 int i; 68 69 for (i = 0; i < ctrl->niomux_routes; i++) { 70 data = &ctrl->iomux_routes[i]; 71 if (data->bank_num == bank->bank_num && 72 data->pin == pin && data->func == mux) 73 break; 74 } 75 76 if (i >= ctrl->niomux_routes) 77 return false; 78 79 *reg = data->route_offset; 80 *value = data->route_val; 81 82 return true; 83 } 84 85 static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) 86 { 87 int offset = 0; 88 89 if (mux_type & IOMUX_WIDTH_4BIT) { 90 if ((pin % 8) >= 4) 91 offset = 0x4; 92 *bit = (pin % 4) * 4; 93 *mask = 0xf; 94 } else if (mux_type & IOMUX_WIDTH_3BIT) { 95 /* 96 * pin0 ~ pin4 are at first register, and 97 * pin5 ~ pin7 are at second register. 98 */ 99 if ((pin % 8) >= 5) 100 offset = 0x4; 101 *bit = (pin % 8 % 5) * 3; 102 *mask = 0x7; 103 } else { 104 *bit = (pin % 8) * 2; 105 *mask = 0x3; 106 } 107 108 return offset; 109 } 110 111 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 112 { 113 struct rockchip_pinctrl_priv *priv = bank->priv; 114 int iomux_num = (pin / 8); 115 struct regmap *regmap; 116 unsigned int val; 117 int reg, ret, mask, mux_type; 118 u8 bit; 119 120 if (iomux_num > 3) 121 return -EINVAL; 122 123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 124 debug("pin %d is unrouted\n", pin); 125 return -EINVAL; 126 } 127 128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 129 return RK_FUNC_GPIO; 130 131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 132 ? priv->regmap_pmu : priv->regmap_base; 133 134 /* get basic quadrupel of mux registers and the correct reg inside */ 135 mux_type = bank->iomux[iomux_num].type; 136 reg = bank->iomux[iomux_num].offset; 137 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 138 139 if (bank->recalced_mask & BIT(pin)) 140 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 141 142 ret = regmap_read(regmap, reg, &val); 143 if (ret) 144 return ret; 145 146 return ((val >> bit) & mask); 147 } 148 149 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 150 int index) 151 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 152 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 153 154 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 155 } 156 157 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 158 int pin, int mux) 159 { 160 int iomux_num = (pin / 8); 161 162 if (iomux_num > 3) 163 return -EINVAL; 164 165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 166 debug("pin %d is unrouted\n", pin); 167 return -EINVAL; 168 } 169 170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 171 if (mux != IOMUX_GPIO_ONLY) { 172 debug("pin %d only supports a gpio mux\n", pin); 173 return -ENOTSUPP; 174 } 175 } 176 177 return 0; 178 } 179 180 /* 181 * Set a new mux function for a pin. 182 * 183 * The register is divided into the upper and lower 16 bit. When changing 184 * a value, the previous register value is not read and changed. Instead 185 * it seems the changed bits are marked in the upper 16 bit, while the 186 * changed value gets set in the same offset in the lower 16 bit. 187 * All pin settings seem to be 2 bit wide in both the upper and lower 188 * parts. 189 * @bank: pin bank to change 190 * @pin: pin to change 191 * @mux: new mux function to set 192 */ 193 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 194 { 195 struct rockchip_pinctrl_priv *priv = bank->priv; 196 int iomux_num = (pin / 8); 197 struct regmap *regmap; 198 int reg, ret, mask, mux_type; 199 u8 bit; 200 u32 data, route_reg, route_val; 201 202 ret = rockchip_verify_mux(bank, pin, mux); 203 if (ret < 0) 204 return ret; 205 206 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 207 return 0; 208 209 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 210 211 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 212 ? priv->regmap_pmu : priv->regmap_base; 213 214 /* get basic quadrupel of mux registers and the correct reg inside */ 215 mux_type = bank->iomux[iomux_num].type; 216 reg = bank->iomux[iomux_num].offset; 217 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 218 219 if (bank->recalced_mask & BIT(pin)) 220 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 221 222 if (bank->route_mask & BIT(pin)) { 223 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 224 &route_val)) { 225 ret = regmap_write(regmap, route_reg, route_val); 226 if (ret) 227 return ret; 228 } 229 } 230 231 data = (mask << (bit + 16)); 232 data |= (mux & mask) << bit; 233 ret = regmap_write(regmap, reg, data); 234 235 return ret; 236 } 237 238 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 239 { 2, 4, 8, 12, -1, -1, -1, -1 }, 240 { 3, 6, 9, 12, -1, -1, -1, -1 }, 241 { 5, 10, 15, 20, -1, -1, -1, -1 }, 242 { 4, 6, 8, 10, 12, 14, 16, 18 }, 243 { 4, 7, 10, 13, 16, 19, 22, 26 } 244 }; 245 246 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 247 int pin_num, int strength) 248 { 249 struct rockchip_pinctrl_priv *priv = bank->priv; 250 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 251 struct regmap *regmap; 252 int reg, ret, i; 253 u32 data, rmask_bits, temp; 254 u8 bit; 255 int drv_type = bank->drv[pin_num / 8].drv_type; 256 257 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 258 pin_num, strength); 259 260 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 261 262 ret = -EINVAL; 263 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 264 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 265 ret = i; 266 break; 267 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 268 ret = rockchip_perpin_drv_list[drv_type][i]; 269 break; 270 } 271 } 272 273 if (ret < 0) { 274 debug("unsupported driver strength %d\n", strength); 275 return ret; 276 } 277 278 switch (drv_type) { 279 case DRV_TYPE_IO_1V8_3V0_AUTO: 280 case DRV_TYPE_IO_3V3_ONLY: 281 rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; 282 switch (bit) { 283 case 0 ... 12: 284 /* regular case, nothing to do */ 285 break; 286 case 15: 287 /* 288 * drive-strength offset is special, as it is spread 289 * over 2 registers, the bit data[15] contains bit 0 290 * of the value while temp[1:0] contains bits 2 and 1 291 */ 292 data = (ret & 0x1) << 15; 293 temp = (ret >> 0x1) & 0x3; 294 295 data |= BIT(31); 296 ret = regmap_write(regmap, reg, data); 297 if (ret) 298 return ret; 299 300 temp |= (0x3 << 16); 301 reg += 0x4; 302 ret = regmap_write(regmap, reg, temp); 303 304 return ret; 305 case 18 ... 21: 306 /* setting fully enclosed in the second register */ 307 reg += 4; 308 bit -= 16; 309 break; 310 default: 311 debug("unsupported bit: %d for pinctrl drive type: %d\n", 312 bit, drv_type); 313 return -EINVAL; 314 } 315 break; 316 case DRV_TYPE_IO_DEFAULT: 317 case DRV_TYPE_IO_1V8_OR_3V0: 318 case DRV_TYPE_IO_1V8_ONLY: 319 rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; 320 break; 321 default: 322 debug("unsupported pinctrl drive type: %d\n", 323 drv_type); 324 return -EINVAL; 325 } 326 327 /* enable the write to the equivalent lower bits */ 328 data = ((1 << rmask_bits) - 1) << (bit + 16); 329 data |= (ret << bit); 330 331 ret = regmap_write(regmap, reg, data); 332 return ret; 333 } 334 335 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 336 { 337 PIN_CONFIG_BIAS_DISABLE, 338 PIN_CONFIG_BIAS_PULL_UP, 339 PIN_CONFIG_BIAS_PULL_DOWN, 340 PIN_CONFIG_BIAS_BUS_HOLD 341 }, 342 { 343 PIN_CONFIG_BIAS_DISABLE, 344 PIN_CONFIG_BIAS_PULL_DOWN, 345 PIN_CONFIG_BIAS_DISABLE, 346 PIN_CONFIG_BIAS_PULL_UP 347 }, 348 }; 349 350 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 351 int pin_num, int pull) 352 { 353 struct rockchip_pinctrl_priv *priv = bank->priv; 354 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 355 struct regmap *regmap; 356 int reg, ret, i, pull_type; 357 u8 bit; 358 u32 data; 359 360 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 361 pin_num, pull); 362 363 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 364 365 switch (ctrl->type) { 366 case RK3036: 367 case RK3128: 368 data = BIT(bit + 16); 369 if (pull == PIN_CONFIG_BIAS_DISABLE) 370 data |= BIT(bit); 371 ret = regmap_write(regmap, reg, data); 372 break; 373 case RV1108: 374 case RK3188: 375 case RK3288: 376 case RK3368: 377 case RK3399: 378 pull_type = bank->pull_type[pin_num / 8]; 379 ret = -EINVAL; 380 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 381 i++) { 382 if (rockchip_pull_list[pull_type][i] == pull) { 383 ret = i; 384 break; 385 } 386 } 387 388 if (ret < 0) { 389 debug("unsupported pull setting %d\n", pull); 390 return ret; 391 } 392 393 /* enable the write to the equivalent lower bits */ 394 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 395 data |= (ret << bit); 396 397 ret = regmap_write(regmap, reg, data); 398 break; 399 default: 400 debug("unsupported pinctrl type\n"); 401 return -EINVAL; 402 } 403 404 return ret; 405 } 406 407 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 408 int pin_num, int enable) 409 { 410 struct rockchip_pinctrl_priv *priv = bank->priv; 411 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 412 struct regmap *regmap; 413 int reg, ret; 414 u8 bit; 415 u32 data; 416 417 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 418 pin_num, enable); 419 420 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 421 if (ret) 422 return ret; 423 424 /* enable the write to the equivalent lower bits */ 425 data = BIT(bit + 16) | (enable << bit); 426 427 return regmap_write(regmap, reg, data); 428 } 429 430 /* 431 * Pinconf_ops handling 432 */ 433 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 434 unsigned int pull) 435 { 436 switch (ctrl->type) { 437 case RK3036: 438 case RK3128: 439 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 440 pull == PIN_CONFIG_BIAS_DISABLE); 441 case RV1108: 442 case RK3188: 443 case RK3288: 444 case RK3368: 445 case RK3399: 446 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 447 } 448 449 return false; 450 } 451 452 /* set the pin config settings for a specified pin */ 453 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 454 u32 pin, u32 param, u32 arg) 455 { 456 struct rockchip_pinctrl_priv *priv = bank->priv; 457 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 458 int rc; 459 460 switch (param) { 461 case PIN_CONFIG_BIAS_DISABLE: 462 rc = rockchip_set_pull(bank, pin, param); 463 if (rc) 464 return rc; 465 break; 466 467 case PIN_CONFIG_BIAS_PULL_UP: 468 case PIN_CONFIG_BIAS_PULL_DOWN: 469 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 470 case PIN_CONFIG_BIAS_BUS_HOLD: 471 if (!rockchip_pinconf_pull_valid(ctrl, param)) 472 return -ENOTSUPP; 473 474 if (!arg) 475 return -EINVAL; 476 477 rc = rockchip_set_pull(bank, pin, param); 478 if (rc) 479 return rc; 480 break; 481 482 case PIN_CONFIG_DRIVE_STRENGTH: 483 if (!ctrl->drv_calc_reg) 484 return -ENOTSUPP; 485 486 rc = rockchip_set_drive_perpin(bank, pin, arg); 487 if (rc < 0) 488 return rc; 489 break; 490 491 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 492 if (!ctrl->schmitt_calc_reg) 493 return -ENOTSUPP; 494 495 rc = rockchip_set_schmitt(bank, pin, arg); 496 if (rc < 0) 497 return rc; 498 break; 499 500 default: 501 break; 502 } 503 504 return 0; 505 } 506 507 static const struct pinconf_param rockchip_conf_params[] = { 508 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 509 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 510 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 511 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 512 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 513 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 514 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 515 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 516 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 517 }; 518 519 static int rockchip_pinconf_prop_name_to_param(const char *property, 520 u32 *default_value) 521 { 522 const struct pinconf_param *p, *end; 523 524 p = rockchip_conf_params; 525 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 526 527 /* See if this pctldev supports this parameter */ 528 for (; p < end; p++) { 529 if (!strcmp(property, p->property)) { 530 *default_value = p->default_value; 531 return p->param; 532 } 533 } 534 535 *default_value = 0; 536 return -EPERM; 537 } 538 539 static int rockchip_pinctrl_set_state(struct udevice *dev, 540 struct udevice *config) 541 { 542 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 543 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 544 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 545 u32 bank, pin, mux, conf, arg, default_val; 546 int ret, count, i; 547 const char *prop_name; 548 const void *value; 549 int prop_len, param; 550 const u32 *data; 551 ofnode node; 552 #ifdef CONFIG_OF_LIVE 553 const struct device_node *np; 554 struct property *pp; 555 #else 556 int property_offset, pcfg_node; 557 const void *blob = gd->fdt_blob; 558 #endif 559 data = dev_read_prop(config, "rockchip,pins", &count); 560 if (count < 0) { 561 debug("%s: bad array size %d\n", __func__, count); 562 return -EINVAL; 563 } 564 565 count /= sizeof(u32); 566 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 567 debug("%s: unsupported pins array count %d\n", 568 __func__, count); 569 return -EINVAL; 570 } 571 572 for (i = 0; i < count; i++) 573 cells[i] = fdt32_to_cpu(data[i]); 574 575 for (i = 0; i < (count >> 2); i++) { 576 bank = cells[4 * i + 0]; 577 pin = cells[4 * i + 1]; 578 mux = cells[4 * i + 2]; 579 conf = cells[4 * i + 3]; 580 581 ret = rockchip_verify_config(dev, bank, pin); 582 if (ret) 583 return ret; 584 585 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 586 if (ret) 587 return ret; 588 589 node = ofnode_get_by_phandle(conf); 590 if (!ofnode_valid(node)) 591 return -ENODEV; 592 #ifdef CONFIG_OF_LIVE 593 np = ofnode_to_np(node); 594 for (pp = np->properties; pp; pp = pp->next) { 595 prop_name = pp->name; 596 prop_len = pp->length; 597 value = pp->value; 598 #else 599 pcfg_node = ofnode_to_offset(node); 600 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 601 value = fdt_getprop_by_offset(blob, property_offset, 602 &prop_name, &prop_len); 603 if (!value) 604 return -ENOENT; 605 #endif 606 param = rockchip_pinconf_prop_name_to_param(prop_name, 607 &default_val); 608 if (param < 0) 609 break; 610 611 if (prop_len >= sizeof(fdt32_t)) 612 arg = fdt32_to_cpu(*(fdt32_t *)value); 613 else 614 arg = default_val; 615 616 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 617 param, arg); 618 if (ret) { 619 debug("%s: rockchip_pinconf_set fail: %d\n", 620 __func__, ret); 621 return ret; 622 } 623 } 624 } 625 626 return 0; 627 } 628 629 const struct pinctrl_ops rockchip_pinctrl_ops = { 630 .set_state = rockchip_pinctrl_set_state, 631 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 632 }; 633 634 /* retrieve the soc specific data */ 635 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 636 { 637 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 638 struct rockchip_pin_ctrl *ctrl = 639 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 640 struct rockchip_pin_bank *bank; 641 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 642 643 grf_offs = ctrl->grf_mux_offset; 644 pmu_offs = ctrl->pmu_mux_offset; 645 drv_pmu_offs = ctrl->pmu_drv_offset; 646 drv_grf_offs = ctrl->grf_drv_offset; 647 bank = ctrl->pin_banks; 648 649 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 650 int bank_pins = 0; 651 652 bank->priv = priv; 653 bank->pin_base = ctrl->nr_pins; 654 ctrl->nr_pins += bank->nr_pins; 655 656 /* calculate iomux and drv offsets */ 657 for (j = 0; j < 4; j++) { 658 struct rockchip_iomux *iom = &bank->iomux[j]; 659 struct rockchip_drv *drv = &bank->drv[j]; 660 int inc; 661 662 if (bank_pins >= bank->nr_pins) 663 break; 664 665 /* preset iomux offset value, set new start value */ 666 if (iom->offset >= 0) { 667 if (iom->type & IOMUX_SOURCE_PMU) 668 pmu_offs = iom->offset; 669 else 670 grf_offs = iom->offset; 671 } else { /* set current iomux offset */ 672 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 673 pmu_offs : grf_offs; 674 } 675 676 /* preset drv offset value, set new start value */ 677 if (drv->offset >= 0) { 678 if (iom->type & IOMUX_SOURCE_PMU) 679 drv_pmu_offs = drv->offset; 680 else 681 drv_grf_offs = drv->offset; 682 } else { /* set current drv offset */ 683 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 684 drv_pmu_offs : drv_grf_offs; 685 } 686 687 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 688 i, j, iom->offset, drv->offset); 689 690 /* 691 * Increase offset according to iomux width. 692 * 4bit iomux'es are spread over two registers. 693 */ 694 inc = (iom->type & (IOMUX_WIDTH_4BIT | 695 IOMUX_WIDTH_3BIT)) ? 8 : 4; 696 if (iom->type & IOMUX_SOURCE_PMU) 697 pmu_offs += inc; 698 else 699 grf_offs += inc; 700 701 /* 702 * Increase offset according to drv width. 703 * 3bit drive-strenth'es are spread over two registers. 704 */ 705 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 706 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 707 inc = 8; 708 else 709 inc = 4; 710 711 if (iom->type & IOMUX_SOURCE_PMU) 712 drv_pmu_offs += inc; 713 else 714 drv_grf_offs += inc; 715 716 bank_pins += 8; 717 } 718 719 /* calculate the per-bank recalced_mask */ 720 for (j = 0; j < ctrl->niomux_recalced; j++) { 721 int pin = 0; 722 723 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 724 pin = ctrl->iomux_recalced[j].pin; 725 bank->recalced_mask |= BIT(pin); 726 } 727 } 728 729 /* calculate the per-bank route_mask */ 730 for (j = 0; j < ctrl->niomux_routes; j++) { 731 int pin = 0; 732 733 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 734 pin = ctrl->iomux_routes[j].pin; 735 bank->route_mask |= BIT(pin); 736 } 737 } 738 } 739 740 return ctrl; 741 } 742 743 int rockchip_pinctrl_probe(struct udevice *dev) 744 { 745 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 746 struct rockchip_pin_ctrl *ctrl; 747 struct udevice *syscon; 748 struct regmap *regmap; 749 int ret = 0; 750 751 /* get rockchip grf syscon phandle */ 752 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 753 &syscon); 754 if (ret) { 755 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 756 return ret; 757 } 758 759 /* get grf-reg base address */ 760 regmap = syscon_get_regmap(syscon); 761 if (!regmap) { 762 debug("unable to find rockchip grf regmap\n"); 763 return -ENODEV; 764 } 765 priv->regmap_base = regmap; 766 767 /* option: get pmu-reg base address */ 768 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 769 &syscon); 770 if (!ret) { 771 /* get pmugrf-reg base address */ 772 regmap = syscon_get_regmap(syscon); 773 if (!regmap) { 774 debug("unable to find rockchip pmu regmap\n"); 775 return -ENODEV; 776 } 777 priv->regmap_pmu = regmap; 778 } 779 780 ctrl = rockchip_pinctrl_get_soc_data(dev); 781 if (!ctrl) { 782 debug("driver data not available\n"); 783 return -EINVAL; 784 } 785 786 priv->ctrl = ctrl; 787 return 0; 788 } 789