1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4  */
5 
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11 
12 #include "pinctrl-rockchip.h"
13 
14 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
15 	{
16 		.num = 2,
17 		.pin = 12,
18 		.reg = 0x24,
19 		.bit = 8,
20 		.mask = 0x3
21 	}, {
22 		.num = 2,
23 		.pin = 15,
24 		.reg = 0x28,
25 		.bit = 0,
26 		.mask = 0x7
27 	}, {
28 		.num = 2,
29 		.pin = 23,
30 		.reg = 0x30,
31 		.bit = 14,
32 		.mask = 0x3
33 	},
34 };
35 
36 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
37 	{
38 		/* uart2dbg_rxm0 */
39 		.bank_num = 1,
40 		.pin = 1,
41 		.func = 2,
42 		.route_offset = 0x50,
43 		.route_val = BIT(16) | BIT(16 + 1),
44 	}, {
45 		/* uart2dbg_rxm1 */
46 		.bank_num = 2,
47 		.pin = 1,
48 		.func = 1,
49 		.route_offset = 0x50,
50 		.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
51 	}, {
52 		/* gmac-m1_rxd0 */
53 		.bank_num = 1,
54 		.pin = 11,
55 		.func = 2,
56 		.route_offset = 0x50,
57 		.route_val = BIT(16 + 2) | BIT(2),
58 	}, {
59 		/* gmac-m1-optimized_rxd3 */
60 		.bank_num = 1,
61 		.pin = 14,
62 		.func = 2,
63 		.route_offset = 0x50,
64 		.route_val = BIT(16 + 10) | BIT(10),
65 	}, {
66 		/* pdm_sdi0m0 */
67 		.bank_num = 2,
68 		.pin = 19,
69 		.func = 2,
70 		.route_offset = 0x50,
71 		.route_val = BIT(16 + 3),
72 	}, {
73 		/* pdm_sdi0m1 */
74 		.bank_num = 1,
75 		.pin = 23,
76 		.func = 3,
77 		.route_offset = 0x50,
78 		.route_val =  BIT(16 + 3) | BIT(3),
79 	}, {
80 		/* spi_rxdm2 */
81 		.bank_num = 3,
82 		.pin = 2,
83 		.func = 4,
84 		.route_offset = 0x50,
85 		.route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
86 	}, {
87 		/* i2s2_sdim0 */
88 		.bank_num = 1,
89 		.pin = 24,
90 		.func = 1,
91 		.route_offset = 0x50,
92 		.route_val = BIT(16 + 6),
93 	}, {
94 		/* i2s2_sdim1 */
95 		.bank_num = 3,
96 		.pin = 2,
97 		.func = 6,
98 		.route_offset = 0x50,
99 		.route_val =  BIT(16 + 6) | BIT(6),
100 	}, {
101 		/* card_iom1 */
102 		.bank_num = 2,
103 		.pin = 22,
104 		.func = 3,
105 		.route_offset = 0x50,
106 		.route_val =  BIT(16 + 7) | BIT(7),
107 	}, {
108 		/* tsp_d5m1 */
109 		.bank_num = 2,
110 		.pin = 16,
111 		.func = 3,
112 		.route_offset = 0x50,
113 		.route_val =  BIT(16 + 8) | BIT(8),
114 	}, {
115 		/* cif_data5m1 */
116 		.bank_num = 2,
117 		.pin = 16,
118 		.func = 4,
119 		.route_offset = 0x50,
120 		.route_val =  BIT(16 + 9) | BIT(9),
121 	},
122 };
123 
124 #define RK3328_PULL_OFFSET		0x100
125 
126 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
127 					 int pin_num, struct regmap **regmap,
128 					 int *reg, u8 *bit)
129 {
130 	struct rockchip_pinctrl_priv *priv = bank->priv;
131 
132 	*regmap = priv->regmap_base;
133 	*reg = RK3328_PULL_OFFSET;
134 	*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
135 	*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
136 
137 	*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
138 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
139 }
140 
141 #define RK3328_DRV_GRF_OFFSET		0x200
142 
143 static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
144 					int pin_num, struct regmap **regmap,
145 					int *reg, u8 *bit)
146 {
147 	struct rockchip_pinctrl_priv *priv = bank->priv;
148 
149 	*regmap = priv->regmap_base;
150 	*reg = RK3328_DRV_GRF_OFFSET;
151 	*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
152 	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
153 
154 	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
155 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
156 }
157 
158 #define RK3328_SCHMITT_BITS_PER_PIN		1
159 #define RK3328_SCHMITT_PINS_PER_REG		16
160 #define RK3328_SCHMITT_BANK_STRIDE		8
161 #define RK3328_SCHMITT_GRF_OFFSET		0x380
162 
163 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
164 					   int pin_num,
165 					   struct regmap **regmap,
166 					   int *reg, u8 *bit)
167 {
168 	struct rockchip_pinctrl_priv *priv = bank->priv;
169 
170 	*regmap = priv->regmap_base;
171 	*reg = RK3328_SCHMITT_GRF_OFFSET;
172 
173 	*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
174 	*reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
175 	*bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
176 
177 	return 0;
178 }
179 
180 static struct rockchip_pin_bank rk3328_pin_banks[] = {
181 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
182 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
183 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
184 			     IOMUX_WIDTH_3BIT,
185 			     IOMUX_WIDTH_3BIT,
186 			     0),
187 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
188 			     IOMUX_WIDTH_3BIT,
189 			     IOMUX_WIDTH_3BIT,
190 			     0,
191 			     0),
192 };
193 
194 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
195 		.pin_banks		= rk3328_pin_banks,
196 		.nr_banks		= ARRAY_SIZE(rk3328_pin_banks),
197 		.label			= "RK3328-GPIO",
198 		.type			= RK3288,
199 		.grf_mux_offset		= 0x0,
200 		.iomux_recalced		= rk3328_mux_recalced_data,
201 		.niomux_recalced	= ARRAY_SIZE(rk3328_mux_recalced_data),
202 		.iomux_routes		= rk3328_mux_route_data,
203 		.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
204 		.pull_calc_reg		= rk3328_calc_pull_reg_and_bit,
205 		.drv_calc_reg		= rk3328_calc_drv_reg_and_bit,
206 		.schmitt_calc_reg	= rk3328_calc_schmitt_reg_and_bit,
207 };
208 
209 static const struct udevice_id rk3328_pinctrl_ids[] = {
210 	{
211 		.compatible = "rockchip,rk3328-pinctrl",
212 		.data = (ulong)&rk3328_pin_ctrl
213 	},
214 	{ }
215 };
216 
217 U_BOOT_DRIVER(pinctrl_rk3328) = {
218 	.name		= "rockchip_rk3328_pinctrl",
219 	.id		= UCLASS_PINCTRL,
220 	.of_match	= rk3328_pinctrl_ids,
221 	.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
222 	.ops		= &rockchip_pinctrl_ops,
223 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
224 	.bind		= dm_scan_fdt_dev,
225 #endif
226 	.probe		= rockchip_pinctrl_probe,
227 };
228