1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <dm/pinctrl.h> 9 #include <regmap.h> 10 #include <syscon.h> 11 12 #include "pinctrl-rockchip.h" 13 14 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 15 { 16 /* edphdmi_cecinoutt1 */ 17 .bank_num = 7, 18 .pin = 16, 19 .func = 2, 20 .route_offset = 0x264, 21 .route_val = BIT(16 + 12) | BIT(12), 22 }, { 23 /* edphdmi_cecinout */ 24 .bank_num = 7, 25 .pin = 23, 26 .func = 4, 27 .route_offset = 0x264, 28 .route_val = BIT(16 + 12), 29 }, 30 }; 31 32 #define RK3288_PULL_OFFSET 0x140 33 #define RK3288_PULL_PMU_OFFSET 0x64 34 35 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 36 int pin_num, struct regmap **regmap, 37 int *reg, u8 *bit) 38 { 39 struct rockchip_pinctrl_priv *priv = bank->priv; 40 41 /* The first 24 pins of the first bank are located in PMU */ 42 if (bank->bank_num == 0) { 43 *regmap = priv->regmap_pmu; 44 *reg = RK3288_PULL_PMU_OFFSET; 45 46 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 47 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; 48 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 49 } else { 50 *regmap = priv->regmap_base; 51 *reg = RK3288_PULL_OFFSET; 52 53 /* correct the offset, as we're starting with the 2nd bank */ 54 *reg -= 0x10; 55 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 56 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 57 58 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 59 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 60 } 61 } 62 63 #define RK3288_DRV_PMU_OFFSET 0x70 64 #define RK3288_DRV_GRF_OFFSET 0x1c0 65 66 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 67 int pin_num, struct regmap **regmap, 68 int *reg, u8 *bit) 69 { 70 struct rockchip_pinctrl_priv *priv = bank->priv; 71 72 /* The first 24 pins of the first bank are located in PMU */ 73 if (bank->bank_num == 0) { 74 *regmap = priv->regmap_pmu; 75 *reg = RK3288_DRV_PMU_OFFSET; 76 77 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 78 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; 79 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 80 } else { 81 *regmap = priv->regmap_base; 82 *reg = RK3288_DRV_GRF_OFFSET; 83 84 /* correct the offset, as we're starting with the 2nd bank */ 85 *reg -= 0x10; 86 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 87 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 88 89 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 90 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 91 } 92 } 93 94 static struct rockchip_pin_bank rk3288_pin_banks[] = { 95 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 96 IOMUX_SOURCE_PMU, 97 IOMUX_SOURCE_PMU, 98 IOMUX_UNROUTED 99 ), 100 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 101 IOMUX_UNROUTED, 102 IOMUX_UNROUTED, 103 0 104 ), 105 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 106 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 107 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 108 IOMUX_WIDTH_4BIT, 109 0, 110 0 111 ), 112 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 113 0, 114 0, 115 IOMUX_UNROUTED 116 ), 117 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 118 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 119 0, 120 IOMUX_WIDTH_4BIT, 121 IOMUX_UNROUTED 122 ), 123 PIN_BANK(8, 16, "gpio8"), 124 }; 125 126 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 127 .pin_banks = rk3288_pin_banks, 128 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 129 .label = "RK3288-GPIO", 130 .type = RK3288, 131 .grf_mux_offset = 0x0, 132 .pmu_mux_offset = 0x84, 133 .iomux_routes = rk3288_mux_route_data, 134 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 135 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 136 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 137 }; 138 139 static const struct udevice_id rk3288_pinctrl_ids[] = { 140 { 141 .compatible = "rockchip,rk3288-pinctrl", 142 .data = (ulong)&rk3288_pin_ctrl 143 }, 144 { } 145 }; 146 147 U_BOOT_DRIVER(pinctrl_rk3288) = { 148 .name = "rockchip_rk3288_pinctrl", 149 .id = UCLASS_PINCTRL, 150 .of_match = rk3288_pinctrl_ids, 151 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 152 .ops = &rockchip_pinctrl_ops, 153 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 154 .bind = dm_scan_fdt_dev, 155 #endif 156 .probe = rockchip_pinctrl_probe, 157 }; 158