1*e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+ 2*e7ae4cf2SDavid Wu /* 3*e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4*e7ae4cf2SDavid Wu */ 5*e7ae4cf2SDavid Wu 6*e7ae4cf2SDavid Wu #include <common.h> 7*e7ae4cf2SDavid Wu #include <dm.h> 8*e7ae4cf2SDavid Wu #include <dm/pinctrl.h> 9*e7ae4cf2SDavid Wu #include <regmap.h> 10*e7ae4cf2SDavid Wu #include <syscon.h> 11*e7ae4cf2SDavid Wu 12*e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h" 13*e7ae4cf2SDavid Wu 14*e7ae4cf2SDavid Wu static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 15*e7ae4cf2SDavid Wu { 16*e7ae4cf2SDavid Wu /* edphdmi_cecinoutt1 */ 17*e7ae4cf2SDavid Wu .bank_num = 7, 18*e7ae4cf2SDavid Wu .pin = 16, 19*e7ae4cf2SDavid Wu .func = 2, 20*e7ae4cf2SDavid Wu .route_offset = 0x264, 21*e7ae4cf2SDavid Wu .route_val = BIT(16 + 12) | BIT(12), 22*e7ae4cf2SDavid Wu }, { 23*e7ae4cf2SDavid Wu /* edphdmi_cecinout */ 24*e7ae4cf2SDavid Wu .bank_num = 7, 25*e7ae4cf2SDavid Wu .pin = 23, 26*e7ae4cf2SDavid Wu .func = 4, 27*e7ae4cf2SDavid Wu .route_offset = 0x264, 28*e7ae4cf2SDavid Wu .route_val = BIT(16 + 12), 29*e7ae4cf2SDavid Wu }, 30*e7ae4cf2SDavid Wu }; 31*e7ae4cf2SDavid Wu 32*e7ae4cf2SDavid Wu #define RK3288_PULL_OFFSET 0x140 33*e7ae4cf2SDavid Wu #define RK3288_PULL_PMU_OFFSET 0x64 34*e7ae4cf2SDavid Wu 35*e7ae4cf2SDavid Wu static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 36*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap, 37*e7ae4cf2SDavid Wu int *reg, u8 *bit) 38*e7ae4cf2SDavid Wu { 39*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv; 40*e7ae4cf2SDavid Wu 41*e7ae4cf2SDavid Wu /* The first 24 pins of the first bank are located in PMU */ 42*e7ae4cf2SDavid Wu if (bank->bank_num == 0) { 43*e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu; 44*e7ae4cf2SDavid Wu *reg = RK3288_PULL_PMU_OFFSET; 45*e7ae4cf2SDavid Wu 46*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 47*e7ae4cf2SDavid Wu *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; 48*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 49*e7ae4cf2SDavid Wu } else { 50*e7ae4cf2SDavid Wu *regmap = priv->regmap_base; 51*e7ae4cf2SDavid Wu *reg = RK3288_PULL_OFFSET; 52*e7ae4cf2SDavid Wu 53*e7ae4cf2SDavid Wu /* correct the offset, as we're starting with the 2nd bank */ 54*e7ae4cf2SDavid Wu *reg -= 0x10; 55*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 56*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 57*e7ae4cf2SDavid Wu 58*e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 59*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 60*e7ae4cf2SDavid Wu } 61*e7ae4cf2SDavid Wu } 62*e7ae4cf2SDavid Wu 63*e7ae4cf2SDavid Wu #define RK3288_DRV_PMU_OFFSET 0x70 64*e7ae4cf2SDavid Wu #define RK3288_DRV_GRF_OFFSET 0x1c0 65*e7ae4cf2SDavid Wu 66*e7ae4cf2SDavid Wu static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 67*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap, 68*e7ae4cf2SDavid Wu int *reg, u8 *bit) 69*e7ae4cf2SDavid Wu { 70*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv; 71*e7ae4cf2SDavid Wu 72*e7ae4cf2SDavid Wu /* The first 24 pins of the first bank are located in PMU */ 73*e7ae4cf2SDavid Wu if (bank->bank_num == 0) { 74*e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu; 75*e7ae4cf2SDavid Wu *reg = RK3288_DRV_PMU_OFFSET; 76*e7ae4cf2SDavid Wu 77*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 78*e7ae4cf2SDavid Wu *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; 79*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 80*e7ae4cf2SDavid Wu } else { 81*e7ae4cf2SDavid Wu *regmap = priv->regmap_base; 82*e7ae4cf2SDavid Wu *reg = RK3288_DRV_GRF_OFFSET; 83*e7ae4cf2SDavid Wu 84*e7ae4cf2SDavid Wu /* correct the offset, as we're starting with the 2nd bank */ 85*e7ae4cf2SDavid Wu *reg -= 0x10; 86*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 87*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 88*e7ae4cf2SDavid Wu 89*e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 90*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 91*e7ae4cf2SDavid Wu } 92*e7ae4cf2SDavid Wu } 93*e7ae4cf2SDavid Wu 94*e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3288_pin_banks[] = { 95*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 96*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU, 97*e7ae4cf2SDavid Wu IOMUX_SOURCE_PMU, 98*e7ae4cf2SDavid Wu IOMUX_UNROUTED 99*e7ae4cf2SDavid Wu ), 100*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 101*e7ae4cf2SDavid Wu IOMUX_UNROUTED, 102*e7ae4cf2SDavid Wu IOMUX_UNROUTED, 103*e7ae4cf2SDavid Wu 0 104*e7ae4cf2SDavid Wu ), 105*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 106*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 107*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 108*e7ae4cf2SDavid Wu IOMUX_WIDTH_4BIT, 109*e7ae4cf2SDavid Wu 0, 110*e7ae4cf2SDavid Wu 0 111*e7ae4cf2SDavid Wu ), 112*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 113*e7ae4cf2SDavid Wu 0, 114*e7ae4cf2SDavid Wu 0, 115*e7ae4cf2SDavid Wu IOMUX_UNROUTED 116*e7ae4cf2SDavid Wu ), 117*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 118*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 119*e7ae4cf2SDavid Wu 0, 120*e7ae4cf2SDavid Wu IOMUX_WIDTH_4BIT, 121*e7ae4cf2SDavid Wu IOMUX_UNROUTED 122*e7ae4cf2SDavid Wu ), 123*e7ae4cf2SDavid Wu PIN_BANK(8, 16, "gpio8"), 124*e7ae4cf2SDavid Wu }; 125*e7ae4cf2SDavid Wu 126*e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 127*e7ae4cf2SDavid Wu .pin_banks = rk3288_pin_banks, 128*e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 129*e7ae4cf2SDavid Wu .label = "RK3288-GPIO", 130*e7ae4cf2SDavid Wu .type = RK3288, 131*e7ae4cf2SDavid Wu .grf_mux_offset = 0x0, 132*e7ae4cf2SDavid Wu .pmu_mux_offset = 0x84, 133*e7ae4cf2SDavid Wu .iomux_routes = rk3288_mux_route_data, 134*e7ae4cf2SDavid Wu .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 135*e7ae4cf2SDavid Wu .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 136*e7ae4cf2SDavid Wu .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 137*e7ae4cf2SDavid Wu }; 138*e7ae4cf2SDavid Wu 139*e7ae4cf2SDavid Wu static const struct udevice_id rk3288_pinctrl_ids[] = { 140*e7ae4cf2SDavid Wu { 141*e7ae4cf2SDavid Wu .compatible = "rockchip,rk3288-pinctrl", 142*e7ae4cf2SDavid Wu .data = (ulong)&rk3288_pin_ctrl 143*e7ae4cf2SDavid Wu }, 144*e7ae4cf2SDavid Wu { } 145*e7ae4cf2SDavid Wu }; 146*e7ae4cf2SDavid Wu 147*e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rk3288) = { 148*e7ae4cf2SDavid Wu .name = "rockchip_rk3288_pinctrl", 149*e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL, 150*e7ae4cf2SDavid Wu .of_match = rk3288_pinctrl_ids, 151*e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 152*e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops, 153*e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA) 154*e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev, 155*e7ae4cf2SDavid Wu #endif 156*e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe, 157*e7ae4cf2SDavid Wu }; 158